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[None][perf] Fix the tactic sorting in TrtllmGenBatchedGemmRunner::getValidConfigIndices by jinyangyuan-nvidia · Pull Request #7419 · NVIDIA/TensorRT-LLM · GitHub
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@jinyangyuan-nvidia jinyangyuan-nvidia commented Sep 1, 2025

The tactic sorting in TrtllmGenBatchedGemmRunner::getValidConfigIndices may not be as expected because different criteria are applied in different sorting function calls. This PR fixes the issue by applying these criteria in the same sorting function call. Moreover, the number of CTAs is estimated using the modified getNumCtas to align with the kernel launch.

Summary by CodeRabbit

  • New Features

    • Added public capabilities to retrieve CTA/grid layout details and derive batched GEMM options at runtime.
    • Switched to dynamic CTA computation during launches, replacing previously stored counts.
  • Performance

    • Improved kernel configuration selection with device-aware (multi-processor) and CTA-aware scheduling for better efficiency across problem sizes.
  • Refactor

    • Unified tie-break and sorting logic for kernel configs into a single, consistent comparator.
    • Removed internal state for CTA counts in favor of on-demand computation.
    • Updated public interfaces to reflect dynamic option/CTA computation.

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📝 Walkthrough

Walkthrough

Introduces CTA/grid computation helpers and moves CTA counts to runtime. Updates BatchedGemmInterface API (add getCtaInfo, getOptionsFromConfigAndData; change getNumCtas signature; remove mNumCtas) and adjusts run() accordingly. Refactors KernelRunner config sorting into a single comparator that uses CTA-aware tie-breakers and SM count via cudaUtils.

Changes

Cohort / File(s) Summary
Kernel config selection and sorting refactor
cpp/tensorrt_llm/kernels/trtllmGenKernels/batchedGemm/KernelRunner.cpp
Added include for cudaUtils.h. Folds multiple tiered comparators into one lambda handling tileK, unroll flag, tileM/tileN, and scheduler preference using CTAs vs. SM count. Pulls options via getOptionsFromConfigAndData and CTAs via getNumCtas; reads multiProcessorCount. Uses single std::sort.
Batched GEMM CTA/grid API changes
cpp/tensorrt_llm/kernels/trtllmGenKernels/batchedGemm/trtllmGen_bmm_export/BatchedGemmInterface.h
Adds getCtaInfo(options, data) returning grid tuple and batchM; adds getOptionsFromConfigAndData(config, data). Changes getNumCtas to accept options and data and compute from getCtaInfo. Removes internal mNumCtas. Updates run() to call getCtaInfo and use returned grid components.

Sequence Diagram(s)

sequenceDiagram
  autonumber
  participant Caller
  participant KernelRunner
  participant Interface as BatchedGemmInterface
  participant HW as GPU/SM Info

  Caller->>KernelRunner: getValidConfigIndices(gemmData)
  KernelRunner->>HW: common::getMultiProcessorCount()
  HW-->>KernelRunner: multiProcessorCount
  loop Compare candidate configs
    KernelRunner->>Interface: getOptionsFromConfigAndData(config, gemmData)
    Interface-->>KernelRunner: BatchedGemmOptions
    KernelRunner->>Interface: getNumCtas(options, gemmData)
    Interface-->>KernelRunner: totalCTAs
    KernelRunner->>KernelRunner: cmpFunc tie-breaks (tileK, unroll, tileM/N, scheduler vs. SMs)
  end
  KernelRunner-->>Caller: sorted valid config indices
Loading
sequenceDiagram
  autonumber
  participant Caller
  participant Interface as BatchedGemmInterface
  participant Kernel as BatchedGemmKernel

  Caller->>Interface: run(config, data)
  Interface->>Interface: options = getOptionsFromConfigAndData(config, data)
  Interface->>Interface: (x,y,z,maxBatchCtas,batchM) = getCtaInfo(options, data)
  Interface->>Interface: totalCTAs = getNumCtas(options, data)
  Interface->>Kernel: launch(x,y,z, options, data)
  Kernel-->>Interface: execution completes
  Interface-->>Caller: status
Loading

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Actionable comments posted: 1

Caution

Some comments are outside the diff and can’t be posted inline due to platform limitations.

⚠️ Outside diff range comments (2)
cpp/tensorrt_llm/kernels/trtllmGenKernels/batchedGemm/trtllmGen_bmm_export/BatchedGemmInterface.h (2)

1-18: Add required include guards per project guidelines.

Guidelines require TRTLLM_<FILE_NAME_IN_CAPS> include guards for headers (in addition to or instead of pragma once).

Apply:

-#pragma once
+#ifndef TRTLLM_BATCHEDGEMMINTERFACE_H
+#define TRTLLM_BATCHEDGEMMINTERFACE_H
+// Optional: keep pragma once for toolchain speed; guards remain canonical.
+#pragma once
@@
-} // namespace batchedGemm
- 
-////////////////////////////////////////////////////////////////////////////////////////////////////
- 
-} // namespace batchedGemm
+} // namespace batchedGemm
+
+////////////////////////////////////////////////////////////////////////////////////////////////////
+
+} // namespace batchedGemm
+
+#endif // TRTLLM_BATCHEDGEMMINTERFACE_H

Also applies to: 758-761


540-546: Potential size_t truncation in accumulate.

Initial value 0 makes the accumulation integral promote to int. Use size_t{0} to avoid overflow on large workspaces.

-    auto size = std::accumulate(workspaceSizes.begin(), workspaceSizes.end(), 0);
+    auto size = std::accumulate(workspaceSizes.begin(), workspaceSizes.end(), size_t{0});
🧹 Nitpick comments (3)
cpp/tensorrt_llm/kernels/trtllmGenKernels/batchedGemm/KernelRunner.cpp (2)

310-311: Using current-device SM count during sorting can mismatch the target device.

getValidConfigIndices() queries SM count from the current CUDA device, but run() accepts an explicit device and may be called for a different GPU. On multi-GPU or MIG systems this can reorder tactics suboptimally or inconsistently; also, calling CUDA here can fail if a context wasn’t established yet.

  • Prefer passing the intended device (or multiProcessorCount) into getValidConfigIndices()/getDefaultValidConfigIndex()/isValidConfigIndex, or defer the SM-aware tie-break to a point where the device is known.
  • If keeping it here, add a safe fallback when querying fails, and document the assumption that the current device matches the future run() device.

386-386: Consider stable_sort for deterministic ordering among equals.

Not required, but std::stable_sort can keep relative order of equal elements and mirror multi-pass sorts. Low risk either way.

cpp/tensorrt_llm/kernels/trtllmGenKernels/batchedGemm/trtllmGen_bmm_export/BatchedGemmInterface.h (1)

602-633: Double-check maxNumCtasInBatchDim for dynamic/static combinations.

When options.mIsStaticBatch is false and options.mNumTokens == 0, maxNumCtasInBatchDim remains 0. KernelParams::setKernelParams uses this value when isStaticBatch == false (ctaOffset = maxNumCtas). Please confirm that the dynamic-batch/no-token path is never used (i.e., such cases are always static) or set maxNumCtasInBatchDim to the computed numCtaXy as well.

If needed, minimally adjust:

-    int32_t maxNumCtasInBatchDim{numCtaXy};
+    int32_t maxNumCtasInBatchDim{numCtaXy};
@@
-    if ((options.mEnablesEarlyExit || options.mEnablesDelayedEarlyExit) && options.mNumTokens != 0)
+    if ((options.mEnablesEarlyExit || options.mEnablesDelayedEarlyExit) && options.mNumTokens != 0)
     {
         // ...
         maxNumCtasInBatchDim = batchedGemmData.mProblemDimensions.mMaxNumCtasInTokenDim;
     }
+    else if (!options.mIsStaticBatch)
+    {
+        // Dynamic batching without tokens: still cap by host-known CTA count.
+        maxNumCtasInBatchDim = numCtaXy;
+    }
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🔇 Additional comments (4)
cpp/tensorrt_llm/kernels/trtllmGenKernels/batchedGemm/KernelRunner.cpp (1)

24-26: Include-order guard looks correct.

cudaUtils.h and logger.h are included after BatchedGemmInterface.h as required by the note. LGTM.

cpp/tensorrt_llm/kernels/trtllmGenKernels/batchedGemm/trtllmGen_bmm_export/BatchedGemmInterface.h (3)

435-444: getNumCtas() refactor looks good.

Delegating to getCtaInfo() keeps the contract clear and avoids duplicated grid math. LGTM.


449-451: Helper to materialize options from (config,data) is appropriate.

This removes scattered options wiring and aligns with callers in KernelRunner. LGTM.


666-666: run(): Grid derivation via getCtaInfo() is a clean centralization.

This aligns grid/block/cluster computation and avoids stale mNumCtas. LGTM.

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…tValidConfigIndices

Signed-off-by: Jinyang Yuan <154768711+jinyangyuan-nvidia@users.noreply.github.com>
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@nekorobov nekorobov merged commit b622cde into NVIDIA:main Sep 25, 2025
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@jinyangyuan-nvidia jinyangyuan-nvidia deleted the dev/perf_tactic_sorting branch September 26, 2025 09:41
// Returns true if the configuration of the cubin can be executed for the given params.
bool isValidConfig(BatchedGemmConfig const& config, BatchedGemmData const& data) const;

// Creates GemmOptions from kernel and data.
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Please file a MR of this change to trtllm-gen repo to make it permanent

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