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[None][perf] Fix the tactic sorting in TrtllmGenBatchedGemmRunner::getValidConfigIndices #7419
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[None][perf] Fix the tactic sorting in TrtllmGenBatchedGemmRunner::getValidConfigIndices #7419
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📝 WalkthroughWalkthroughIntroduces CTA/grid computation helpers and moves CTA counts to runtime. Updates BatchedGemmInterface API (add getCtaInfo, getOptionsFromConfigAndData; change getNumCtas signature; remove mNumCtas) and adjusts run() accordingly. Refactors KernelRunner config sorting into a single comparator that uses CTA-aware tie-breakers and SM count via cudaUtils. Changes
Sequence Diagram(s)sequenceDiagram
autonumber
participant Caller
participant KernelRunner
participant Interface as BatchedGemmInterface
participant HW as GPU/SM Info
Caller->>KernelRunner: getValidConfigIndices(gemmData)
KernelRunner->>HW: common::getMultiProcessorCount()
HW-->>KernelRunner: multiProcessorCount
loop Compare candidate configs
KernelRunner->>Interface: getOptionsFromConfigAndData(config, gemmData)
Interface-->>KernelRunner: BatchedGemmOptions
KernelRunner->>Interface: getNumCtas(options, gemmData)
Interface-->>KernelRunner: totalCTAs
KernelRunner->>KernelRunner: cmpFunc tie-breaks (tileK, unroll, tileM/N, scheduler vs. SMs)
end
KernelRunner-->>Caller: sorted valid config indices
sequenceDiagram
autonumber
participant Caller
participant Interface as BatchedGemmInterface
participant Kernel as BatchedGemmKernel
Caller->>Interface: run(config, data)
Interface->>Interface: options = getOptionsFromConfigAndData(config, data)
Interface->>Interface: (x,y,z,maxBatchCtas,batchM) = getCtaInfo(options, data)
Interface->>Interface: totalCTAs = getNumCtas(options, data)
Interface->>Kernel: launch(x,y,z, options, data)
Kernel-->>Interface: execution completes
Interface-->>Caller: status
Estimated code review effort🎯 4 (Complex) | ⏱️ ~60 minutes ✨ Finishing Touches
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Actionable comments posted: 1
Caution
Some comments are outside the diff and can’t be posted inline due to platform limitations.
⚠️ Outside diff range comments (2)
cpp/tensorrt_llm/kernels/trtllmGenKernels/batchedGemm/trtllmGen_bmm_export/BatchedGemmInterface.h (2)
1-18: Add required include guards per project guidelines.Guidelines require TRTLLM_<FILE_NAME_IN_CAPS> include guards for headers (in addition to or instead of pragma once).
Apply:
-#pragma once +#ifndef TRTLLM_BATCHEDGEMMINTERFACE_H +#define TRTLLM_BATCHEDGEMMINTERFACE_H +// Optional: keep pragma once for toolchain speed; guards remain canonical. +#pragma once @@ -} // namespace batchedGemm - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -} // namespace batchedGemm +} // namespace batchedGemm + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +} // namespace batchedGemm + +#endif // TRTLLM_BATCHEDGEMMINTERFACE_HAlso applies to: 758-761
540-546: Potential size_t truncation in accumulate.Initial value 0 makes the accumulation integral promote to int. Use size_t{0} to avoid overflow on large workspaces.
- auto size = std::accumulate(workspaceSizes.begin(), workspaceSizes.end(), 0); + auto size = std::accumulate(workspaceSizes.begin(), workspaceSizes.end(), size_t{0});
🧹 Nitpick comments (3)
cpp/tensorrt_llm/kernels/trtllmGenKernels/batchedGemm/KernelRunner.cpp (2)
310-311: Using current-device SM count during sorting can mismatch the target device.getValidConfigIndices() queries SM count from the current CUDA device, but run() accepts an explicit device and may be called for a different GPU. On multi-GPU or MIG systems this can reorder tactics suboptimally or inconsistently; also, calling CUDA here can fail if a context wasn’t established yet.
- Prefer passing the intended device (or multiProcessorCount) into getValidConfigIndices()/getDefaultValidConfigIndex()/isValidConfigIndex, or defer the SM-aware tie-break to a point where the device is known.
- If keeping it here, add a safe fallback when querying fails, and document the assumption that the current device matches the future run() device.
386-386: Consider stable_sort for deterministic ordering among equals.Not required, but std::stable_sort can keep relative order of equal elements and mirror multi-pass sorts. Low risk either way.
cpp/tensorrt_llm/kernels/trtllmGenKernels/batchedGemm/trtllmGen_bmm_export/BatchedGemmInterface.h (1)
602-633: Double-check maxNumCtasInBatchDim for dynamic/static combinations.When options.mIsStaticBatch is false and options.mNumTokens == 0, maxNumCtasInBatchDim remains 0. KernelParams::setKernelParams uses this value when isStaticBatch == false (ctaOffset = maxNumCtas). Please confirm that the dynamic-batch/no-token path is never used (i.e., such cases are always static) or set maxNumCtasInBatchDim to the computed numCtaXy as well.
If needed, minimally adjust:
- int32_t maxNumCtasInBatchDim{numCtaXy}; + int32_t maxNumCtasInBatchDim{numCtaXy}; @@ - if ((options.mEnablesEarlyExit || options.mEnablesDelayedEarlyExit) && options.mNumTokens != 0) + if ((options.mEnablesEarlyExit || options.mEnablesDelayedEarlyExit) && options.mNumTokens != 0) { // ... maxNumCtasInBatchDim = batchedGemmData.mProblemDimensions.mMaxNumCtasInTokenDim; } + else if (!options.mIsStaticBatch) + { + // Dynamic batching without tokens: still cap by host-known CTA count. + maxNumCtasInBatchDim = numCtaXy; + }
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📒 Files selected for processing (2)
cpp/tensorrt_llm/kernels/trtllmGenKernels/batchedGemm/KernelRunner.cpp(3 hunks)cpp/tensorrt_llm/kernels/trtllmGenKernels/batchedGemm/trtllmGen_bmm_export/BatchedGemmInterface.h(3 hunks)
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📓 Path-based instructions (4)
**/*.{cpp,cc,cxx,cu,h,hpp,hh,hxx,cuh}
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**/*.{cpp,cc,cxx,cu,h,hpp,hh,hxx,cuh}: In C++ and CUDA files, closing braces of namespaces must include a trailing comment naming the namespace (e.g., } // namespace foo)
Prefer const or constexpr variables over #define for constants; variables not modified after initialization must be declared const
Avoid magic literals: except 0, nullptr, true, false, use named constants (e.g., constexpr) instead of inline numeric or string literals
Use Allman brace style; always brace bodies of if/else/switch/while/do/for; put the semicolon of empty loops on a new line
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Locally visible static variables should be lowerCamelCase starting with 's' (e.g., static std::once_flag sFlag)
Member variables use mPrefix (e.g., mCount); public members may omit but using m is encouraged for clarity
Constants (enums, globals, static constants, and function-scope magic-number constants) use uppercase SNAKE_CASE with k prefix (e.g., kMAX_SIZE)
Avoid macros; if necessary, use UPPER_SNAKE_CASE for macro names
Run clang-format (LLVM style) before submitting; maximum line length is 120; use clang-format off/on only for justified exceptions
Use C++ comments (//); C-style /* / only for special inline cases; prefer Doxygen comments: //! and //!<; full-sentence comments are capitalized and punctuated; document public APIs with Doxygen
Disable code with #if/#endif (possibly via a DEBUG macro); do not comment out code; avoid dead code blocks
Do not throw exceptions across library boundaries
Use the least-forceful cast; avoid C-style and functional casts (except void casts); do not remove const/volatile; void to T* via static_cast; reinterpret_cast only a...
Files:
cpp/tensorrt_llm/kernels/trtllmGenKernels/batchedGemm/KernelRunner.cppcpp/tensorrt_llm/kernels/trtllmGenKernels/batchedGemm/trtllmGen_bmm_export/BatchedGemmInterface.h
**/*.{cpp,cc,cxx,cu,h,hpp,hh,hxx,cuh,py}
📄 CodeRabbit inference engine (CODING_GUIDELINES.md)
**/*.{cpp,cc,cxx,cu,h,hpp,hh,hxx,cuh,py}: Use spaces only; no tabs; indent with 4 spaces
Prepend NVIDIA copyright header (current year) to all source files (.cpp, .h, .cu, .py, etc.)
Files:
cpp/tensorrt_llm/kernels/trtllmGenKernels/batchedGemm/KernelRunner.cppcpp/tensorrt_llm/kernels/trtllmGenKernels/batchedGemm/trtllmGen_bmm_export/BatchedGemmInterface.h
**/*.{cpp,cc,cxx,cu}
📄 CodeRabbit inference engine (CODING_GUIDELINES.md)
**/*.{cpp,cc,cxx,cu}: Prefer smart pointers; use std::unique_ptr for sole ownership, std::shared_ptr for shared ownership; avoid deprecated smart pointers
Do not use assignment in subexpressions (e.g., if (x = y)); avoid chained assignments (x = y = z)
Switch statements: provide cases for all enum values and omit default to catch new values; prohibit fall-through except between empty labels; terminate each case with break or throw; do not end a case with return; place break inside braces when using a compound statement
Files:
cpp/tensorrt_llm/kernels/trtllmGenKernels/batchedGemm/KernelRunner.cpp
**/*.{hpp,h,hxx,hh}
📄 CodeRabbit inference engine (CODING_GUIDELINES.md)
Header include guards are required with macro name TRTLLM_<FILE_NAME_IN_CAPS> (no directories, no leading/trailing underscores)
Files:
cpp/tensorrt_llm/kernels/trtllmGenKernels/batchedGemm/trtllmGen_bmm_export/BatchedGemmInterface.h
🧠 Learnings (1)
📚 Learning: 2025-08-29T08:49:23.221Z
Learnt from: CR
PR: NVIDIA/TensorRT-LLM#0
File: CODING_GUIDELINES.md:0-0
Timestamp: 2025-08-29T08:49:23.221Z
Learning: Applies to **/*.cuh : CUDA headers (.cuh) should also follow the project include-guard convention TRTLLM_<FILE_NAME_IN_CAPS>
Applied to files:
cpp/tensorrt_llm/kernels/trtllmGenKernels/batchedGemm/KernelRunner.cpp
🧬 Code graph analysis (2)
cpp/tensorrt_llm/kernels/trtllmGenKernels/batchedGemm/KernelRunner.cpp (1)
cpp/include/tensorrt_llm/common/cudaUtils.h (1)
getMultiProcessorCount(393-400)
cpp/tensorrt_llm/kernels/trtllmGenKernels/batchedGemm/trtllmGen_bmm_export/BatchedGemmInterface.h (2)
cpp/tensorrt_llm/kernels/trtllmGenKernels/batchedGemm/trtllmGen_bmm_export/KernelParams.h (5)
std(120-565)std(189-558)std(199-204)std(240-259)std(251-256)cpp/tensorrt_llm/kernels/trtllmGenKernels/batchedGemm/trtllmGen_bmm_export/GemmOptions.h (1)
divUp(499-502)
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🔇 Additional comments (4)
cpp/tensorrt_llm/kernels/trtllmGenKernels/batchedGemm/KernelRunner.cpp (1)
24-26: Include-order guard looks correct.cudaUtils.h and logger.h are included after BatchedGemmInterface.h as required by the note. LGTM.
cpp/tensorrt_llm/kernels/trtllmGenKernels/batchedGemm/trtllmGen_bmm_export/BatchedGemmInterface.h (3)
435-444: getNumCtas() refactor looks good.Delegating to getCtaInfo() keeps the contract clear and avoids duplicated grid math. LGTM.
449-451: Helper to materialize options from (config,data) is appropriate.This removes scattered options wiring and aligns with callers in KernelRunner. LGTM.
666-666: run(): Grid derivation via getCtaInfo() is a clean centralization.This aligns grid/block/cluster computation and avoids stale mNumCtas. LGTM.
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| // Returns true if the configuration of the cubin can be executed for the given params. | ||
| bool isValidConfig(BatchedGemmConfig const& config, BatchedGemmData const& data) const; | ||
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| // Creates GemmOptions from kernel and data. |
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Please file a MR of this change to trtllm-gen repo to make it permanent
The tactic sorting in
TrtllmGenBatchedGemmRunner::getValidConfigIndicesmay not be as expected because different criteria are applied in different sorting function calls. This PR fixes the issue by applying these criteria in the same sorting function call. Moreover, the number of CTAs is estimated using the modifiedgetNumCtasto align with the kernel launch.Summary by CodeRabbit
New Features
Performance
Refactor
Description
Test Coverage
PR Checklist
Please review the following before submitting your PR:
PR description clearly explains what and why. If using CodeRabbit's summary, please make sure it makes sense.
PR Follows TRT-LLM CODING GUIDELINES to the best of your knowledge.
Test cases are provided for new code paths (see test instructions)
Any new dependencies have been scanned for license and vulnerabilities
CODEOWNERS updated if ownership changes
Documentation updated as needed
The reviewers assigned automatically/manually are appropriate for the PR.
Please check this after reviewing the above items as appropriate for this PR.
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