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[None][feat] DeepEP LL fp8 dispatch/combine by yilin-void · Pull Request #7927 · NVIDIA/TensorRT-LLM · GitHub
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@yilin-void yilin-void commented Sep 23, 2025

DeepEP diff: https://github.com/deepseek-ai/DeepEP/compare/515a311f290eb6d9592fcccfcc80c40f5123ca72...be2582ffe69b5e7d61c3bc9bf7a5316bc48261f9?expand=1

Summary by CodeRabbit

  • New Features

    • Enabled FP8 activations for W4A8 quantization in MoE.
    • Added low-precision combine support via a unified precision-based API.
    • Introduced an adapter to align fused MoE outputs with DeepEP for low-latency paths.
    • Expanded low-latency dispatch/combine to support NVFP4, FP8 QDQ, and W4A8.
  • Improvements

    • Centralized output adaptation and simplified post-alltoall handling across quantization modes.
    • Enabled use of pre-quantization scales with NVFP4 in relevant paths.
  • Chores

    • Updated DeepEP dependency to a newer revision.

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@yilin-void yilin-void requested a review from a team as a code owner September 23, 2025 09:38
@yilin-void yilin-void requested a review from QiJune September 23, 2025 09:38
@yilin-void yilin-void changed the title DeepEP LL fp8 dispatch/combine [None][feat]DeepEP LL fp8 dispatch/combine Sep 23, 2025
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📝 Walkthrough

Walkthrough

Updates DeepEP commit pin in CMake. Enables NVFP4 AWQ with prequant scales and adds a CutlassMoeFCRunner instantiation. Adds guarded FP8 activation handling for INT4 W4 in moeOp. Renames and generalizes a low-latency combine API to support multiple precisions. Refactors fused MoE Wide EP to centralize DeepEP dispatch/adaptation and support FP8 QDQ, NVFP4, and W4A8 paths.

Changes

Cohort / File(s) Summary
DeepEP commit pin
cpp/tensorrt_llm/deep_ep/CMakeLists.txt
Updated DEEP_EP_COMMIT hash from 515a311f... to 6e134bbd....
Cutlass MoE kernels
cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_kernels.cu
Removed guard blocking prequant scales with NVFP4 in FP8-FP8 AWQ path; added explicit template instantiation: CutlassMoeFCRunner<__nv_fp8_e4m3, cutlass::uint4b_t, __nv_bfloat16, __nv_fp8_e4m3>.
THOP MoE operator FP8
cpp/tensorrt_llm/thop/moeOp.cpp
Added FP8 activation handling under ENABLE_FP8 for INT4 W4 group scaling; otherwise raises unsupported error; retained Half/BFloat16 cases.
DeepEP utils API
tensorrt_llm/_torch/modules/fused_moe/deep_ep_utils.py
Renamed/widened method: low_latency_combine_fp4(...)low_latency_combine_low_precision(precision, hidden_states, global_scales?, topk_idx, topk_weights, handle); updated call sites to pass precision.
Fused MoE Wide EP refactor
tensorrt_llm/_torch/modules/fused_moe/fused_moe_wide_ep.py
Added deep_ep_low_latency_dispatch_modify_output_to_adapt_fused_moe(...); centralized DeepEP dispatch/output adaptation; updated flows for FP8 QDQ, NVFP4, and W4A8; integrated low-precision combine via low_latency_combine_low_precision; simplified nvfp4 gating via quant_mode checks.

Sequence Diagram(s)

sequenceDiagram
  autonumber
  participant W as WideEPMoE
  participant D as DeepEP Buffer
  participant A2A as AllToAll
  participant AD as Adapter (new)

  Note over W: Dispatch with multi-precision support

  W->>A2A: alltoall(x, x_sf, expert counts)
  A2A-->>W: recv_x, recv_x_sf, recv_expert_count

  alt Quant mode == FP8 QDQ
    W->>D: dispatch(recv_x.cast(fp8), recv_x_sf)
    D-->>W: token_selected, token_scales?
    W->>AD: adapt outputs (fp8)
  else Quant mode == NVFP4
    W->>D: dispatch_nvfp4(recv_x_fp4, recv_x_sf)
    D-->>W: token_selected, token_scales
    W->>AD: adapt outputs (nvfp4)
  else Quant mode == W4A8
    W->>W: apply prequant scales (W4A8)
    W->>D: dispatch(recv_x_a8, recv_x_sf)
    D-->>W: token_selected, token_scales?
    W->>AD: adapt outputs (w4a8)
  end

  AD-->>W: token_selected_slots, final_scales?, topk_idx, topk_weights
Loading
sequenceDiagram
  autonumber
  participant W as WideEPMoE
  participant BU as VariableLengthLowLatencyBuffer
  Note over W: Low-precision combine (generalized)

  W->>BU: low_latency_combine_low_precision(precision, hidden_states, global_scales?, topk_idx, topk_weights, handle)
  BU-->>W: combined_hidden_states
Loading

Estimated code review effort

🎯 4 (Complex) | ⏱️ ~60 minutes

Pre-merge checks and finishing touches

❌ Failed checks (2 warnings)
Check name Status Explanation Resolution
Docstring Coverage ⚠️ Warning Docstring coverage is 11.11% which is insufficient. The required threshold is 80.00%. You can run @coderabbitai generate docstrings to improve docstring coverage.
Description Check ⚠️ Warning The PR description contains only a DeepEP diff link and the unfilled repository PR template, and it omits an implementation summary, a list of key modified files, explicit test coverage, and migration notes for public API changes (for example the low_latency_combine_fp4 → low_latency_combine_low_precision rename), so reviewers lack the context needed to evaluate impact and testing. Please update the PR description with a short summary of functional changes and rationale, enumerate the key modified files and any breaking or public API changes (notably the method rename and new/dependent DeepEP commit), list the tests that exercise new FP8/NVFP4/W4A8 code paths and how to run them, and note any documentation, CODEOWNERS, or CI considerations required for this change.
✅ Passed checks (1 passed)
Check name Status Explanation
Title Check ✅ Passed The title "[None][feat] DeepEP LL fp8 dispatch/combine" is concise, follows the repository title template, and accurately summarizes the primary intent of the changeset—adding FP8 dispatch and combine support for DeepEP low-latency paths across C++ kernels and Python integration layers.
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Actionable comments posted: 0

Caution

Some comments are outside the diff and can’t be posted inline due to platform limitations.

⚠️ Outside diff range comments (2)
cpp/tensorrt_llm/deep_ep/CMakeLists.txt (1)

112-115: Bug: STREQUAL compares against the literal string; stamp check is always true

This compares OLD_NVSHMEM_STAMP_CONTENT to the literal “NVSHMEM_STAMP_CONTENT”. It should compare variable-to-variable (and quote values). Otherwise it will keep wiping the nvshmem project even when not needed.

Apply this diff:

-if(NOT OLD_NVSHMEM_STAMP_CONTENT STREQUAL NVSHMEM_STAMP_CONTENT)
+if(NOT "${OLD_NVSHMEM_STAMP_CONTENT}" STREQUAL "${NVSHMEM_STAMP_CONTENT}")
   file(REMOVE_RECURSE ${CMAKE_CURRENT_BINARY_DIR}/nvshmem_project-prefix)
   file(WRITE ${NVSHMEM_STAMP_FILE} "${NVSHMEM_STAMP_CONTENT}")
 endif()
tensorrt_llm/_torch/modules/fused_moe/fused_moe_wide_ep.py (1)

1-1: Add required NVIDIA Apache-2.0 header (2025).

Per coding guidelines, prepend the NVIDIA Apache-2.0 copyright header with current year.

+# Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
 import os
🧹 Nitpick comments (7)
cpp/tensorrt_llm/deep_ep/CMakeLists.txt (1)

128-132: Avoid globally overriding compilers for the whole configure when only NVSHMEM needs GCC

Overriding CMAKE_{C,CXX}_COMPILER and CMAKE_CUDA_HOST_COMPILER globally can perturb the rest of the project when users pick Clang. Prefer setting compilers via ExternalProject’s CMAKE_CACHE_ARGS only, or isolate into a dedicated toolchain for the ExternalProject.

cpp/tensorrt_llm/thop/moeOp.cpp (1)

203-217: Guarded FP8-activation path for W4A8 is consistent with kernel instantiation

  • The specialization CutlassMoeFCRunner<__nv_fp8_e4m3, cutlass::uint4b_t, __nv_bfloat16, __nv_fp8_e4m3> aligns with the explicit instantiation added in moe_kernels.cu.
  • Erroring on non-W4A8 for FP8 activations is a good guard.

Minor:

  • Consider a short comment noting SM/ENABLE_FP8 constraints to aid future refactors.
tensorrt_llm/_torch/modules/fused_moe/deep_ep_utils.py (1)

182-197: Avoid magic numbers for precision; prefer Literal or constants

The precision parameter uses 0/1. This is brittle. Suggest tightening the type and using named constants for clarity.

Apply this diff locally to the signature:

-from typing import List, Optional, Tuple, Union
+from typing import List, Optional, Tuple, Union, Literal

and

-    def low_latency_combine_low_precision(self, precision: int,
+    def low_latency_combine_low_precision(self, precision: Literal[0, 1],
                                           hidden_states: torch.Tensor,
                                           global_scales: Optional[torch.Tensor],
                                           topk_idx: torch.Tensor,
                                           topk_weights: torch.Tensor,
                                           handle: Tuple):

Optional: define constants at module top for readability:

# Place near the top of the module
FP8_PRECISION = 0
NVFP4_PRECISION = 1
tensorrt_llm/_torch/modules/fused_moe/fused_moe_wide_ep.py (4)

188-193: Remove stray no-op expression; keep env flags.

Line 188 evaluates self.quant_config.quant_mode without using it (Ruff B018).

         if self.enable_alltoall:
-            self.quant_config.quant_mode
             self.use_postquant_alltoall = (os.environ.get(
                 "TRTLLM_MOE_POST_QUANT_ALLTOALLV", "1") == "1")
             self.use_low_precision_combine = (os.environ.get(
                 "TRTLLM_MOE_USE_LOW_PRECISION_COMBINE", "0") == "1")

647-649: Shorten/standardize exception message (Ruff TRY003).

Keep error messages concise; avoid long f-strings referencing large objects.

-                    raise ValueError(
-                        f"unsupported quantization mode in postquant alltoall: {self.quant_config.quant_mode}"
-                    )
+                    raise ValueError("Unsupported quantization mode in postquant alltoall")

708-717: Avoid magic numbers for precision; use an IntEnum.

Improves readability and reduces mistakes when adding new precisions.

-                    assert self.has_nvfp4 or self.has_w4afp8 or self.has_fp8_qdq, "Low precision combine only supports nvfp4, w4afp8 and fp8 qdq"
-                    precision = 0
+                    assert self.has_nvfp4 or self.has_w4afp8 or self.has_fp8_qdq, "Low precision combine only supports nvfp4, w4afp8 and fp8 qdq"
+                    precision = CombinePrecision.FP8
                     global_scales = None
                     if self.has_nvfp4:
-                        precision = 1
+                        precision = CombinePrecision.NVFP4
                         global_scales = torch.ops.trtllm.calculate_nvfp4_global_scale(
                             final_hidden_states, recv_expert_count)
                     final_hidden_states = self.deep_ep_buffer.low_latency_combine_low_precision(
                         precision, final_hidden_states, global_scales,
                         deep_ep_topk_idx, deep_ep_topk_weights, deep_ep_handle)

Add near the AlltoallMethodType (outside this hunk):

class CombinePrecision(IntEnum):
    FP8 = 0
    NVFP4 = 1

311-339: Fix dtype and docstring; moe_ep_rank is a @Property

  • moe_ep_rank is defined with @Property in tensorrt_llm/mapping.py — no () needed.
  • Ensure torch.where doesn't upcast: make the "else" branch an int32 tensor (e.g., torch.full(..., dtype=torch.int32, device=...)); use -1 in reshapes and token_selected_slots.reshape(-1, 1).
  • Add the short docstring for the DeepEP adapter describing input/output shapes and dtypes.
  • Optional: prefer precomputed Mapping.slot_start/slot_end if the Mapping exposes them to avoid arithmetic on moe_ep_rank.
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📒 Files selected for processing (5)
  • cpp/tensorrt_llm/deep_ep/CMakeLists.txt (1 hunks)
  • cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_kernels.cu (1 hunks)
  • cpp/tensorrt_llm/thop/moeOp.cpp (1 hunks)
  • tensorrt_llm/_torch/modules/fused_moe/deep_ep_utils.py (2 hunks)
  • tensorrt_llm/_torch/modules/fused_moe/fused_moe_wide_ep.py (6 hunks)
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  • cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_kernels.cu
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  • cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_kernels.cu
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  • tensorrt_llm/_torch/modules/fused_moe/deep_ep_utils.py
  • tensorrt_llm/_torch/modules/fused_moe/fused_moe_wide_ep.py
  • cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_kernels.cu
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  • tensorrt_llm/_torch/modules/fused_moe/deep_ep_utils.py
  • tensorrt_llm/_torch/modules/fused_moe/fused_moe_wide_ep.py
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🧠 Learnings (4)
📚 Learning: 2025-08-08T22:03:40.707Z
Learnt from: sklevtsov-nvidia
PR: NVIDIA/TensorRT-LLM#3294
File: cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_kernels.cu:1198-1209
Timestamp: 2025-08-08T22:03:40.707Z
Learning: In the CUTLASS MoE kernels (cpp/tensorrt_llm/cutlass_extensions), when `layout_info.fusion` is set to `TmaWarpSpecializedGroupedGemmInput::EpilogueFusion::FINALIZE`, the `router_scales` parameter must be non-null by design. The fused finalize kernel epilogue does not perform nullptr checks and requires valid router scales to function correctly. This is an implicit contract that callers must satisfy when enabling the FINALIZE fusion mode.

Applied to files:

  • cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_kernels.cu
📚 Learning: 2025-08-09T20:57:04.084Z
Learnt from: sklevtsov-nvidia
PR: NVIDIA/TensorRT-LLM#3294
File: cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_gemm_tma_warp_specialized_input.cu:118-127
Timestamp: 2025-08-09T20:57:04.084Z
Learning: In the CUTLASS MoE finalize fusion implementation (cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_gemm_tma_warp_specialized_input.cu), when setting `fused_finalize_epilogue.stride_final_output` with shape `(hidden_size, num_output_tokens, 1)`, the `num_rows_in_final_output` should be set to `num_output_tokens` (not `hidden_size`) because of a swap+transpose operation that maps rows of the output tensor to `hidden_size` and columns to `num_output_tokens`.

Applied to files:

  • cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_kernels.cu
📚 Learning: 2025-09-19T21:28:13.751Z
Learnt from: jhaotingc
PR: NVIDIA/TensorRT-LLM#7856
File: cpp/tensorrt_llm/thop/fp8BlockScaleMoe.cpp:159-166
Timestamp: 2025-09-19T21:28:13.751Z
Learning: In TensorRT-LLM blockScaleMoe routing (cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/runner.cu), the DeepSeek routing method performs reinterpret_cast<float*>(routingLogits) at line 89, which could cause issues if routing_logits are BF16. However, Qwen3-FP8 models use RenormalizeNaive routing method and are not affected by this dtype casting issue.

Applied to files:

  • cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_kernels.cu
📚 Learning: 2025-08-19T03:35:20.866Z
Learnt from: djns99
PR: NVIDIA/TensorRT-LLM#6915
File: cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_kernels.cu:4616-4626
Timestamp: 2025-08-19T03:35:20.866Z
Learning: In the MOE profiler TMA workspace preparation (cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_kernels.cu), the overlapping of TMA WS regions for NONE and FINALIZE variants is deliberate design to save memory space, as confirmed by djns99. The comment "reuse the same pointers to save space" reflects this intentional behavior.

Applied to files:

  • cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_kernels.cu
🧬 Code graph analysis (3)
cpp/tensorrt_llm/thop/moeOp.cpp (1)
cpp/tests/unit_tests/kernels/mixtureOfExpertsTest.cu (1)
  • ENABLE_FP8 (216-225)
tensorrt_llm/_torch/modules/fused_moe/deep_ep_utils.py (1)
tensorrt_llm/_common.py (1)
  • precision (111-116)
tensorrt_llm/_torch/modules/fused_moe/fused_moe_wide_ep.py (6)
tensorrt_llm/_torch/modules/fused_moe/quantization.py (2)
  • FP8QDQFusedMoEMethod (493-601)
  • FusedMoEQuantScalesW4A8 (57-65)
tensorrt_llm/_torch/modules/fused_moe/interface.py (4)
  • MoEWeightLoadingMode (16-22)
  • has_any_quant (277-280)
  • has_fp8_qdq (284-287)
  • has_nvfp4 (296-299)
tensorrt_llm/mapping.py (1)
  • moe_ep_rank (360-361)
tensorrt_llm/_torch/custom_ops/torch_custom_ops.py (9)
  • _ (249-302)
  • _ (378-386)
  • _ (464-474)
  • _ (643-670)
  • _ (703-713)
  • _ (787-797)
  • _ (887-903)
  • _ (983-991)
  • _ (1024-1035)
tensorrt_llm/_torch/modules/fused_moe/deep_ep_utils.py (3)
  • low_latency_dispatch (139-155)
  • low_latency_dispatch_fp4 (169-180)
  • low_latency_combine_low_precision (182-197)
tensorrt_llm/_torch/modules/fused_moe/fused_moe_cutlass.py (1)
  • has_w4afp8 (181-184)
🪛 Ruff (0.13.1)
tensorrt_llm/_torch/modules/fused_moe/fused_moe_wide_ep.py

188-188: Found useless expression. Either assign it to a variable or remove it.

(B018)


647-649: Avoid specifying long messages outside the exception class

(TRY003)

🔇 Additional comments (8)
cpp/tensorrt_llm/deep_ep/CMakeLists.txt (2)

1-1: Verified DeepEP pin — commit exists and nvshmem.patch present

Commit 6e134bbd0a1e2d3c9ab58908de4eb40aa446ba17 is reachable on GitHub and the tarball contains third-party/nvshmem.patch — NVSHMEM patch flow OK.


25-30: Confirmed — "100f" is valid for CMake 3.31+
CMake 3.31+ accepts "100f" (it forwards the token to the CUDA toolchain). "f" = family‑specific (matches the major SM and allows equal/higher minor); "a" = architecture‑specific (exact SM only).

cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_kernels.cu (1)

4737-4738: Explicit instantiation for FP8-act × W4 weights (BF16 out) looks correct

Matches the new runner used in moeOp and is properly gated by ENABLE_FP8 and ENABLE_BF16. No issues from a linkage/ODR perspective.

tensorrt_llm/_torch/modules/fused_moe/deep_ep_utils.py (2)

5-5: Import addition is correct

Optional is needed; no concerns.


192-194: Confirm deep_ep.Buffer API parity and callsite updates

VariableLengthLowLatencyBuffer.low_latency_combine_low_precision delegates to self.buffer.low_latency_combine_low_precision; callsites found at tensorrt_llm/_torch/modules/fused_moe/fused_moe_wide_ep.py (~L715, L719). No occurrences of low_latency_combine_fp4 remain in the repo. The deep_ep extension/bindings are not in this repo — confirm the native deep_ep.Buffer implements low_latency_combine_low_precision (or provide updated bindings).

tensorrt_llm/_torch/modules/fused_moe/fused_moe_wide_ep.py (3)

20-22: Imports look correct.

New imports (FP8 QDQ, W4A8 scales) match usages below.


521-524: Adapter invocation LGTM.

Correctly adapts DeepEP low-latency outputs to fused_moe inputs for the non-postquant path.


610-651: Confirm Tensor.view(dtype) usage is supported in your PyTorch/build

Repo-wide search shows many .view(torch.) calls (e.g. tensorrt_llm/_torch/modules/fused_moe/fused_moe_wide_ep.py around lines 616–619 and 643–645). If your PyTorch build does not accept a dtype argument for .view, replace with .to(dtype) or an explicit zero-copy reinterpretation helper to avoid runtime errors.

Signed-off-by: Yilin Zhang <18275976+yilin-void@users.noreply.github.com>
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PR_Github #19689 [ run ] triggered by Bot

@yilin-void yilin-void changed the title [None][feat]DeepEP LL fp8 dispatch/combine [None][feat] DeepEP LL fp8 dispatch/combine Sep 24, 2025
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PR_Github #19689 [ run ] completed with state SUCCESS
/LLM/main/L0_MergeRequest_PR pipeline #14817 completed with status: 'FAILURE'

Signed-off-by: Yilin Zhang <18275976+yilin-void@users.noreply.github.com>
Signed-off-by: Yilin Zhang <18275976+yilin-void@users.noreply.github.com>
Signed-off-by: Yilin Zhang <18275976+yilin-void@users.noreply.github.com>
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/bot run

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PR_Github #19767 [ run ] triggered by Bot

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PR_Github #19767 [ run ] completed with state SUCCESS
/LLM/main/L0_MergeRequest_PR pipeline #14871 completed with status: 'SUCCESS'
Pipeline passed with automatic retried tests. Check the rerun report for details.

@yilin-void yilin-void merged commit 336c2ef into NVIDIA:main Sep 25, 2025
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@yilin-void yilin-void deleted the deep_ep/hopper_fp8 branch September 28, 2025 03:27
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