[None] [blog] Scaling Expert Parallelism in TensorRT LLM (Part 3: Pushing the Performance Boundary) #8323
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Signed-off-by: Kaiyu Xie <26294424+kaiyux@users.noreply.github.com> Update Signed-off-by: Kaiyu Xie <26294424+kaiyux@users.noreply.github.com> add alltoall optimization part Signed-off-by: Dongxu Yang <78518666+dongxuy04@users.noreply.github.com> Update Signed-off-by: Kaiyu Xie <26294424+kaiyux@users.noreply.github.com> Minor updates Signed-off-by: Kaiyu Xie <26294424+kaiyux@users.noreply.github.com> doc: add FP8 context FMHA support part. Signed-off-by: Yuxian Qiu <142763828+yuxianq@users.noreply.github.com> Add lowprecision all2all and fuse shared expert into local reduction Signed-off-by: Zongfei Jing <20381269+zongfeijing@users.noreply.github.com> Add MTP LM head tensor parallelism Signed-off-by: Kaiyu Xie <26294424+kaiyux@users.noreply.github.com> Polish Signed-off-by: Kaiyu Xie <26294424+kaiyux@users.noreply.github.com> Update Signed-off-by: Kaiyu Xie <26294424+kaiyux@users.noreply.github.com> Update Signed-off-by: Kaiyu Xie <26294424+kaiyux@users.noreply.github.com> Add images Signed-off-by: Kaiyu Xie <26294424+kaiyux@users.noreply.github.com> Update Signed-off-by: Kaiyu Xie <26294424+kaiyux@users.noreply.github.com> Update Signed-off-by: Kaiyu Xie <26294424+kaiyux@users.noreply.github.com> Update Signed-off-by: Kaiyu Xie <26294424+kaiyux@users.noreply.github.com> AI polishment Signed-off-by: Kaiyu Xie <26294424+kaiyux@users.noreply.github.com> Update Signed-off-by: Kaiyu Xie <26294424+kaiyux@users.noreply.github.com> Update Signed-off-by: Kaiyu Xie <26294424+kaiyux@users.noreply.github.com> Update Signed-off-by: Kaiyu Xie <26294424+kaiyux@users.noreply.github.com> Update Signed-off-by: Kaiyu Xie <26294424+kaiyux@users.noreply.github.com> Update Signed-off-by: Kaiyu Xie <26294424+kaiyux@users.noreply.github.com> Update Signed-off-by: Kaiyu Xie <26294424+kaiyux@users.noreply.github.com> Update Signed-off-by: Kaiyu Xie <26294424+kaiyux@users.noreply.github.com>
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📝 WalkthroughWalkthroughAdds a new technical blog markdown file detailing Part 3 of Scaling Expert Parallelism in TensorRT-LLM, covering precision strategies, network structure adjustments, and kernel fusion/overlap techniques, with references, diagrams, and performance notes. Changes
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docs/source/blogs/tech_blog/blog14_Scaling_Expert_Parallelism_in_TensorRT-LLM_part3.md (9)
176-184: Correct figure reference and unify AlltoAll casing.Reference points to Figure 4 but the caption is Figure 6; also standardize “AlltoAll”.
-Taking the dispatch of four fields as an example, the data flow is shown in Figure 4. +Taking the dispatch of four fields as an example, the data flow is shown in Figure 6. @@ -<p align="center"><sub><em>Figure 6: The data flow of new Alltoall kernel</em></sub></p> +<p align="center"><sub><em>Figure 6: The data flow of the new `AlltoAll` kernel</em></sub></p>
36-36: Add alt text to images (MD045).All images should include meaningful alt text for accessibility and lint compliance.
- <img src="../media/tech_blog14_overview_before_opt.png" width="600"> + <img src="../media/tech_blog14_overview_before_opt.png" alt="Figure 1: Network structure before optimization" width="600"> @@ - <img src="../media/tech_blog14_MTP_parallel_1.png" width="500"> + <img src="../media/tech_blog14_MTP_parallel_1.png" alt="Figure 2: MTP LM head before optimization" width="500"> @@ - <img src="../media/tech_blog14_MTP_parallel_2.png" width="500"> + <img src="../media/tech_blog14_MTP_parallel_2.png" alt="Figure 3: MTP LM head after applying tensor parallelism" width="500"> @@ - <img src="../media/tech_blog14_pdloff.png" width="1000"> + <img src="../media/tech_blog14_pdloff.png" alt="Figure 4: Profiling results with PDL disabled" width="1000"> @@ - <img src="../media/tech_blog14_pdlon.png" width="1000"> + <img src="../media/tech_blog14_pdlon.png" alt="Figure 5: Profiling results with PDL enabled" width="1000"> @@ - <img src="../media/tech_blog14_alltoall_dataflow.png" width="800"> + <img src="../media/tech_blog14_alltoall_dataflow.png" alt="Figure 6: Data flow of the new AlltoAll kernel" width="800"> @@ - <img src="../media/tech_blog14_overview_after_opt.png" width="600"> + <img src="../media/tech_blog14_overview_after_opt.png" alt="Figure 7: Network structure after optimization" width="600"> @@ - <img src="../media/tech_blog14_perf.png" width="600"> + <img src="../media/tech_blog14_perf.png" alt="Figure 8: End-to-end performance comparison" width="600">Also applies to: 88-88, 97-97, 154-154, 163-163, 180-180, 219-219, 227-227
50-51: Avoid bare URLs (MD034).Use descriptive Markdown links.
-* https://huggingface.co/nvidia/DeepSeek-R1-FP4-v2 -* https://huggingface.co/nvidia/DeepSeek-R1-0528-FP4-v2 +* [DeepSeek‑R1‑FP4‑v2 checkpoint](https://huggingface.co/nvidia/DeepSeek-R1-FP4-v2) +* [DeepSeek‑R1‑0528‑FP4‑v2 checkpoint](https://huggingface.co/nvidia/DeepSeek-R1-0528-FP4-v2)
204-212: Specify code fence language and clean up units/wording.Add fence language (MD040), use µs, and tighten phrasing.
-On ISL/OSL 8k/1k, batch size 1 cases, on context phase, we observed that the `copy` operation takes 306us, which is clearly suboptimal. If we try to calculate a theoretical duration, considering 8 TB/sec HBM3e bandwidth, the formula would roughly be: -``` -( ISL 8192 * k_nope_size 128 * num_heads 128 * 2 bytes * read/write 2 ) / ( 8 TB/sec * efficiency 0.8 ) = 80 us -``` +In ISL/OSL 8k/1k, batch‑size‑1 context‑phase cases, we observed that the `copy` operation takes 306 µs, which is clearly suboptimal. A rough theoretical duration, assuming 8 TB/s HBM3e bandwidth, is: +```text +( ISL 8192 * k_nope_size 128 * num_heads 128 * 2 bytes * read/write 2 ) / ( 8 TB/s * efficiency 0.8 ) ≈ 80 µs +``` @@ -To optimize the operator, we simply added `torch.compile` decorator to the operation, and the kernel duration directly drops to 107us, which is greatly reduced and already on a promising level. [PR 8044](https://github.com/NVIDIA/TensorRT-LLM/pull/8044) implemented the changes. This is an outstanding example demonstrating the power of `torch.compile`, and showing the process of analyzing and optimizing without heavily hand-crafting kernels. +To optimize the operator, we added the `torch.compile` decorator to the operation; the kernel duration dropped to 107 µs. [PR 8044](https://github.com/NVIDIA/TensorRT-LLM/pull/8044) implemented the changes. This demonstrates the power of `torch.compile` and a data‑driven path to optimization without heavy hand‑crafted kernels.
32-33: Polish opening sentence.Simplify and fix phrasing.
-Let's firstly take a look at how the network structure looks like before we did the optimizations, to give an overall review on how the workloads look like: +First, let's look at the network structure before the optimizations to provide an overview of the workloads:
47-49: Clarify “wo GEMM” terminology.Use a standard symbol and crisper wording.
-The wo GEMM is the final linear layer within the multi-head attention block that produces the final outputs. While DeepSeek R1's MLA modifies the initial projections for keys and values, the wo GEMM operator remains a critical and standard component for finalizing the attention computation. In the term, "wo" is the abbreviation for the weight matrix for the output. +The output‑projection GEMM (often denoted Wₒ) is the final linear layer within the multi‑head attention block. While DeepSeek R1's MLA modifies the initial projections for keys and values, the Wₒ GEMM remains a standard component for finalizing the attention computation. Here, “Wₒ” denotes the output‑projection weight matrix.
93-95: Minor phrasing for readability.Prefer “first” and simplify.
-Collecting the local argmax logits firstly helps with minimizing communication and argmax computation overheads. Finally, we split logits to guarantee correctness. +Collecting the local argmax logits first minimizes communication and argmax overhead. Finally, we split logits to guarantee correctness.
126-136: PDL wording: fix prepositions and clarify.Minor grammar nits.
-We inserted the `cudaTriggerProgrammaticLaunchCompletion` API with all thread blocks in the primary kernel, which signals that it's ready for the secondary kernel to launch, and then call the `cudaGridDependencySynchronize` API in the secondary kernel, which blocks until all primary kernels the secondary kernel depends on have completed and flushed results to global memory. +We insert `cudaTriggerProgrammaticLaunchCompletion` in all thread blocks of the primary kernel to signal readiness for launching the secondary kernel, and call `cudaGridDependencySynchronize` in the secondary kernel, which blocks until all dependent primary kernels have completed and flushed results to global memory.
9-9: Optional: avoid emphasis-as-heading (MD036).Consider plain text without italics or a small “Authors” line; current style is acceptable if you ignore this lint rule.
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61-63: NVFP4 scale-factor description is accurate: NVFP4 encodes 4-bit floats in E2M1 layout, applies one E4M3 FP8 scale per 16-element micro-block, and uses a global FP32 scale for overflow safety.
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📝 WalkthroughWalkthroughAdds a new documentation file introducing a blog post on performance optimizations for expert parallelism in TensorRT-LLM, covering low-precision techniques, network structure adjustments, kernel overlap/fusion strategies, and end-to-end performance notes. No code or public APIs are changed. Changes
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docs/source/blogs/tech_blog/blog14_Scaling_Expert_Parallelism_in_TensorRT-LLM_part3.md (5)
36-36: Add alt text to images for accessibility (MD045).All images use HTML
without alt text. Add concise alt attributes.
- <img src="https://github.com/NVIDIA/TensorRT-LLM/raw/main/docs/source/blogs/media/tech_blog14_overview_before_opt.png" width="600"> + <img alt="Network structure overview before optimization" src="https://github.com/NVIDIA/TensorRT-LLM/raw/main/docs/source/blogs/media/tech_blog14_overview_before_opt.png" width="600">- <img src="https://github.com/NVIDIA/TensorRT-LLM/raw/main/docs/source/blogs/media/tech_blog14_MTP_parallel_1.png" width="500"> + <img alt="MTP LM head computation before optimization" src="https://github.com/NVIDIA/TensorRT-LLM/raw/main/docs/source/blogs/media/tech_blog14_MTP_parallel_1.png" width="500">- <img src="https://github.com/NVIDIA/TensorRT-LLM/raw/main/docs/source/blogs/media/tech_blog14_MTP_parallel_2.png" width="500"> + <img alt="MTP LM head computation after applying tensor parallelism" src="https://github.com/NVIDIA/TensorRT-LLM/raw/main/docs/source/blogs/media/tech_blog14_MTP_parallel_2.png" width="500">- <img src="https://github.com/NVIDIA/TensorRT-LLM/raw/main/docs/source/blogs/media/tech_blog14_pdloff.png" width="1000"> + <img alt="Profiling timeline with PDL disabled" src="https://github.com/NVIDIA/TensorRT-LLM/raw/main/docs/source/blogs/media/tech_blog14_pdloff.png" width="1000">- <img src="https://github.com/NVIDIA/TensorRT-LLM/raw/main/docs/source/blogs/media/tech_blog14_pdlon.png" width="1000"> + <img alt="Profiling timeline with PDL enabled" src="https://github.com/NVIDIA/TensorRT-LLM/raw/main/docs/source/blogs/media/tech_blog14_pdlon.png" width="1000">- <img src="https://github.com/NVIDIA/TensorRT-LLM/raw/main/docs/source/blogs/media/tech_blog14_alltoall_dataflow.png" width="800"> + <img alt="Data flow of the new AlltoAll kernel" src="https://github.com/NVIDIA/TensorRT-LLM/raw/main/docs/source/blogs/media/tech_blog14_alltoall_dataflow.png" width="800">- <img src="https://github.com/NVIDIA/TensorRT-LLM/raw/main/docs/source/blogs/media/tech_blog14_overview_after_opt.png" width="600"> + <img alt="Network structure overview after optimization" src="https://github.com/NVIDIA/TensorRT-LLM/raw/main/docs/source/blogs/media/tech_blog14_overview_after_opt.png" width="600">- <img src="https://github.com/NVIDIA/TensorRT-LLM/raw/main/docs/source/blogs/media/tech_blog14_perf.png" width="600"> + <img alt="End-to-end performance comparison (Aug 31)" src="https://github.com/NVIDIA/TensorRT-LLM/raw/main/docs/source/blogs/media/tech_blog14_perf.png" width="600">Based on static analysis hints
Also applies to: 88-88, 97-97, 154-154, 163-163, 180-180, 219-219, 227-227
50-51: Replace bare URLs with labeled links (MD034).Improves readability and lint compliance.
-* https://huggingface.co/nvidia/DeepSeek-R1-FP4-v2 -* https://huggingface.co/nvidia/DeepSeek-R1-0528-FP4-v2 +* [nvidia/DeepSeek-R1-FP4-v2](https://huggingface.co/nvidia/DeepSeek-R1-FP4-v2) +* [nvidia/DeepSeek-R1-0528-FP4-v2](https://huggingface.co/nvidia/DeepSeek-R1-0528-FP4-v2)Based on static analysis hints
207-209: Specify a language for the fenced code block (MD040).This is a formula; use a neutral language label.
-``` +```text ( ISL 8192 * k_nope_size 128 * num_heads 128 * 2 bytes * read/write 2 ) / ( 8 TB/sec * efficiency 0.8 ) = 80 usBased on static analysis hints --- `9-9`: **Optional: avoid emphasis-as-heading (MD036).** Use a small heading instead of italicized line. ```diff -*By NVIDIA TensorRT LLM Team* +#### By the NVIDIA TensorRT-LLM TeamBased on static analysis hints
32-32: Minor grammar/wording polish for clarity.Tighten phrasing and fix small grammar nits.
-Let's firstly take a look at how the network structure looks like before we did the optimizations, to give an overall review on how the workloads look like: +Let's first look at the network structure before the optimizations, to give an overall view of the workloads:-Collecting the local argmax logits firstly helps with minimizing communication and argmax computation overheads. +Collecting the local argmax logits first helps minimize communication and argmax computation overhead.-As mentioned in previous section, Q and K are divided into two parts in DeepSeek MLA: with RoPE and without RoPE. +As mentioned in the previous section, Q and K are divided into two parts in DeepSeek MLA: with RoPE and without RoPE.-On ISL/OSL 8k/1k, batch size 1 cases, on context phase, we observed that the `copy` operation takes 306us, which is clearly suboptimal. +In ISL/OSL 8k/1k, batch‑size‑1 context cases, we observed that the `copy` operation takes ~306 us, which is suboptimal.Also applies to: 93-93, 204-204, 206-206
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Scaling Expert Parallelism in TensorRT LLM (Part 3: Pushing the Performance Boundary)
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