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Description
🐛 Describe the bug
For mean_out op, the print value of y1 suppose to be "tensor([[[2., 2., 2., 2.]]], dtype=torch.float16)" but it will be randn value which is same as y1 create. This means it not put the result to the out parameter of mean_out op.
import torch
x1 = torch.tensor([[[1.0, 1.0, 1.0, 1.0]], [[2.0, 2.0, 2.0, 2.0]], [[3.0, 3.0, 3.0, 3.0]]], dtype=torch.float16)
y1 = torch.empty((1, 1, 4), dtype=torch.float16)
torch.mean(x1, dim=0, keepdim=True, out=y1)
print(y1)
This may because of the code in file ".\aten\src\ATen\native\ReduceOps.cpp" function "TORCH_IMPL_FUNC(mean_out)"
TORCH_IMPL_FUNC(mean_out)
(const Tensor& self,
OptionalIntArrayRef opt_dim,
bool keepdim,
std::optional<ScalarType> opt_dtype,
const Tensor& result) {
ScalarType dtype = result.scalar_type();
// TODO: the TensorIterator reduction implementation of mean
// (mean_kernel_impl()) is unvectorized and leads to very poor performance
// for production workloads. Once that's fixed, the following code can be used
// in lieu of the sum + divide implementation below.
if (self.device().is_cpu()) {
int64_t dim_prod = 1;
if (!opt_dim.has_value() || opt_dim.value().empty() || self.ndimension() == 0) {
dim_prod = self.numel();
} else {
auto dim = opt_dim.value();
for (auto d : dim) {
dim_prod *= self.size(d);
}
}
auto& result_mut = const_cast<Tensor&>(result);
// For accuracy reasons, BF16/FP16 mean should be computed via the
// following approach:
// cast_fp32 -> sum -> div -> cast_bf16_or_fp16
//
// Such an approach is necessary because if we were to choose the same
// approach for BF16/FP16 as FP32 here, then it would have resulted in
// the following code-flow -
// cast_fp32 -> sum -> cast_bf16 -> cast_fp32 -> div -> cast_bf16,
// which, in turn, does not produce as accurate results.
bool is_half_type = (dtype == kHalf || dtype == kBFloat16);
auto sum_out_dtype = is_half_type ? ScalarType::Float : dtype;
result_mut = is_half_type ? result_mut.to(sum_out_dtype) : result_mut;
// If dtype is FP16 or BF16, self (input tensor) will initially be cast to
// FP32 in sum_out. This results in having to read that FP32 tensor again,
// but maybe in the future, we could revise the implementation to not
// materialize that intermediate FP32 tensor. That approach would probably
// require some modifications in binary_kernel_reduce_vec(),
// TensorIteratorBase::for_each(), and
// TensorIteratorBase::serial_for_each(), apart from sum kernel for CPU.
at::sum_out(result_mut, self, opt_dim, keepdim, sum_out_dtype).div_(dim_prod);
// After sum & div, cast result_mut back to BF16 or FP16, if required.
result_mut = is_half_type ? result_mut.to(dtype) : result_mut;
} else {
// device is not CPU
auto iter = at::meta::make_reduction_from_out_ty(
self, result, opt_dim, keepdim, dtype);
if (iter.numel() == 0) {
result.fill_(std::numeric_limits<double>::quiet_NaN());
} else {
mean_stub(iter.device_type(), iter);
}
}
}
In these two lines "result_mut = is_half_type ? result_mut.to(sum_out_dtype) : result_mut;" and "result_mut = is_half_type ? result_mut.to(dtype) : result_mut;" the storage of the tensor resut_mul will be changed as to() is not an inplace op, so the storage of given out tensor will not be update.
Versions
Collecting environment information...
PyTorch version: 2.4.0+cu121
Is debug build: False
CUDA used to build PyTorch: 12.1
ROCM used to build PyTorch: N/A
OS: Ubuntu 20.04.6 LTS (x86_64)
GCC version: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0
Clang version: Could not collect
CMake version: version 3.22.1
Libc version: glibc-2.31
Python version: 3.8.10 (default, Nov 22 2023, 10:22:35) [GCC 9.4.0] (64-bit runtime)
Python platform: Linux-5.4.0-124-generic-x86_64-with-glibc2.29
Is CUDA available: False
CUDA runtime version: No CUDA
CUDA_MODULE_LOADING set to: N/A
GPU models and configuration: No CUDA
Nvidia driver version: No CUDA
cuDNN version: No CUDA
HIP runtime version: N/A
MIOpen runtime version: N/A
Is XNNPACK available: True
CPU:
Architecture: x86_64
CPU op-mode(s): 32-bit, 64-bit
Byte Order: Little Endian
Address sizes: 39 bits physical, 48 bits virtual
CPU(s): 12
On-line CPU(s) list: 0-11
Thread(s) per core: 2
Core(s) per socket: 6
Socket(s): 1
NUMA node(s): 1
Vendor ID: GenuineIntel
CPU family: 6
Model: 151
Model name: 12th Gen Intel(R) Core(TM) i5-12400
Stepping: 2
CPU MHz: 3919.025
CPU max MHz: 5600.0000
CPU min MHz: 800.0000
BogoMIPS: 4992.00
Virtualization: VT-x
L1d cache: 288 KiB
L1i cache: 192 KiB
L2 cache: 7.5 MiB
L3 cache: 18 MiB
NUMA node0 CPU(s): 0-11
Vulnerability Itlb multihit: Not affected
Vulnerability L1tf: Not affected
Vulnerability Mds: Not affected
Vulnerability Meltdown: Not affected
Vulnerability Mmio stale data: Not affected
Vulnerability Spec store bypass: Mitigation; Speculative Store Bypass disabled via prctl and seccomp
Vulnerability Spectre v1: Mitigation; usercopy/swapgs barriers and __user pointer sanitization
Vulnerability Spectre v2: Mitigation; Enhanced IBRS, IBPB conditional, RSB filling
Vulnerability Srbds: Not affected
Vulnerability Tsx async abort: Not affected
Flags: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid aperfmperf tsc_known_freq pni pclmulqdq dtes64 monitor ds_cpl vmx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch cpuid_fault epb invpcid_single ssbd ibrs ibpb stibp ibrs_enhanced tpr_shadow vnmi flexpriority ept vpid ept_ad fsgsbase tsc_adjust bmi1 avx2 smep bmi2 erms invpcid rdseed adx smap clflushopt clwb intel_pt sha_ni xsaveopt xsavec xgetbv1 xsaves dtherm ida arat pln pts hwp hwp_notify hwp_act_window hwp_epp hwp_pkg_req umip pku ospke waitpkg gfni vaes vpclmulqdq rdpid movdiri movdir64b md_clear flush_l1d arch_capabilities
Versions of relevant libraries:
[pip3] numpy==1.22.0
[pip3] onnx==1.10.0
[pip3] onnxruntime==1.9.0
[pip3] torch==2.4.0
[pip3] triton==3.0.0
[conda] Could not collect
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