Logic Design Lab 4 Verilogintroduction Verilogintroduction
Instructor: Kuan Jen Lin () E-Mail: kjlin@mails.fju.edu.tw Web: http://vlsi.ee.fju.edu.tw/teacher/kjlin/kjlin.htm Room: SF 727B
FPGA Design Flow
Design entry Synthesis Functional simulation Fitting Timing simulation Programming & configuration HDL programming
Use CAD Tools to design and verify logic circuits
Create design
Draw schematic Use HDL (e.g. Verilog), like C programming
Verify design: give test patterns, and check if outputs meet specification.
Simulation
Graphical input/ouput Embedded test_modules in HDL programs
Emulation (Prototyping):
FPGA/CPLD Discrete components
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Schematic Capture
Simulation
What is an HDL?
A Hardware Description Language (HDL) is a high level programming language with special language constructs used to model the function of hardware logic circuits. The special language constructs provide you the ability to: Describe the connectivity (structure) of a circuit Describe the functionality (bhavior) of a circuit Describe a circuit at various levels of abstraction Describe the timing information and timing constraints of a circuit Express concurrency
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Why Use an HDL?
Model the design in higher level of abstraction
Reduce the design capturing effort Easy for handling complex design Separate from implementation, increase the protability Potential for design re-use
Mix behavioral/structural descriptioms in adesign
Model datapath and regular portion of circuit structurally Model control and regular portion of circuit behaviorally
Model the design and testbench with the same language
First Example
Structural Description (An SR Latch)
A module is defined name of the module
set
g1 g2
q qBar
module nandLatch Reset (q, qBar,set, reset); ouput q, qbar; input set, reset; nand g1 (q, qBar, set); nand g2 (qBar, q, reset); endmodule
Port declaration Type declaration
primitive gates with names and interconnections
Primitives
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Overview of Verilog Module
A verilog module includes the following parts:
module module_name (port list) ;
Declarations of port-type, wires, reg Instantiation of Primitives & Low-level modules always & initial Behavioral blocks assign-data flow statements
Task & function (testbench)
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endmodule
2X4 Decoder with enable
high-active or low-active
Source: Mano, Digital Design, 3th edition.
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Structural Description (pp. 177)
module decoder_2x4(D, A, B, enable); output [3:0] D; input A, B, enable; wire not_A, not_B, not_enable not (not_A, A); not (not_B, B); not (not_enable, enable); nand (D[0], not_A, not_B, not_enable); nand (D[1], not_A, B, not_enable); nand (D[2], A, not_B, not_enable); nand (D[3], A, B, not_enable); endmodule
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Continuous assignments( pp. 182) (Data flow description)
module decoder_2x4(D, A, B, enable); output [3:0] D; input A, B, enable; assign D[0] = ~(~A & ~B & ~enable); assign D[1] = ~(~A & B & ~enable); assign D[2] = ~(A & ~B & ~enable); assign D[4] = ~(A & B & ~enable); endmodule
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Operators (1/2)
Logic operators : return a value. &&, ||, ! assign a = b && c; Bitwise logic operators : return result in bus form. &, |, ~, assign a[2:0] = b[2:0] & c[2:0]; Equality operator: ==, != Reduction operator: a = &b; Relational operator: >=, > , <=, <
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Operators (2/2)
Are all Verilog operators synthesizable? Conditional operators Shift operators e.g. assign a = b << 2; Arithmetic operators
e.g. assign a = b+c; assign a = b-c; assign a = b*c; assign a = b/c; assign a = b%c; e.g. assign a = c ? x : y ;
Writing test bench or in process, do not use assign.
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Module Hierarchy
module fulladder(S, Co, A, B, Ci);
input A, B, Ci; output S, Co; assign Co = { (A ^ B) & Ci } | (A & B); assign S = A ^ B ^ Ci;
A Co S B Ci
endmodule
A B
Co Ci
A[3] B[3] C4
A B
A[2] B[2] C3
A B
A[1] B[1] C2
A B
A[0] B[0] C1
A B
Co FA3 Ci S
Co FA2 Ci S
Co FA1 Ci S
Co FA0 Ci S
C0
S[3] input [3:0] A, B; input C0; output [3:0] S; output C4; wire C1, C2, C3;
S[2]
S[1]
S[0]
module adder(S, C4, A, B, C0);
//Intermediate carries //Instantiate the fulladder
fulladder FA0(S[0], C1, A[0], B[0], C0); fulladder FA1(S[1], C2, A[1], B[1], C1); fulladder FA2(S[2], C3, A[2], B[2], C2); fulladder FA3(S[3], C4, A[3], B[3], C3);
Must not miss
endmodule
Behavioral Description
module decoder_2x4(D, A, B, enable); output [3:0] D; input A, B, enable; Sensitive list always @(A, B, enable) begin D=4b1111; // Dont miss this line if (~A & ~B & ~enable) D[0] = 0; if (~A & B & ~enable) D[1] = 0; if ( A & ~B & ~enable) D[2] = 0; if (A & B & ~enable) D[3] = 0; C-like end Procedural endmodule statements
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always (sensitive list) begin C-like procedural statements . end
Rules for combinational circuits All inputs to your combinational function must be listed in the sensitive list. Combinational output(s) must be assigned to every control path.
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Behavioral Description-2
module decoder_2x4(D, A, B, enable); output [3:0] D; input A, B, enable; always @(A, B, enable) begin D=4b1111; // Dont miss this line case ( {A, B, enable} ) 3b000: D[0] = 0; 3b010: D[1] = 0; 3b100: D[2] = 0; 3b110: D[3] = 0; // Other cases??? endcase end endmodule
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Behavioral modelling
A behavioral model of a module is an abstraction of how the module works. always defines a process Procedural statement
Suspend execution of this always process until a change occurs one of variable in the sensitive list. C programming-like Conversely, structural descriptions are concurrent statements.
Within an always process, the left side of = must be declared as register.
Register does not always need a physical storage.
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Verilog
module name( port list) Declarartion of signals Interconnections of low-level modules or primitives assign p= a&b assign Concurrent always@(...) begin running . end always@(...) begin .. end
endmodule
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Why use behavioral descrption?
Use behavioral model on early design stage.
HDLs are designed originally for simulation
Write testbench Partial behavioral descriptions can be synthesized to circuits.
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Create a Testbench For a Module
testbench Test Generator And Monitor Design Under Test (DUT)
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module_testBench
module testBench; wire w1, w2, w3, w4, w5; binaryToESeg d (w1, w2, w3, w4, w5); test_bToESeg t (w1, w2, w3, w4, w5); endmodule
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Test module
module test_bToESeg (output reg A, B, C, D, input eSeg); initial // two slashes introduce a single line comment begin $monitor ( $time,, "A = %b B = %b C = %b D = %b, eSeg = %b", A, B, C, D, eSeg); //waveform for simulating the nand lip lop #10 A = 0; B = 0; C = 0; D = 0; #10 D = 1; 0 A = x B = x C = x D = x, eSeg = x 10 A = 0 B = 0 C = 0 D = 0, eSeg = x #10 C = 1; D = 0; 12 A = 0 B = 0 C = 0 D = 0, eSeg = 1 #10 $finish; 20 A = 0 B = 0 C = 0 D = 1, eSeg = 1 end 22 A = 0 B = 0 C = 0 D = 1, eSeg = 0 endmodule 30 A = 0 B = 0 C = 1 D = 0, eSeg = 0 27
32 A = 0 B = 0 C = 1 D = 0, eSeg = 1
Interconnection of Design and Test Modules
testbench Test Generator And Monitor Design Under
eSeg A B C D
eSeg A B C D
Test (DUT)
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Standard Model of a Moore FSM
reset 0 00/0 1 0 11/0 01/1 1 0 x Q1 D Q clk
Input Comb. Circuit State Registers Comb. Circuit Output
Q0 x clk
reset D Q clk ~Q1 Z
Q0
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//D flip-flop module D_FF(D, Q, CLK, RST); input D, CLK, RST; output Q; reg Q; always @(posedge CLK or negedge RST) if(~RST) Q = 1'b0; else Q = D; endmodule
reset Q0 x clk x Q1 D Q clk Q0 D Q clk ~Q1
module state_machine(x, reset, clk, z); input x, Reset, clk; output z; wire D1, D0; assign z =~Q1 & Q0; assign D1 =Q0 & x; assign D0= x | Q1; D_FF A1(D1, Q1, clk, reset); D_FF A0(D0, Q0, clk, reset); endmodule
Z
behavioral model of FSM
module fsm (output reg z, input x, clk, reset reg [1:0] curStste, nextStste; 0 always @(x, curState) begin z=~curState[1] & curState[0]; nextState=0; if (curState ==0) if (x) nextState=1; if (curState ==1) if (x) nextState=3; if (curState ==3) if (x) nextState=3; else nextState =1; end end
reset 00/0 1 0 11/0 01/1 1 0
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D_FF
always @(posedge clk, negedge reset) begin if (~reset) curState <=0; else curState <= nextState; end endmodule
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Module Hierarchy
board
Display driver
count
m16
clk
m555
A counter example
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Top module
Bus concatenation module boardWithConcatenation; wire clock, eSeg, w3, w2, w1, w0; m16 counter ({w3, w2, w1, w0}, clock); m555 clockGen (clock); binaryToESeg disp (eSeg, w3, w2, w1, w0); instantiate
initial $monitor ($time,,,"count=%d, eSeg=%d", {w3, w2, w1, w0}, eSeg); endmodule
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m16 (Counter)
module m16 (output reg [3:0] ctr = 1, input clock); always @(posedge clock) ctr <= ctr + 1; endmodule
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A clock generator (simulation)
module m555 (output reg clock); initial #5 clock = 1; always #50 clock = ~ clock; endmodule
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Rules for Synthesizable Combinational Circuits All inputs to your combinational function must be listed in the sensitive list. Combinational output(s) must be assigned to every control path.
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module synAutoSensitivity ( input a, b, c, output reg f); always @( a, b ,c) always @( *) if (a == 1) f = b; else f = c; endmodule
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module synAutoSensitivity ( input a, b, c, output reg f); always @(*) begin f = c; if (a == 1) f = b; end endmodule
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Inferred Latches
amodule synAutoSensitivity ( input a, b, c, output reg f); always @(*) if (a == 1) f=b&c; // else f = ? endmodule
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Use case Statement Using Case Statement
Using full_case (attributes) explicitly specify (truth table form) or a default item to fully specify. Specify Dont Care situations for input and output.
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Use case Statement (cont.)
Truth table method module fred List each input (output reg f, combination input a, b, c); Assign to output(s) in always @ (a or b or c) each case item. case ({a, b, c})
3b000: f = 1b0; 3b001: f = 1b1; 3b010: f = 1b1; 3b011: f = 1b1; 3b100: f = 1b1; 3b101: f = 1b0; 3b110: f = 1b0; 3b111: f = 1b1; endcase endmodule
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Use case Statement (cont.)
module fred (output reg f, input a, b, c); always @(a or b or c) case({a,b,c}) 3b000: f = 1b0; 3b101: f = 1b0; 3b110: f = 1b0; default: f = 1b1; endcase endmodule
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Specify dont care Rules
You cant say if (a == 1bx) this has meaning in ab simulation, but not in 00 01 11 10 c synthesis. 0 x 1 0 1 However, an unknown x 1 1 x 1 1 on the right-hand side will be interpreted as a The inverse function was implemented; dont care.
xs taken as ones.
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Specify dont care (cont.)
module caseExample( (output reg f, input a, b, c); always @ (a or b or c) case ({a, b, c}) 3b001: f = 1b1; 3b010: f = 1b1; 3b011: f = 1b1; 3b100: f = 1b1; 3b110: f = 1b0; 3b111: f = 1b1; default: f = 1bx; endcase endmodule
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Rules for Synthesizable Sequential Circuits
The sensitive list includes only the edges of the clock, reset and preset conditions. Inside the always block, the reset and preset conditions are specified first. Any register assigned to in the sequential always block will be implemented using flipflops. The <= states that all the transfers in the whole system that are specified should occur concurrently.
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if (~reset),,,,
Latch inferences
module synLatchReset( Q, g, d, reset); input g, d, reset; output Q; reg Q; always @(*) if (~reset) Q = 0; else if (g) Q = d; // else Q = ? endmodule To infer a latch, two situations must exist in the always statement: At least one control path must exist that does not assign to an output. The sensitivity list must not contain any edge-sensitive specifications. (levelsensitive )
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Flip Flop inferences
module synDFF( q, clock, d); input clock, d; output q; reg q; always @(posedge clock, negedge reset, posedge set) begin if (~reset) q <= 0; else if (set) q <= 1; else q <= d; end endmodule The form of the description must follow these rule : Always statement must specify the edge for each signal. The first statement follow the always must be if. procedural assignments must either be blocking or non-blocking assignment.
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Conclusion
Type of Logic Combinational Output Assign To An output must be assigned to in all control path Edge Specifiers in Sensitivity List Not allowed. The whole input set must be in the sensitivity list.The construct @(*) assure this.
Interred latch
There must exist Not allowed. at least one control path where an output is not assign to. From this omission,the tool infers a latch. No affect. Required from the presence of an edge specifier, the tool infers a flip flop. All registers in the always block are clocked by the specified edge.
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Inferred flip flop
