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The First Computer
Introduction
Digital Electronics
The Babbage Difference Engine (1832) 25,000 parts cost: 17,470
2
ENIAC - The first electronic computer (1946)
Copyright 2005 Pearson Addison-Wesley. All rights reserved.
1-4
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The First Integrated Circuits
Bipolar logic 1960s
ECL 3-input Gate Motorola 1966
Copyright 2005 Pearson Addison-Wesley. All rights reserved.
1-5
Intel 4004 Micro-Processor
1971 1000 transistors 1 MHz operation
Intel Pentium (IV) microprocessor
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Moores Law
In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months. He made a prediction that semiconductor technology will double its effectiveness every 18 months
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LOG2 OF THE NUMBER OF COMPONENTS PER INTEGRATED FUNCTION
Moores Law
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
Electronics, April 19, 1965.
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Evolution in Complexity
K 1,000,000 100,000 10,000 1,000 100 10 1 1975
Transistor Counts
1 Billion Transistors
i486 i386 80286 8086
Pentium III Pentium II Pentium Pro Pentium
1980
1985 1990
1995 2000
Projected
2005 2010
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12
Courtesy, Intel
1975
Source: Intel
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Moores law in Microprocessors
100 1000
Die Size Growth
Die size (mm)
100
2X growth in 1.96 years!
P6 Pentium proc 10 8080 8008 4004 1 1970 1990 Year 2000 2010 1980 1990 Year 2000 2010 8086 8085 286 386 P6 486 Pentium proc
Transistors (MT)
10 1 0.1 0.01 8086 8085 8080 8008 4004 1980 386 286 486
~7% growth per year ~2X growth in 10 years
0.001
1970
Die size grows by 14% to satisfy Moores Law
Transistors on Lead Microprocessors double every 2 years
13
Courtesy, Intel
14
Courtesy, Intel
Frequency
10000 1000 Doubles every 2 years 100
Power Dissipation
P6 Pentium proc
Frequency (Mhz)
Power (Watts)
100 486 10 1 0.1 1970 8085 8086 286 386
P6 Pentium proc
10 8086 286 1 4004 8085 8080 486 386
8008
8080 8008 4004 1980 1990 Year 2000 2010
0.1 1971 1974 1978 Year 1985 1992 2000
Lead Microprocessors frequency doubles every 2 years
Lead Microprocessors power continues to increase
15
Courtesy, Intel
16
Courtesy, Intel
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Power will be a major problem
100000 10000
Power density
10000
Power Density (W/cm2)
Power (Watts)
1000 100 10 Pentium proc
18KW 5KW 1.5KW 500W
1000
Rocket Nozzle Nuclear Reactor
286 8086 386 486 8085 8080 8008 1 4004
100
0.1 1971 1974 1978 1985 1992 Year 2000 2004 2008
8086 10 4004 Hot Plate P6 8008 8085 Pentium proc 386 286 486 8080 1 1970 1980 1990 2000 Year
2010
Power delivery and dissipation will be prohibitive
Power density too high to keep junctions at low temp
18
17
Courtesy, Intel
Courtesy, Intel
Not Only Microprocessors
Cell Phone
Challenges in Digital Design
DSM 1/DSM
Macroscopic Issues
Time-to-Market Millions of Gates High-Level Abstractions Reuse & IP: Portability Predictability etc.
Small Signal RF
Microscopic Problems
Power RF
Digital Cellular Market (Phones Shipped)
Power Management
1996 1997 1998 1999 2000
Units
48M 86M 162M 260M 435M
Analog Baseband
Digital Baseband (DSP + MCU)
Ultra-high speed design Interconnect Noise, Crosstalk Reliability, Manufacturability Power Dissipation Clock distribution. Everything Looks a Little Different
(data from Texas Instruments)
19 20
and Theres a Lot of Them!
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Why Scaling?
Technology shrinks by 0.7/generation With every generation can integrate 2x more functions per chip; chip cost does not increase significantly Cost of a function decreases by 2x But
How to design chips with more and more functions? Design engineering population does not double every two years
Design Abstraction Levels
SYSTEM
MODULE + GATE
CIRCUIT
DEVICE G S n+ D n+
Hence, a need for more efficient design methods
Exploit different levels of abstraction
21 22
Why?
Why should we be concerned with digital circuit design at all?
Some one still has to design and implement the module libraries
Approximately every two years requires a redesign of the library
Why?
Why should we be concerned with digital circuit design at all?
Creating an adequate model of a cell or module requires an in-depth understanding of its internal operation
Identify the dominant performance parameters of a given design Recognize the critical timing path
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Why?
Why should we be concerned with digital circuit design at all?
Library-based approach works fine when the design constrains (speed, cost, or power) are not stringent. At High performance, designers tend to push technology to its limits Hierarchical approach tends to become less attractive
Why?
Why should we be concerned with digital circuit design at all?
The performance of, for instance, an adder can be substantially influenced by the way it is connected to its environment.
Interconnect parasitics
Customize
Why?
Why should we be concerned with digital circuit design at all?
Scaling tends to emphasize some other deficiencies.
Clock signals for synchronization and supply lines
Connecting more cells to a supply line can cause a voltage drop over the wire.
Why?
Why should we be concerned with digital circuit design at all?
New design issues
One must be able to model and analyze their impact into circuit topology and behavior.
A fabricated circuit does not always exhibit the exact waveforms one might expect from advance simulators
Deviations can be caused by variations in the fabrication
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Fundamental Design Metrics
Functionality Cost
NRE (fixed) costs - design effort RE (variable) costs - cost of parts, assembly, test
Cost of Integrated Circuits
NRE (non-recurring engineering) costs
Fixed cost to produce the design
design effort design verification effort mask generation
Reliability, robustness
Noise margins Noise immunity
Influenced by the design complexity and designer productivity More pronounced for small volume products
Recurring costs proportional to product volume
silicon processing
also proportional to chip area
Performance
Speed (delay) Power consumption; energy
Time-to-market
assembly (packaging) test
fixed cost cost per IC = variable cost per IC + ----------------volume
NRE Cost is Increasing
Silicon Wafer
Single die
Wafer
From http://www.amd.com
07/02/2013
Recurring Costs
cost of die + cost of die test + cost of packaging variable cost = ---------------------------------------------------------------final test yield cost of wafer cost of die = ----------------------------------dies per wafer die yield
(wafer diameter/2)2 wafer diameter dies per wafer = ---------------------------------- --------------------------die area 2 die area
Yield Example
Example
wafer size of 12 inches, die size of 2.5 cm2, 1 defects/cm2, (measure of manufacturing process complexity) 252 dies/wafer (remember, wafers round & dies square) die yield of 16% 252 x 16% = only 40 dies/wafer die yield ! =3
Die cost is strong function of die area
proportional to the third or fourth power of the die area
die yield
= (1 + (defects per unit area die area)/)-
Examples of Cost Metrics (1994)
Chip 386DX 486DX2 PowerPC 601 HP PA 7100 DEC Alpha Super SPARC Pentium Metal layers 2 3 4 3 3 3 3 Line Wafer Defects Area Dies/ Yield Die width cost /cm2 (mm2) wafer cost 0.90 $900 1.0 43 360 71% $4 0.80 $1200 1.0 81 181 54% $12 0.80 $1700 1.3 121 115 28% $53 0.80 0.70 0.70 0.80 $1300 $1500 $1700 $1500 1.0 1.2 1.6 1.5 196 234 256 296 66 53 48 40 27% $73
Reliability
Noise in Digital Integrated Circuits
Noise unwanted variations of voltages and currents at the logic nodes
from two wires placed side by side
capacitive coupling
- voltage change on one wire can influence signal on the neighboring wire - cross talk
v(t)
19% $149 13% $272 9% $417
inductive coupling
- current change on one wire can influence signal on the neighboring wire
i(t)
VDD
from noise on the power and ground supply rails
can influence signal levels in the gate
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Example of Capacitive Coupling
Signal wire glitches as large as 80% of the supply voltage will be common due to crosstalk between neighboring wires as feature sizes continue to scale
Crosstalk vs. Technology
Pulsed Signal 0.12m CMOS 0.16m CMOS
Black line quiet Red lines pulsed Glitches strength vs technology 0.25m CMOS 0.35m CMOS
From Dunlop, Lucent, 2000
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