Overview of Computer Organization
Chapter 1 S. Dandamudi
Outline
Introduction
Basic Terminology and Notation
Processor
Execution cycle Pipelining RSIC and CISC
Views of computer systems Users view Programmers view
Advantages of high-level languages Why program in assembly language?
Memory
Basic memory operations Design issues
Architects view Implementers view
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Input/Output Interconnection: The glue Historical Perspective Technological Advances
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Introduction
Some basic terms
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Computer architecture Computer organization Computer design Computer programming Users view Programmers view Architects view Implementers view
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Various views of computer systems
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Introduction (contd) Term K (kilo) M (mega) G (giga) T (tera) P (peta)
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Decimal 103 106 109 1012 1015
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Binary 210 220 230 240 250
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A Users View of Computer Systems
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A Programmers View
Depends on the type and level of language used A hierarchy of languages
Machine language Assembly language High-level language Application programs increasing level of abstraction
Machine-independent
High-level languages/application programs
Machine-specific
Machine and assembly languages
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A Programmers View (contd)
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A Programmers View (contd)
Machine language
Native to a processor Consists of alphabet 1s and 0s 1111 1111 0000 0110 0000 1010 0000 0000B
Assembly language
Slightly higher-level language Human-readable One-to-one correspondence with most machine language instructions
inc
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count
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A Programmers View (contd)
Readability of assembly language instructions is much better than the machine language instructions
Machine language instructions are a sequence of 1s and 0s
Assembly Language inc mov and add
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Machine Language (in Hex) FF060A00 C7060C002D00 80260E0080 83060F000A
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result class_size,45 mask,128 marks,10
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A Programmers View (contd)
Assemblers translate between assembly and machine languages
TASM MASM NASM
Compiler translates from a high-level language to machine language
Directly Indirectly via assembly language
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A Programmers View (contd)
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A Programmers View (contd)
High-level languages versus low-level languages In C:
result = count1 + count2 + count3 + count4
In Pentium assembly language:
mov add add add mov
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AX,count1 AX,count2 AX,count3 AX,count4 result,AX
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A Programmers View (contd)
Some simple high-level language instructions can be expressed by a single assembly instruction Assembly Language
inc mov and add result size,45 mask1,128 marks,10
C
result++; size = 45; mask1 &= 128; marks += 10;
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A Programmers View (contd)
Most high-level language instructions need more than one assembly instruction C Assembly Language
size = value; mov mov sum += x + y + z; mov add add add mov
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AX,value size,AX AX,sum AX,x AX,y AX,z sum,AX
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A Programmers View (contd)
Instruction set architecture (ISA)
An important level of abstraction Specifies how a processor functions
Defines a logical processor
Various physical implementations are possible
All logically look the same Different implementations may differ in
Performance Price
Two popular examples of ISA specifications
SPARC and JVM
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Advantages of High-Level Languages
Program development is faster
High-level instructions Fewer instructions to code
Program maintenance is easier
For the same reasons as above
Programs are portable
Contain few machine-dependent details Can be used with little or no modifications on different types of machines Compiler translates to the target machine language Assembly language programs are not portable
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Why Program in Assembly Language?
Two main reasons:
Efficiency
Space-efficiency Time-efficiency
Accessibility to system hardware
Space-efficiency
Assembly code tends to be compact
Time-efficiency
Assembly language programs tend to run faster
Only a well-written assembly language program runs faster Easy to write an assembly program that runs slower than its high-level language equivalent
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Architects View
Looks at the design aspect from a high level
Much like a building architect Does not focus on low level details Uses higher-level building blocks
Ex: Arithmetic and logical unit (ALU)
Consists of three main components
Processor Memory I/O devices
Glued together by an interconnect
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Architects View (contd)
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Architects View (contd)
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Implementers View
Implements the designs generated by architects
Uses digital logic gates and other hardware circuits
Example
Processor consists of
Control unit Datapath ALU Registers
Implementers are concerned with design of these components
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Implementers View (contd)
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Implementers View (contd)
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Implementers View (contd)
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Processor
Execution cycle
Fetch Decode Execute
von Neumann architecture
Stored program model No distinction between data and instructions Instructions are executed sequentially
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Processor (contd)
Pipelining
Overlapped execution Increases throughput
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Processor (contd)
Another way of looking at pipelined execution
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Processor (contd)
RISC and CISC designs
Reduced Instruction Set Computer
Uses simple instructions Operands are assumed to be in processor registers Not in memory Simplifies design 4Example: Fixed instruction size
Complex Instruction Set Computer
Uses complex instructions Operands can be in registers or memory Instruction size varies Typically uses a microprogram
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Processor (contd)
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Processor (contd)
Variations of the ISA-level can be implemented by changing the microprogram
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Memory
Ordered sequence of bytes
The sequence number is called the memory address Byte addressable memory
Each byte has a unique address Almost all processors support this
Memory address space
Determined by the address bus width Pentium has a 32-bit address bus
address space = 4GB (232)
Itanium with 64-bit address bus supports
264 bytes of address space
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Memory (contd)
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Memory (contd)
Memory unit
Address Data Control signals
Read Write
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Memory (contd)
Read cycle
1. Place address on the address bus 2. Assert memory read control signal 3. Wait for the memory to retrieve the data
Introduce wait states if using a slow memory
4. Read the data from the data bus 5. Drop the memory read signal
In Pentium, a simple read takes three clocks cycles
Clock 1: steps 1 and 2 Clock 2: step 3 Clock 3 : steps 4 and 5
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Memory (contd)
Write cycle
1. 2. 3. 4. Place address on the address bus Place data on the data bus Assert memory write signal Wait for the memory to retrieve the data
Introduce wait states if necessary
5. Drop the memory write signal
In Pentium, a simple write also takes three clocks
Clock 1: steps 1 and 3 Clock 2: step 2 Clock 3 : steps 4 and 5
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Byte Ordering
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Byte Ordering (contd)
Multibyte data address pointer is independent of the endianness
100 in our example
Little-endian
Used by Pentium
Big-endian
Default in MIPS and PowerPC
On modern processors
Configurable
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Design Issues
Slower memories
Problem: Speed gap between processor and memory Solution: Cache memory
Use small amount of fast memory Make the slow memory appear faster Works due to reference locality
Size limitations
Limited amount of physical memory
Overlay technique Programmer managed
Virtual memory
Automates overlay management Some additional benefits
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Design Issues (contd)
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Design Issues (contd)
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Input/Output
I/O devices are interfaced via an I/O controller
Takes care of low-level operations details
Several ways of mapping I/O
Memory-mapped I/O
Reading and writing similar to memory read/write Uses same memory read and write signals Most processors use this I/O mapping
Isolated I/O
Separate I/O address space Separate I/O read and write signals are needed Pentium supports isolated I/O Also supports memory-mapped I/O
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Input/Output (contd)
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Input/Output (contd)
Several ways of transferring data
Programmed I/O
Program uses a busy-wait loop Anticipated transfer
Direct memory access (DMA)
Special controller (DMA controller) handles data transfers Typically used for bulk data transfer
Interrupt-driven I/O
Interrupts are used to initiate and/or terminate data transfers Powerful technique Handles unanticipated transfers
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Interconnection
System components are interconnected by buses
Bus: a bunch of parallel wires
Uses several buses at various levels
On-chip buses
Buses to interconnect ALU and registers A, B, and C buses in our example Data and address buses to connect on-chip caches
Internal buses
PCI, AGP, PCMCIA
External buses
Serial, parallel, USB, IEEE 1394 (FireWire)
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Interconnection (contd)
Bus is a shared resource
Bus transactions
Sequence of actions to complete a well-defined activity Involves a master and a slave Memory read, memory write, I/O read, I/O write
Bus operations
A bus transaction may perform one or more bus operations Pentium burst read 4Transfers four memory words 4Bus transaction consists of four memory read operations
Bus arbitration
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Historical Perspective
The early generations
Difference engine of Charles Babbage
Vacuum tube generation
Around the 1940s and 1950s
Transistor generation
Around the 1950s and 1960s
IC generation
Around the 1960s and 1970s
VLSI generation
Since the mid-1970s
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Technological Advances
Transistor density
Until 1990s, doubled every 18 to 24 months Since then, doubling every 2.5 years
Memory density
Until 1990s, quadrupled every 3 years Since then, slowed down (4X in 5 years)
Disk capacities
3.5 form factor 2.5 form factor 1.8 form factor (e.g., portable USB-powered drives)
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Technological Advances (contd)
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Technological Advances (contd)
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Technological Advances (contd)
Last slide
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