Lecture-12
Test-2 Solution
Design Issues
How do you identify the module issuing the
interrupt?
How do you deal with multiple interrupts?
i.e. an interrupt handler being interrupted
Identifying Interrupting Module (1)
Different line for each module
PC
Limits number of devices
Software poll
CPU asks each module in turn
Slow
Identifying Interrupting Module (2)
Daisy Chain or Hardware poll
Interrupt Acknowledge sent down a chain
Module responsible places vector on bus
CPU uses vector to identify handler routine
Bus Master
Module must claim the bus before it can raise
interrupt
e.g. PCI & SCSI
Multiple Interrupts
Each interrupt line has a priority
Higher priority lines can interrupt lower
priority lines
If bus mastering, only current master can
interrupt
Example - PC Bus
80x86 has one interrupt line
8086 based systems use one 8259A interrupt
controller
8259A has 8 interrupt lines
Sequence of Events
8259A accepts interrupts
8259A determines priority
8259A signals 8086 (raises INTR line)
CPU Acknowledges
8259A puts correct vector on data bus
CPU processes interrupt
ISA Bus Interrupt System
ISA bus chains two 8259As together
Link is via interrupt 2
Gives 15 lines
16 lines less one for link
IRQ 9 is used to re-route anything trying to use
IRQ 2
Backwards compatibility
Incorporated in chip set
82C59A Interrupt
Controller
Direct Memory Access
Interrupt driven and programmed I/O require
active CPU intervention
Transfer rate is limited
CPU is tied up
DMA is the answer
DMA Function
Direct memory access (DMA) is a process in
which an external device takes over the control of
system bus from the CPU.
DMA is for high-speed data transfer from/to
mass storage peripherals, e.g. hard disk drive,CDROM, and sometimes video controllers.
The basic idea of DMA is to transfer blocks of
data directly between memory and peripherals.
The data dont go through the microprocessor
but the system data bus is occupied.
DMA Function
Normal transfer of one data byte takes up to
29 clock cycles. The DMA transfer requires
only 5 clock cycles.
Nowadays, DMA can transfer data as fast as 60
MB per second or more. The transfer rate is
limited by the speed of memory and
peripheral devices.
Typical DMA Module Diagram
DMA Operation
CPU tells DMA controller: Read/Write
Device address
Starting address of memory block for data
Amount of data to be transferred
CPU carries on with other work
DMA controller deals with transfer
DMA controller sends interrupt when finished
DMA Transfer
Cycle Stealing
DMA controller takes over bus for a cycle
Transfer of one word of data
Not an interrupt
CPU does not switch context
CPU suspended just before it accesses bus
i.e. before an operand or data fetch or a data
write
Slows down CPU but not as much as CPU
doing transfer
DMA Configurations (1)
Single Bus, Detached DMA controller
Each transfer uses bus twice
I/O to DMA then DMA to memory
CPU is suspended twice
DMA Configurations (2)
Single Bus, Integrated DMA controller
Controller may support >1 device
Each transfer uses bus once
DMA to memory
CPU is suspended once
DMA Configurations (3)
Separate I/O Bus
Bus supports all DMA enabled devices
Each transfer uses bus once
DMA to memory
CPU is suspended once
Intel 8237A DMA Controller
Interfaces to 80x86 family and DRAM
When DMA module needs buses it sends HOLD signal to processor
CPU responds HLDA (hold acknowledge)
DMA module can use buses
E.g. transfer data from memory to disk
1. Device requests service of DMA by pulling DREQ (DMA request) high
2. DMA puts high on HRQ (hold request),
3. CPU finishes present bus cycle (not necessarily present instruction) and puts
high on HDLA (hold acknowledge). HOLD remains active for duration of DMA
4. DMA activates DACK (DMA acknowledge), telling device to start transfer
5. DMA starts transfer by putting address of first byte on address bus and
activating MEMR; it then activates IOW to write to peripheral. DMA
decrements counter and increments address pointer. Repeat until count
reaches zero
6. DMA deactivates HRQ, giving bus back to CPU
Fly-By
While DMA using buses processor idle
Processor using bus, DMA idle
Known as fly-by DMA controller
Data does not pass through and is not stored in
DMA chip
DMA only between I/O port and memory
Not between two I/O ports or two memory locations
Can do memory to memory via register
8237 contains four DMA channels
Programmed independently
Any one active
Numbered 0, 1, 2, and 3
