Lets talk about
communication!
We first discuss the universal synchronous
asynchronous receive transmit (USART) protocol
Also referred to as serial communication
We will discuss both asynchronous communication and
synchronous communication
Always a transmitter and receiver (but can have multiple
receivers)
However, we will mostly focus on asynchronous comm.
We will also discuss how to use the USART as a master
SPI node
But NOT until we discuss SPI!!!
Asynchronous comm.
Why do we call it asynchronous
communication?
Asynchronous comm.
Why do we call it asynchronous
communication?
A common clock signal is NOT required between
the receiver and transmitter
The data being transmitted need not be synchronized
with the receiver
So how do we synchronize the data???
Asynchronous comm.
Why do we call it asynchronous
communication?
A common clock signal is NOT required between
the receiver and transmitter
The data being transmitted need not be synchronized
with the receiver
So how do we synchronize the data???
Complicated hardware, but the short answer is:
Use a start and stop bit
ASCII Letters
Recall: When you press a key on the
keyboard, the result is an 8-bit binary number
American standard code for information interchange
ASCII sequence on the serial line
Lets have a look at sending the letter A down
the serial line!
Note from the ASCII table, A = 0100 0001b
Using one stop bit and one start bit
ASCII sequence on the serial line
Things to note
When idle, the serial line is HIGH
The start bit pulls the line low to start the sequence
The data is piped down the line backwards
Recall: there is ALWAYS a transmitter and receiver
Serial timing
The falling edge of the start bit triggers the
timing sequence of the receiver
The receiver then waits 1.5 bit times before
sampling the receive line to get the first data bit
The receiver then waits 1 bit time thereafter to
sample each successive data bit
Note: All of the timing issues are handled by
the USART itself NOT the programmer
Programmer responsibilities
So what is the programmer responsible for?
The programmer (YOU) must ensure that the
parameters associated with the serial lines are
IDENTICAL on both the transmit and receive end
Setting the correct number of bits (usually 8 but can be
more or less)
Using a parity bit (typically not used)
Setting the BAUD rate
Speed of the serial communication
Defined as the inverse of time/bit
Number of stop bits (usually 1 or 2)
RS-232
Note: This is the serial protocol, but the serial line
itself need not be a wire
Could be infrared, radio, optical, etc.
Arguably the most common serial comm. medium is
RS-232 (pre-USB)
Provides a greater distance for RELIABLE serial comm.
RS-232 uses an inverted scheme for transmission
A logic HIGH is a voltage less than -3 V
A logic LOW is a voltage greater than 3 V
Why the heck do we do this???
RS-232
Note: This is the serial protocol, but the serial line
itself need not be a wire
Could be infrared, radio, optical, etc.
Arguably the most common serial comm. medium is
RS-232 (pre-USB)
Provides a greater distance for RELIABLE serial comm.
RS-232 uses an inverted scheme for transmission
A logic HIGH is a voltage less than -3 V
A logic LOW is a voltage greater than 3 V
Why the heck do we do this???
Allow for hardware error checking, broken wire = 0 V
USART on the AVR
The ATMega328p (your dev. Board) has 1 USART
USART0
Ability to operate full duplex (also half duplex more
later)
Independent receive and transmit registers
Can operate in Asynchronous or Synchronous mode
Master or slave operation in synchronous mode
High resolution baud rate (bits per second measure)
USART on the AVR
Support for serial frames with 5, 6, 7, 8, or 9 bits
Supports 1 or 2 stop bits
Odd or even parity generator
Parity checked by hardware NOT software
Data overrun detection
Frame error detection
False start bit detection (filtering)
USART on the AVR
Three independent interrupts (more later)
TX complete, RX complete, TX data register empty
Multi-processor communication mode
Typically using 9-bit data operation
NOT strictly necessary
Double speed mode
Only in asynchronous mode
Register description
Each USART has three control and status
registers
UCSRnA/B/C
Each USART has an I/O Data register
UDRn
Used for both received AND transmitted data
Same I/O address
Each USART has its own baud rate register
12-bits (of two 8-bit registers)
UBRRnL and UBRRnH
Clock generation
Synchronous mode:
The Arduino can NOT do synchronous data
communication
The external clock is not brought out on the dev. Board
(XCKn)
The RedBoard CAN
The external clock pins are:
PD4 (XCK)
Internal clock generation
Each USART has an internal baud rate
generator
Set in the UBBRn register
Similar to the timers we will discuss
The frequency (or in this case baud rate) is:
Down counter that generates a prescaled clock signal
based on the match value in UBBRn
BAUD = f_clk/(N * UBRRn + 1)
BAUD (bits per second transmitted, bps)
N: depends on the mode of operation
f_clk: system clock frequency
Computing the baud value
In asynchronous mode:
We can operate at normal speed or double speed
We will discuss double speed requirements in a minute
Determined by the U2Xn bit in UCSRnA
Also as a synchronous master
Computing the baud value
Double speed operation
U2Xn = 1 in UCSRnA
Reduces the prescale factor from 16 to 8
Hence double the speed
Drawbacks (receiver):
Receiver only has access to half the number of samples
for data sampling and clock synchronization
MUST have a very accurate clock on the receiving end
for accurate data reception
External Clock
Only used in synchronous mode
Used to synchronize the receiver with the
transmitter
On Redboard
XCKn is sampled by a synchronization register then
passed to an edge detector BEFORE it can be used for
the transmitter/receiver
Introduces two CPU delay cycles
Max external frequency:
f_XCKn < f_clk/4
Serial Frame Formats
The AVR family supports 5, 6, 7, 8, or 9 data
bits
1-start bit
Parity bit (none, even, or odd)
1 or 2 stop bits
Example frame
Start bit is ALWAYS low
Idle line is always high
Parity bit comes after the data
Then the stop bit(s)
Frame format
Serial frame format is set in both the UCSRnB
and UCSRnC register
UCSZn 2:0: USART character size
UPMn 1:0: Parity mode
USBSn: Stop bits
Both the receiver and the transmitter MUST
use the same settings
We should ALWAYS disable comms when
changing these settings
Any comms in progress will be corrupted!
Initialization
Each USART needs to be initialized prior to use
Straightforward:
Set the baud rate
Set the frame format
Enable the transmitter/receiver
Enable interrupts (if ISRs are to be used)
We will see several examples soon!
Transmission of Data (5-8 bits)
Must enable the transmitter
TXEN in UCSRnB
Normal port operation on Txn is overridden
Load the transmit buffer with the data to be
transmitted
Data is then transmitted to a shift register when
ready
Writing the data to the UDRn I/O location!
Either in an idle state or after the last stop bit from a
previous transmission
The data is then clocked out in a complete frame:
At the baud rate or the rate of XCKn
What about when 9-bits are used?
Essentially the same protocol with one MAJOR
difference!
The 9th bit must be written to the TXB8 bit in
UCSRnB BEFORE the low byte is written to UDRn
Transmitter interrupts
Two interrupts can be generated by the
transmitter
UDREn: USART data register empty
Indicates that the transmit buffer is ready to receive data
When the UDRIEn (interrupt enable) bit is set, the
interrupt will be executed as long as UDREn is set
Clear the interrupt condition by writing data to UDRn
Note: If interrupt driven data transmission is used,
you MUST write new data to UDRn in the ISR or the
interrupt will persist!!!
Transmitter interrupts
TXCn: Transmission complete
Set when all data is shifted out of the shift register
Interrupt is enabled when TXCIEn bit is set in UCSRnB
Interrupt is cleared by hardware once the ISR is complete
ISRs:
ISR(USARTn_UDRE_vect){//do stuff}
ISR(USARTn_TX_vect){//do stuff}
Receiving data (5 to 8 bits)
Data begins clocking into the receive shift
register AFTER the first start bit is received
Data stops when the first stop bit is received
Note: The second stop bit is ignored unless in
multi-processor mode (later)
Data is then copied to the receive buffer
Can be read from the UDRn I/O location
What about 9-bits?
Similar to 9-bit transmission
9th bit MUST be read from the RXB8n bit in
UCSRnB BEFORE reading the low bits from UDRn
NOTE: This rule also applies to reading the
status bits!
FEn: Frame Error
DORn: Data overrun
UPEn: Parity Error
Receiver interrupt
Only one!
Receive complete interrupt RXCn
Interrupts when data is ready to be read from UDRn
Note: When this interrupt is enabled, the data
MUST be read in the RXCn ISR to clear the
interrupt flag
ISR:
ISR(USARTn_RX_vect){ //do things}
Disabling the USART
When disabling the transmitter:
Clearing TXENn will NOT become effective until
ongoing AND pending transmissions are complete
When disabling the receiver
Effective immediately
All data pending and currently being received will be
lost
Asynchronous range and clock
synchronization
If the transmitter and receiver are out of sync
the receiver can't synchronize the incoming
frame to the start bit
Incorrect baud rate
Low quality clock
Noisy line
etc.
Asynchronous range and clock
synchronization
We need to determine the maximum receiver
baud rate error
Look at the data sheet for the equations to compute
this
Normal Speed:
Asynchronous range and clock
synchronization
Double speed:
What exactly does this mean for
us??? (data sheet)
Recall: U2Xn = 0 regular speed
U2Xn = 1 double speed mode
Multi-processor comm mode
Ability to use serial communication as a master
with several slaves via a serial bus
Set the MPCMn bit in UCSRnA
Enables a filtering function of incoming frames
If the frames do not contain address information they are
NOT put into the receive buffer
Transmitter is NOT effected but MUST handle the
data differently
Address indicator
When 5-8 data bits are used:
When 9 bits are used:
The stop bit indicates address vs. data
The 9th bit (RXB8n) indicates address vs. data
In both cases:
When the indicator is set
The frame is an address
When the indicator is cleared
The frame is data
Steps for communicating using
multi-processor mode
Set all slave uP to Multi-Processor comm mode
Master uP sends an address frame
Slaves read the UDRn register to determine if the
address was theirs
ALL slaves read the frame
If selected, clear the MPCMn bit and wait for data
If not selected, keep waiting for the next address byte
Selected uP receives data until a new address is
sent
Once data transfer is complete, the uP sets its
MPCMn bit and the process begins again
Lets have a look at the USART
registers
Both the read and write UDRn register share
the same I/O address
Can't read while writing and vice versa
When 5, 6, and 7 data bit sizes are used:
The remaining high bits are ignored by the
transmitter and set to zero by the receiver
Registers cont.
RXCn: USART receive complete
TXCn: USART transmit complete
Set when data is ready to be read from the receive
buffer
Set when the entire data frame is shifted out of the
transmit buffer
UDREn: Transmit buffer is ready to receive
new data
Can generate an interrupt
Registers cont.
FEn: Frame error
DORn: Data overrun
Valid until the UDRn buffer is read
Receive buffer is full
UPEn: Parity error
If parity is enabled
U2Xn: Double speed mode
MPCMn: Multi-processor mode
Registers cont.
RXCIEn: RX complete interrupt enable
TXCIEn: TX complete interrupt enable
UDRIEn: Data register empty interrupt enable
RXENn: Receiver enabled
TXENn: Transmitter enabled
Registers cont.
UCSZn2: Character size
RXB8n: Received data bit 8
Combined with the UCSZn 1:0 bits in UCSRnC
Used for the 9th bit
9-bit data reception
TXB8n: Transmitted data bit 8
9-bit data transmission
Registers cont.
UMSELn 1:0: Mode select bits
UPMn 1:0: Parity mode bits
Registers cont.
USBSn: Stop bit selection
UCSZn: Character size
Registers cont.
UCPOLn: Clock polarity
UBRRnL and UBRRnH: Baud rate register
12-bit register to set the baud rate (upper bits MUST
be zero)
Example 1 (printing strings)
Example 1 cont.
Example 1 cont.
Example 2 ( receive and transmit
using a wait loop)
Example 2 cont.
Example 3 (using ISR)
Example 3 cont.
Example 4 (using avr-libc/stdio)
Example 4 cont.
Example 4 cont.
For more info on Example 4 visit and READ
the avr-libc documentation page for stdio.h
