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Design of Two-Stage Operational Amplifier: Shahin Shah (12116053), Abhinav Singhal (12116001) | PDF | Operational Amplifier | Analog Circuits
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Design of Two-Stage Operational Amplifier: Shahin Shah (12116053), Abhinav Singhal (12116001)

This document summarizes the design of a two-stage CMOS operational amplifier that operates at ±1.8V power supply. It introduces the design procedure, which involves meeting specifications for gain, slew rate, common-mode rejection ratio, gain bandwidth product, and phase margin. It describes the challenges of designing op-amps at reduced supply voltages and transistor sizes. Simulation results are planned to validate the design meets specifications and analyze differential and common mode gain versus frequency and phase.

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Shahin Shah
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183 views2 pages

Design of Two-Stage Operational Amplifier: Shahin Shah (12116053), Abhinav Singhal (12116001)

This document summarizes the design of a two-stage CMOS operational amplifier that operates at ±1.8V power supply. It introduces the design procedure, which involves meeting specifications for gain, slew rate, common-mode rejection ratio, gain bandwidth product, and phase margin. It describes the challenges of designing op-amps at reduced supply voltages and transistor sizes. Simulation results are planned to validate the design meets specifications and analyze differential and common mode gain versus frequency and phase.

Uploaded by

Shahin Shah
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Design of Two-Stage Operational Amplifier

Shahin Shah (12116053), Abhinav Singhal(12116001)


Indian Institute of Technology, Roorkee

AbstractThis paper presents a design of Two Stage CMOS


operational amplifier, which operates at 1.8V power supply
using umc 2m CMOS technology. The OP-AMP designed is a
two-stage CMOS OP-AMP. Design and Simulation has been
carried out in Cadence.

Formula used:

Index Terms 2 stage CMOS op-amp, design, simulation and


results.

I. INTRODUCTION
The designing of high performance analog integrated
circuits is becoming most essential with the continuous trend
towards the reduced supply voltages and transistor channel
length. MOS is most success among all because it can be
scaled down to smaller dimensions for higher performance.
The size can be reduced to micrometer or nanometer for getting
higher performance. On scaling down the Transistor size the
most important advantage is we can integrate more number of
transistor on the same size and we can get a faster amplifier
compared to previous one. This leads to continuous growth of
the processing capacity per chip and operating frequency.
In most of the electronics circuits the Operational
Amplifiers is the most common building blocks. So as the
transistor channel length and power supply is reduced then the
design of Op amps face continuous challenge. Due to different
aspect ratio (W/L), there is a tradeoff among speed, gain,
power and the other parameters. The purpose of the design
methodology in this paper is to propose accurate equations for
the design of high- gain 2 staged CMOS op-amp. For this, a
simple analysis with some meaningful parameters (such as gain
bandwidth, phase margin, etc.) is performed.
II. TWO STAGE OP-AMP DESIGN PROCEDURE
The first aspect considered in the design was to meet the
desired specifications. Based on a clear understanding of the
specifications, we have chosen the standard CMOS op-amp
circuit topology in our design.
TABLE I. Specification of two-stage CMOS op-amp
Specification Names

Values

Supply VDD

1.8V

Gain

>65 dB

Slew Rate

0.1 V/ns

CMRR

80 dB

Gain Bandwidth Product

60 MHz

Phase Margin

60o

Positive ICMR:

Negative ICMR:

60o phase margin requires that gm6 = 2.2gm2 (CL/Cc)


if all the roots are 10GB
gm1= gm2= gmI, gm6= gmII

DESIGN CHALLENGES AND TRADE-OFFS


Write your design challenges and trade-offs here.
III. SIMULATION RESULTS
All simulation results, figure and tables and discussion will
be here. Every figure and table should have discussion.
Figure 1. Schematic

Figure 2. Differential Mode Gain v/s Frequency

Figure 3. Differential Mode Gain v/s Phase


Figure 5. Common Mode Gain v/s Phase

FIGURE 4. COMMON MODE GAIN V/S FREQUENCY


Fig. 1. Example of a figure caption. (figure caption)

IV. CONCLUSIONS
This paper presented the full design and analysis of a two
stage CMOS Op-Amp.
REFERENCES
[1] B. Razavi, Design of Analog CMOS Integrated Circuits, New
York: Mc-Graw Hill,2001.

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