PIC16F/LF1826/27

14.0

FIXED VOLTAGE REFERENCE

(FVR)

14.1

Independent Gain Amplifiers

The Fixed Voltage Reference, or FVR, is a stable

voltage reference, independent of VDD, with 1.024V,
2.048V or 4.096V selectable output levels. The output
of the FVR can be configured to supply a reference
voltage to the following:

The output of the FVR supplied to the ADC,

Comparators, and DAC is routed through two
independent programmable gain amplifiers. Each
amplifier can be configured to amplify the reference
voltage by 1x, 2x or 4x, to produce the three possible
voltage levels.

The ADFVR<1:0> bits of the FVRCON register are

used to enable and configure the gain amplifier settings
for the reference supplied to the ADC module. Reference Section 15.0 Analog-to-Digital Converter
(ADC) Module for additional information.

ADC input channel

ADC positive reference
Comparator positive input
Digital-to-Analog Converter (DAC)

The FVR can be enabled by setting the FVREN bit of

the FVRCON register.

The CDAFVR<1:0> bits of the FVRCON register are

used to enable and configure the gain amplifier settings
for the reference supplied to the DAC and comparator
module. Reference Section 16.0 Digital-to-Analog
Converter (DAC) Module and Section 17.0 Comparator Module for additional information.

14.2

FVR Stabilization Period

When the Fixed Voltage Reference module is enabled, it

requires time for the reference and amplifier circuits to
stabilize. Once the circuits stabilize and are ready for use,
the FVRRDY bit of the FVRCON register will be set. See
Section 29.0 Electrical Specifications for the
minimum delay requirement.

FIGURE 14-1:

VOLTAGE REFERENCE BLOCK DIAGRAM

ADFVR<1:0>

CDAFVR<1:0>

FVREN
FVRRDY

2009 Microchip Technology Inc.

2
X1
X2
X4

FVR BUFFER1
(To ADC Module)

X1
X2
X4

FVR BUFFER2
(To Comparators, DAC)

+
_

1.024V Fixed
Reference

Preliminary

DS41391B-page 135

PIC16F/LF1826/27
REGISTER 14-1:

FVRCON: FIXED VOLTAGE REFERENCE CONTROL REGISTER

R/W-0/0

R-q/q

R/W-0/0

R/W-0/0

R/W-0/0

R/W-0/0

R/W-0/0

R/W-0/0

FVREN

FVRRDY(1)

Reserved

Reserved

CDAFVR1

CDAFVR0

ADFVR1

ADFVR0

bit 7

bit 0

Legend:
R = Readable bit

W = Writable bit

U = Unimplemented bit, read as 0

u = Bit is unchanged

x = Bit is unknown

-n/n = Value at POR and BOR/Value at all other Resets

1 = Bit is set

0 = Bit is cleared

q = Value depends on condition

bit 7

FVREN: Fixed Voltage Reference Enable bit

0 = Fixed Voltage Reference is disabled
1 = Fixed Voltage Reference is enabled

bit 6

FVRRDY: Fixed Voltage Reference Ready Flag bit(1)

0 = Fixed Voltage Reference output is not ready or not enabled
1 = Fixed Voltage Reference output is ready for use

bit 5-4

Reserved: Read as 0. Maintain these bits clear.

bit 3-2

CDAFVR<1:0>: Comparator and DAC Fixed Voltage Reference Selection bit

00 = Comparator and DAC Fixed Voltage Reference Peripheral output is off.
01 = Comparator and DAC Fixed Voltage Reference Peripheral output is 1x (1.024V)
10 = Comparator and DAC Fixed Voltage Reference Peripheral output is 2x (2.048V)(2)
11 = Comparator and DAC Fixed Voltage Reference Peripheral output is 4x (4.096V)(2)

bit 1-0

ADFVR<1:0>: ADC Fixed Voltage Reference Selection bit

00 = ADC Fixed Voltage Reference Peripheral output is off.
01 = ADC Fixed Voltage Reference Peripheral output is 1x (1.024V)
10 = ADC Fixed Voltage Reference Peripheral output is 2x (2.048V)(2)
11 = ADC Fixed Voltage Reference Peripheral output is 4x (4.096V)(2)

Note 1:
2:

FVRRDY is always 1 on devices with the LDO (PIC16F1826/27).

Fixed Voltage Reference output cannot exceed VDD.

TABLE 14-1:
Name
FVRCON
Legend:

SUMMARY OF REGISTERS ASSOCIATED WITH THE FVR MODULE

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Register
on page

FVREN

FVRRDY

Reserved

Reserved

CDAFVR1

CDAFVR0

ADFVR1

ADFVR0

136

Shaded cells are unused by the FVR module.

DS41391B-page 136

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PIC16F/LF1826/27
15.0

The ADC can generate an interrupt upon completion of

a conversion. This interrupt can be used to wake-up the
device from Sleep.

ANALOG-TO-DIGITAL
CONVERTER (ADC) MODULE

The Analog-to-Digital Converter (ADC) allows

conversion of an analog input signal to a 10-bit binary
representation of that signal. This device uses analog
inputs, which are multiplexed into a single sample and
hold circuit. The output of the sample and hold is
connected to the input of the converter. The converter
generates a 10-bit binary result via successive
approximation and stores the conversion result into the
ADC result register (ADRES). Figure 15-1 shows the
block diagram of the ADC.
The ADC voltage reference is software selectable to be
either internally generated or externally supplied.

FIGURE 15-1:

ADC BLOCK DIAGRAM

ADNREF = 1

VREF-

ADNREF = 0

VDD

VSS
ADPREF = 0X
ADPREF = 11
VREF+

AN0

00000

AN1

00001

AN2

00010

AN3

00011

AN4

00100

AN5

00101

AN6

00110

AN7

00111

AN8

01000

AN9

01001

AN10

01010

AN11

01011

DAC

11110

FVR Buffer1

11111

ADPREF = 10

ADC
10

GO/DONE
ADFM

0 = Left Justify
1 = Right Justify
16

ADON
VSS

ADRESH

ADRESL

CHS<4:0>

Note:

When ADON = 0, all multiplexer inputs are disconnected.

2009 Microchip Technology Inc.

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PIC16F/LF1826/27
15.1

15.1.4

ADC Configuration

When configuring and using the ADC the following

functions must be considered:

Port configuration
Channel selection
ADC voltage reference selection
ADC conversion clock source
Interrupt control
Result formatting

15.1.1

The ADC can be used to convert both analog and

digital signals. When converting analog signals, the I/O
pin should be configured for analog by setting the
associated TRIS and ANSEL bits. Refer to
Section 12.0 I/O Ports for more information.
Note:

15.1.2

The source of the conversion clock is software selectable via the ADCS bits of the ADCON1 register. There
are seven possible clock options:

PORT CONFIGURATION

Analog voltages on any pin that is defined

as a digital input may cause the input buffer to conduct excess current.

FOSC/2
FOSC/4
FOSC/8
FOSC/16
FOSC/32
FOSC/64
FRC (dedicated internal oscillator)

The time to complete one bit conversion is defined as

TAD. One full 10-bit conversion requires 11.5 TAD periods as shown in Figure 15-2.
For correct conversion, the appropriate TAD specification must be met. Refer to the A/D conversion requirements in Section 29.0 Electrical Specifications for
more information. Table 15-1 gives examples of appropriate ADC clock selections.
Note:

CHANNEL SELECTION

CONVERSION CLOCK

There are 14 channel selections available:

AN<11:0> pins
DAC Output
FVR (Fixed Voltage Reference) Output

Unless using the FRC, any changes in the

system clock frequency will change the
ADC clock frequency, which may
adversely affect the ADC result.

Refer to Section 16.0 Digital-to-Analog Converter

(DAC) Module and Section 14.0 Fixed Voltage
Reference (FVR) for more information on these channel selections.
The CHS bits of the ADCON0 register determine which
channel is connected to the sample and hold circuit.
When changing channels, a delay is required before
starting the next conversion. Refer to Section 15.2
ADC Operation for more information.

15.1.3

ADC VOLTAGE REFERENCE

The ADPREF bits of the ADCON1 register provides

control of the positive voltage reference. The positive
voltage reference can be:
VREF+ pin
VDD
FVR
The ADNREF bits of the ADCON1 register provides
control of the negative voltage reference. The negative
voltage reference can be:
VREF- pin
VSS
See Section 14.0 Fixed Voltage Reference (FVR)
for more details on the fixed voltage reference.

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PIC16F/LF1826/27
TABLE 15-1:

ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES

Device Frequency (FOSC)
Device Frequency (FOSC)

ADC Clock Period (TAD)

ADC
Clock Source

ADCS<2:0>

32 MHz

20 MHz

16 MHz

8 MHz

4 MHz

1 MHz

Fosc/2

000

62.5ns(2)

100 ns(2)

125 ns(2)

250 ns(2)

500 ns(2)

2.0 s

Fosc/4

100

125 ns

(2)

(2)

(2)

(2)

1.0 s

4.0 s

Fosc/8

001

0.5 s(2)

400 ns(2)

0.5 s(2)

1.0 s

2.0 s

8.0 s(3)

Fosc/16

101

800 ns

800 ns

1.0 s

2.0 s

4.0 s

16.0 s(3)

Fosc/32

010

1.0 s

1.6 s

2.0 s

4.0 s

8.0 s(3)

32.0 s(3)

s(3)

64.0 s(3)

Fosc/64
FRC
Legend:
Note 1:
2:
3:
4:

2.0 s

110
x11

1.0-6.0 s

200 ns

3.2 s
(1,4)

1.0-6.0 s

250 ns

4.0 s
(1,4)

1.0-6.0 s

500 ns

8.0
(1,4)

s(3)

1.0-6.0 s

(1,4)

16.0

1.0-6.0 s

(1,4)

1.0-6.0 s(1,4)

Shaded cells are outside of recommended range.

The FRC source has a typical TAD time of 1.6 s for VDD.
These values violate the minimum required TAD time.
For faster conversion times, the selection of another clock source is recommended.
When the device frequency is greater than 1 MHz, the FRC clock source is only recommended if the conversion will be
performed during Sleep.

FIGURE 15-2:

ANALOG-TO-DIGITAL CONVERSION TAD CYCLES

TCY - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11
b4
b1
b0
b6
b7
b2
b9
b8
b3
b5
Conversion starts
Holding capacitor is disconnected from analog input (typically 100 ns)
Set GO bit
On the following cycle:
ADRESH:ADRESL is loaded, GO bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.

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PIC16F/LF1826/27
15.1.5

INTERRUPTS

15.1.6

The ADC module allows for the ability to generate an

interrupt upon completion of an Analog-to-Digital
conversion. The ADC Interrupt Flag is the ADIF bit in
the PIR1 register. The ADC Interrupt Enable is the
ADIE bit in the PIE1 register. The ADIF bit must be
cleared in software.

RESULT FORMATTING

The 10-bit A/D conversion result can be supplied in two

formats, left justified or right justified. The ADFM bit of
the ADCON1 register controls the output format.
Figure 15-3 shows the two output formats.

Note 1: The ADIF bit is set at the completion of

every conversion, regardless of whether
or not the ADC interrupt is enabled.
2: The ADC operates during Sleep only
when the FRC oscillator is selected.
This interrupt can be generated while the device is
operating or while in Sleep. If the device is in Sleep, the
interrupt will wake-up the device. Upon waking from
Sleep, the next instruction following the SLEEP instruction is always executed. If the user is attempting to
wake-up from Sleep and resume in-line code execution, the GIE and PEIE bits of the INTCON register
must be disabled. If the GIE and PEIE bits of the
INTCON register are enabled, execution will switch to
the Interrupt Service Routine.
Please refer to Section 8.0 Interrupts for more
information.

FIGURE 15-3:

10-BIT A/D CONVERSION RESULT FORMAT

ADRESH

(ADFM = 0)

ADRESL

MSB

LSB

bit 7

bit 0

bit 7

10-bit A/D Result

(ADFM = 1)

Unimplemented: Read as 0

MSB
bit 7

LSB
bit 0

Unimplemented: Read as 0

DS41391B-page 140

bit 0

bit 7

bit 0
10-bit A/D Result

Preliminary

2009 Microchip Technology Inc.

PIC16F/LF1826/27
15.2
15.2.1

15.2.4

ADC Operation
STARTING A CONVERSION

To enable the ADC module, the ADON bit of the

ADCON0 register must be set to a 1. Setting the GO/
DONE bit of the ADCON0 register to a 1 will start the
Analog-to-Digital conversion.
Note:

15.2.2

The GO/DONE bit should not be set in the

same instruction that turns on the ADC.
Refer to Section 15.2.6 A/D Conversion Procedure.

COMPLETION OF A CONVERSION

When the conversion is complete, the ADC module will:

Clear the GO/DONE bit
Set the ADIF Interrupt Flag bit
Update the ADRESH and ADRESL registers with
new conversion result

15.2.3

TERMINATING A CONVERSION

If a conversion must be terminated before completion,

the GO/DONE bit can be cleared in software. The
ADRESH and ADRESL registers will be updated with
the partially complete Analog-to-Digital conversion
sample. Incomplete bits will match the last bit
converted.
Note:

A device Reset forces all registers to their

Reset state. Thus, the ADC module is
turned off and any pending conversion is
terminated.

ADC OPERATION DURING SLEEP

The ADC module can operate during Sleep. This

requires the ADC clock source to be set to the FRC
option. When the FRC clock source is selected, the
ADC waits one additional instruction before starting the
conversion. This allows the SLEEP instruction to be
executed, which can reduce system noise during the
conversion. If the ADC interrupt is enabled, the device
will wake-up from Sleep when the conversion
completes. If the ADC interrupt is disabled, the ADC
module is turned off after the conversion completes,
although the ADON bit remains set.
When the ADC clock source is something other than
FRC, a SLEEP instruction causes the present conversion to be aborted and the ADC module is turned off,
although the ADON bit remains set.

15.2.5

SPECIAL EVENT TRIGGER

The Special Event Trigger of the CCPx/ECCPX module

allows periodic ADC measurements without software
intervention. When this trigger occurs, the GO/DONE
bit is set by hardware and the Timer1 counter resets to
zero.

TABLE 15-2:

SPECIAL EVENT TRIGGER

Device

CCPx/ECCPx

PIC16F/LF1826

ECCP1

PIC16F/LF1827

CCP4

Using the Special Event Trigger does not assure proper

ADC timing. It is the users responsibility to ensure that
the ADC timing requirements are met.
Refer to Section 23.0 Capture/Compare/PWM Modules (ECCP1, ECCP2, CCP3, CCP4) for more
information.

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DS41391B-page 141

PIC16F/LF1826/27
15.2.6

A/D CONVERSION PROCEDURE

EXAMPLE 15-1:

This is an example procedure for using the ADC to

perform an Analog-to-Digital conversion:
1.

2.

3.

4.
5.
6.

7.
8.

Configure Port:
Disable pin output driver (Refer to the TRIS
register)
Configure pin as analog (Refer to the ANSEL
register)
Configure the ADC module:
Select ADC conversion clock
Configure voltage reference
Select ADC input channel
Turn on ADC module
Configure ADC interrupt (optional):
Clear ADC interrupt flag
Enable ADC interrupt
Enable peripheral interrupt
Enable global interrupt(1)
Wait the required acquisition time(2).
Start conversion by setting the GO/DONE bit.
Wait for ADC conversion to complete by one of
the following:
Polling the GO/DONE bit
Waiting for the ADC interrupt (interrupts
enabled)
Read ADC Result.
Clear the ADC interrupt flag (required if interrupt
is enabled).

A/D CONVERSION

;This code block configures the ADC

;for polling, Vdd and Vss references, Frc
;clock and AN0 input.
;
;Conversion start & polling for completion
; are included.
;
BANKSEL
ADCON1
;
MOVLW
B11110000 ;Right justify, Frc
;clock
MOVWF
ADCON1
;Vdd and Vss Vref
BANKSEL
TRISA
;
BSF
TRISA,0
;Set RA0 to input
BANKSEL
ANSEL
;
BSF
ANSEL,0
;Set RA0 to analog
BANKSEL
ADCON0
;
MOVLW
B00000001 ;Select channel AN0
MOVWF
ADCON0
;Turn ADC On
CALL
SampleTime
;Acquisiton delay
BSF
ADCON0,ADGO ;Start conversion
BTFSC
ADCON0,ADGO ;Is conversion done?
GOTO
$-1
;No, test again
BANKSEL
ADRESH
;
MOVF
ADRESH,W
;Read upper 2 bits
MOVWF
RESULTHI
;store in GPR space
BANKSEL
ADRESL
;
MOVF
ADRESL,W
;Read lower 8 bits
MOVWF
RESULTLO
;Store in GPR space

Note 1: The global interrupt can be disabled if the

user is attempting to wake-up from Sleep
and resume in-line code execution.
2: Refer to Section 15.3 A/D Acquisition
Requirements.

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PIC16F/LF1826/27
15.2.7

ADC REGISTER DEFINITIONS

The following registers are used to control the

operation of the ADC.

REGISTER 15-1:

ADCON0: A/D CONTROL REGISTER 0

U-0

R/W-0/0

R/W-0/0

R/W-0/0

R/W-0/0

R/W-0/0

R/W-0/0

R/W-0/0

CHS4

CHS3

CHS2

CHS1

CHS0

GO/DONE

ADON

bit 7

bit 0

Legend:
R = Readable bit

W = Writable bit

U = Unimplemented bit, read as 0

u = Bit is unchanged

x = Bit is unknown

-n/n = Value at POR and BOR/Value at all other Resets

1 = Bit is set

0 = Bit is cleared

bit 7

Unimplemented: Read as 0

bit 6-2

CHS<4:0>: Analog Channel Select bits

00000 = AN0
00001 = AN1
00010 = AN2
00011 = AN3
00100 = AN4
00101 = AN5
00110 = AN6
00111 = AN7
01000 = AN8
01001 = AN9
01010 = AN10
01011 = AN11
01100 = Reserved. No channel connected.

11101 = Reserved. No channel connected.

11110 = DAC output(1)
11111 = FVR (Fixed Voltage Reference) Buffer 1 Output(2)

bit 1

GO/DONE: A/D Conversion Status bit

1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle.
This bit is automatically cleared by hardware when the A/D conversion has completed.
0 = A/D conversion completed/not in progress

bit 0

ADON: ADC Enable bit

1 = ADC is enabled
0 = ADC is disabled and consumes no operating current

Note 1:
2:

See Section 16.0 Digital-to-Analog Converter (DAC) Module for more information.
See Section 14.0 Fixed Voltage Reference (FVR) for more information.

2009 Microchip Technology Inc.

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PIC16F/LF1826/27
REGISTER 15-2:

ADCON1: A/D CONTROL REGISTER 1

R/W-0/0

R/W-0/0

R/W-0/0

R/W-0/0

U-0

R/W-0/0

R/W-0/0

R/W-0/0

ADFM

ADCS2

ADCS1

ADCS0

ADNREF

ADPREF1

ADPREF0

bit 7

bit 0

Legend:
R = Readable bit

W = Writable bit

U = Unimplemented bit, read as 0

u = Bit is unchanged

x = Bit is unknown

-n/n = Value at POR and BOR/Value at all other Resets

1 = Bit is set

0 = Bit is cleared

bit 7

ADFM: A/D Result Format Select bit

1 = Right justified. Six Most Significant bits of ADRESH are set to 0 when the conversion result is
loaded.
0 = Left justified. Six Least Significant bits of ADRESL are set to 0 when the conversion result is
loaded.

bit 6-4

ADCS<2:0>: A/D Conversion Clock Select bits

000 = FOSC/2
001 = FOSC/8
010 = FOSC/32
011 = FRC (clock supplied from a dedicated RC oscillator)
100 = FOSC/4
101 = FOSC/16
110 = FOSC/64
111 = FRC (clock supplied from a dedicated RC oscillator)

bit 3

Unimplemented: Read as 0

bit 2

ADNREF: A/D Negative Voltage Reference Configuration bit

0 = VREF- is connected to AVSS
1 = VREF- is connected to external VREF-

bit 1-0

ADPREF<1:0>: A/D Positive Voltage Reference Configuration bits

00 = VREF+ is connected to AVDD
01 = Reserved
10 = VREF+ is connected to external VREF+
11 = VREF+ is connected to internal fixed voltage reference

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PIC16F/LF1826/27
REGISTER 15-3:

ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0

R/W-x/u

R/W-x/u

R/W-x/u

R/W-x/u

R/W-x/u

R/W-x/u

R/W-x/u

R/W-x/u

ADRES9

ADRES8

ADRES7

ADRES6

ADRES5

ADRES4

ADRES3

ADRES2

bit 7

bit 0

Legend:
R = Readable bit

W = Writable bit

U = Unimplemented bit, read as 0

u = Bit is unchanged

x = Bit is unknown

-n/n = Value at POR and BOR/Value at all other Resets

1 = Bit is set

0 = Bit is cleared

bit 7-0

ADRES<9:2>: ADC Result Register bits

Upper 8 bits of 10-bit conversion result

REGISTER 15-4:

ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0

R/W-x/u

R/W-x/u

R/W-x/u

R/W-x/u

R/W-x/u

R/W-x/u

R/W-x/u

R/W-x/u

ADRES1

ADRES0

bit 7

bit 0

Legend:
R = Readable bit

W = Writable bit

U = Unimplemented bit, read as 0

u = Bit is unchanged

x = Bit is unknown

-n/n = Value at POR and BOR/Value at all other Resets

1 = Bit is set

0 = Bit is cleared

bit 7-6

ADRES<1:0>: ADC Result Register bits

Lower 2 bits of 10-bit conversion result

bit 5-0

Reserved: Do not use.

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PIC16F/LF1826/27
REGISTER 15-5:

ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1

R/W-x/u

R/W-x/u

R/W-x/u

R/W-x/u

R/W-x/u

R/W-x/u

R/W-x/u

R/W-x/u

ADRES9

ADRES8

bit 7

bit 0

Legend:
R = Readable bit

W = Writable bit

U = Unimplemented bit, read as 0

u = Bit is unchanged

x = Bit is unknown

-n/n = Value at POR and BOR/Value at all other Resets

1 = Bit is set

0 = Bit is cleared

bit 7-2

Reserved: Do not use.

bit 1-0

ADRES<9:8>: ADC Result Register bits

Upper 2 bits of 10-bit conversion result

REGISTER 15-6:

ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1

R/W-x/u

R/W-x/u

R/W-x/u

R/W-x/u

R/W-x/u

R/W-x/u

R/W-x/u

R/W-x/u

ADRES7

ADRES6

ADRES5

ADRES4

ADRES3

ADRES2

ADRES1

ADRES0

bit 7

bit 0

Legend:
R = Readable bit

W = Writable bit

U = Unimplemented bit, read as 0

u = Bit is unchanged

x = Bit is unknown

-n/n = Value at POR and BOR/Value at all other Resets

1 = Bit is set

0 = Bit is cleared

bit 7-0

ADRES<7:0>: ADC Result Register bits

Lower 8 bits of 10-bit conversion result

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PIC16F/LF1826/27
15.3

A/D Acquisition Requirements

For the ADC to meet its specified accuracy, the charge

holding capacitor (CHOLD) must be allowed to fully
charge to the input channel voltage level. The Analog
Input model is shown in Figure 15-4. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge
the capacitor CHOLD. The sampling switch (RSS)
impedance varies over the device voltage (VDD), refer
to Figure 15-4. The maximum recommended
impedance for analog sources is 10 k. As the

EQUATION 15-1:
Assumptions:

source impedance is decreased, the acquisition time

may be decreased. After the analog input channel is
selected (or changed), an A/D acquisition must be
done before the conversion can be started. To calculate
the minimum acquisition time, Equation 15-1 may be
used. This equation assumes that 1/2 LSb error is used
(1,024 steps for the ADC). The 1/2 LSb error is the
maximum error allowed for the ADC to meet its
specified resolution.

ACQUISITION TIME EXAMPLE

Temperature = 50C and external impedance of 10k 5.0V V DD

T ACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
= T AMP + T C + T COFF
= 2s + T C + [ ( Temperature - 25C ) ( 0.05s/C ) ]
The value for TC can be approximated with the following equations:

1
= V CHOLD
V AP P LI ED 1 -------------------------n+1

(2
)1

;[1] VCHOLD charged to within 1/2 lsb

TC

----------

RC
V AP P LI ED 1 e = V CHOLD

;[2] VCHOLD charge response to VAPPLIED

Tc

---------

1
RC
;combining [1] and [2]
V AP P LI ED 1 e = V A PP LIE D 1 -------------------------n+1

(2
)1

Note: Where n = number of bits of the ADC.

Solving for TC:

T C = C HOLD ( R IC + R SS + R S ) ln(1/511)
= 10pF ( 1k + 7k + 10k ) ln(0.001957)
= 1.12 s
Therefore:
T A CQ = 2s + 1.12s + [ ( 50C- 25C ) ( 0.05S /C ) ]
= 4.42s

Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin
leakage specification.

2009 Microchip Technology Inc.

Preliminary

DS41391B-page 147