Data Converters-II
Analog Electronics (EEE/INSTR C341)
Date: 23/04/2016
Dr. Anita Agrawal,
BITS, Pilani-K.K.Birla Goa Campus
D/A CONVERTERS
24-04-2016 13:11
Anita Agrawal
Sampling frequency: Nyquist criteria/Sampling
theorem which states that:
In order to represent/convert the analog signal
correctly, the sampling frequency fsample must be
atleast twice the highest frequency component
fa(max) of the analog signal.
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Anita Agrawal
Nyquist criteria contd
alias
The highest analog frequency can be no greater than
one-half the sampling frequency
The frequency fa(max) is known as the Nyquist
frequency
fsample f a (max)
24-04-2016 13:11
Anita Agrawal
Nyquist criteria contd
If an input frequency component is greater than the
Nyquist frequency, then a unique form of distortion
called alias is produced which is equal to the
difference in the input frequency and the sampling
rate.
24-04-2016 13:11
Anita Agrawal
Amplitude resolution
It represents the finest discernible change in the signal and is
often represented in terms of no. of bits.
Important to note that once the size of the digital word is
chosen and the peak amplitude is fixed, the input signal must
stay within the specific bounds or gross distortion will occur.
For ex.
24-04-2016 13:11
Anita Agrawal
Applied to DSP: performs operations on incoming data.
D/A conversion
Reconstruction filter: Low pass reconstruction filter to
smoothen the DAC output by eliminating high frequency
contents that result from the fast transitions of the stairstep
24-04-2016 13:11
Anita Agrawal
Other D/A converters
Inverted R-2R ladder D/A converter
Switched-Capacitor D/A converter
Serial D/A converter
Pipelined D/A converter
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Anita Agrawal
Inverted R-2R
Anita Agrawal
Serial D/A converter
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Anita Agrawal
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Drawbacks
Requires considerable external circuitry to decide
upon which switch is to be open and which to close
during the conversion process.
Errors due to:
Parasitic capacitances
Capacitive parasitic capacitances
Switch parasitic capacitances
Clock-feed through
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Anita Agrawal
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Conversion speed is slower
Advantages:
Can be realised in a small chip area
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Anita Agrawal
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Pipelined DAC
Modified serial charge distribution converter.
(n+1) equal valued capacitors, 4n+2 switches for n-bit
conversion
Cascades n+1 serial charge redistribution converters
Uses a new clocking scheme.
Has an improved conversion scheme than the serial
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Anita Agrawal
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Anita Agrawal
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Drawbacks
Non-ideal effects in the converter affects the
conversion accuracy.
Capacitor mismatch
Incomplete charge transfer due to non-zero Rswitch C time
constants
Clock feedthrough due to overlap capacitances, channel
charges and charge pumping in the switches.
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Anita Agrawal
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