Serial Peripheral Interface Bus

1 Interface
SPI
Master

SCLK
MOSI
MISO
SS

SCLK
MOSI
MISO
SS

SPI
Slave

The SPI bus species four logic signals:

SCLK : Serial Clock (output from master).
MOSI : Master Output, Slave Input (output from
master).

Single Master to Single Slave : basic SPI bus example.

MISO : Master Input, Slave Output (output from

slave).

SPI
Master

SCLK
MOSI
MISO
SS1
SS2
SS3

SS : Slave Select (active low, output from master).

SCLK
MOSI
MISO
SS

SPI
Slave

SCLK
MOSI
MISO
SS

SPI
Slave

Alternative naming conventions are also widely used, and

SPI port pin names for particular IC products may dier
from those depicted in these illustrations:
Serial Clock:
SCLK : SCK, CLK.

SCLK
MOSI
MISO
SS

SPI
Slave

Master Output --> Slave Input:

MOSI : SIMO, SDI(for slave devices), DI, DIN, SI,
MTST.

Single Master to Multiple Slaves : typical SPI bus example using

multiple selects.

Master Input <-- Slave Output:

MISO : SOMI, SDO (for slave devices ), DO,
DOUT, SO, MRSR.

The Serial Peripheral Interface (SPI) bus is a

synchronous serial communication interface specication used for short distance communication, primarily Slave Select:
in embedded systems. The interface was developed by
Motorola and has become a de facto standard. Typical
SS : nCS, CS, CSB, CSN, EN, nSS, STE, SYNC,
applications include Secure Digital cards and liquid crysSSQ.
tal displays.

The MOSI/MISO convention requires that, on devices

using the alternate names, SDI on the master be connected to SDO on the slave, and vice versa. Chip select polarity is rarely active high, although some notations
(such as SS or CS instead of nSS or nCS) suggest otherwise. Slave select is used instead of an addressing conSometimes SPI is called a four-wire serial bus, contrastcept.
ing with three-, two-, and one-wire serial buses. The
SPI may be accurately described as a synchronous serial interface,[1] but it is dierent from the Synchronous
Serial Interface (SSI) protocol, which is also a four-wire 2 Operation
synchronous serial communication protocol, but employs
dierential signaling and provides only a single simplex The SPI bus can operate with a single master device and
communication channel.
with one or more slave devices.
SPI devices communicate in full duplex mode using a
master-slave architecture with a single master. The master device originates the frame for reading and writing.
Multiple slave devices are supported through selection
with individual slave select (SS) lines.

2 OPERATION

If a single slave device is used, the SS pin may be xed

to logic low if the slave permits it. Some slaves require a
falling edge of the chip select signal to initiate an action.
An example is the Maxim MAX1242 ADC, which starts
conversion on a highlow transition. With multiple slave
devices, an independent SS signal is required from the
master for each slave device.

as the TSC2101 by Texas Instruments, or 12-bit words for

many digital-to-analog or analog-to-digital converters.
Every slave on the bus that has not been activated using its
chip select line must disregard the input clock and MOSI
signals, and must not drive MISO.

Most slave devices have tri-state outputs so their MISO 2.2 Clock polarity and phase
signal becomes high impedance (logically disconnected)
when the device is not selected. Devices without tri-state
CPOL=0
outputs cannot share SPI bus segments with other devices;
SCK CPOL=1
only one such slave could talk to the master.
SS

2.1

CPHA=0

Data transmission

Master

Slave

Memory

Memory

SCLK

MOSI

CPHA=1

MISO

Cycle #
MISO
MOSI

Cycle #
MISO
MOSI

A timing diagram showing clock polarity and phase. The red vertical line represents CPHA=0 and the blue vertical line represents
CPHA=1

In addition to setting the clock frequency, the master must

also congure the clock polarity and phase with respect
to the data. Motorola SPI Block Guide[2] names these
two options as CPOL and CPHA respectively, and most
To begin communication, the bus master congures the vendors have adopted that convention.
clock, using a frequency supported by the slave device,
typically up to a few MHz. The master then selects the The timing diagram is shown to the right. The timing is
slave device with a logic level 0 on the select line. If a further described below and applies to both the master
waiting period is required, such as for analog-to-digital and the slave device.
conversion, the master must wait for at least that period
of time before issuing clock cycles.
At CPOL=0 the base value of the clock is zero,i.e.
the active state is 1 and idle state is 0.
During each SPI clock cycle, a full duplex data transmisA typical hardware setup using two shift registers to form an interchip circular buer

sion occurs. The master sends a bit on the MOSI line and
the slave reads it, while the slave sends a bit on the MISO
line and the master reads it. This sequence is maintained
even when only one-directional data transfer is intended.

For CPHA=0, data are captured on the clocks

rising edge (lowhigh transition) and data is
output on a falling edge (highlow clock transition).

Transmissions normally involve two shift registers of

For CPHA=1, data are captured on the clocks
some given word size, such as eight bits, one in the masfalling edge and data is output on a rising edge.
ter and one in the slave; they are connected in a virtual
ring topology. Data is usually shifted out with the most At CPOL=1 the base value of the clock is one (insignicant bit rst, while shifting a new least-signicant
version of CPOL=0), i.e. the active state is 0 and
bit into the same register. At the same time, Data from
idle state is 1.
the counterpart is shifted into the least-signicant bit reg For CPHA=0, data are captured on clocks
ister. After the register bits have been shifted out and in,
falling edge and data is output on a rising edge.
the master and slave have exchanged register values. If
more data needs to be exchanged, the shift registers are
For CPHA=1, data are captured on clocks risreloaded and the process repeats. Transmission may coning edge and data is output on a falling edge.
tinue for any number of clock cycles. When complete,
the master stops toggling the clock signal, and typically That is, CPHA=0 means sampling on the rst clock edge,
deselects the slave.
while CPHA=1 means sampling on the second clock
Transmissions often consist of 8-bit words. However, edge, regardless of whether that clock edge is rising or
other word sizes are also common, for example, 16-bit falling. Note that with CPHA=0, the data must be stable
words for touchscreen controllers or audio codecs, such for a half cycle before the rst clock cycle.

2.5

Daisy chain conguration

In other words, CPHA=0 means transmitting data on the together, they are required to be tri-state pins (high, low
active to idle state and CPHA=1 means that data is trans- or high-impedance).
mitted on the idle to active state edge. Note that if transmission happens on a particular edge, then capturing will
happen on the opposite edge(i.e. if transmission hap- 2.5 Daisy chain conguration
pens on falling, then reception happens on rising and vice
versa). The MOSI and MISO signals are usually stable
(at their reception points) for the half cycle until the next
SCLK
SCLK
SPI
SPI
MOSI
MOSI
clock transition. SPI master and slave devices may well
Master
Slave
MISO
MISO
sample data at dierent points in that half cycle.
SS
SS
This adds more exibility to the communication channel
between the master and slave.

2.3

Mode numbers

The combinations of polarity and phases are often referred to as modes which are commonly numbered according to the following convention, with CPOL as the
high order bit and CPHA as the low order bit:

SCLK
MOSI
MISO
SS

SPI
Slave

SCLK
MOSI
MISO
SS

SPI
Slave

For Microchip PIC / ARM-based microcontrollers

Daisy-chained SPI bus: master and cooperative slaves
(note that NCPHA is the inversion of CPHA):
For PIC32MX : SPI mode congure CKP,CKE and SMP Some products that implement SPI may be connected in
bits.Set SMP bit,and CKP,CKE two bits congured as a daisy chain conguration, the rst slave output being
above table.
connected to the second slave input, etc. The SPI port of
each slave is designed to send out during the second group
For other microcontrollers:
of clock pulses an exact copy of the data it received during
Another commonly used notation represents the mode as the rst group of clock pulses. The whole chain acts as a
a (CPOL, CPHA) tuple; e.g., the value '(0, 1)' would in- communication shift register; daisy chaining is often done
dicate CPOL=0 and CPHA=1.
with shift registers to provide a bank of inputs or outputs
through SPI. Such a feature only requires a single SS line
from the master, rather than a separate SS line for each
2.4 Independent slave conguration
slave.[4]

SPI
Master

SCLK
MOSI
MISO
SS1
SS2
SS3

Applications that require a daisy chain conguration include SGPIO and JTAG.

SCLK
MOSI
MISO
SS

SPI
Slave

SCLK
MOSI
MISO
SS

SPI
Slave

SCLK
MOSI
MISO
SS

SPI
Slave

2.6 Valid communications

Some slave devices are designed to ignore any SPI communications in which the number of clock pulses is
greater than specied. Others do not care, ignoring extra inputs and continuing to shift the same output bit. It
is common for dierent devices to use SPI communications with dierent lengths, as, for example, when SPI is
used to access the scan chain of a digital IC by issuing
a command word of one size (perhaps 32 bits) and then
getting a response of a dierent size (perhaps 153 bits,
one for each pin in that scan chain).

Typical SPI bus: master and three independent slaves

In the independent slave conguration, there is an independent chip select line for each slave. A pull-up resistor
between power source and chip select line is highly recommended for each independent device to reduce crosstalk between devices.[3] This is the way SPI is normally
used. Since the MISO pins of the slaves are connected

2.7 Interrupts
SPI devices sometimes use another signal line to send an
interrupt signal to a host CPU. Examples include pendown interrupts from touchscreen sensors, thermal limit
alerts from temperature sensors, alarms issued by real

time clock chips, SDIO,[5] and headset jack insertions

from the sound codec in a cell phone. Interrupts are not
covered by the SPI standard; their usage is neither forbidden nor specied by the standard.

2.8

Example of bit-banging the master

protocol

Below is an example of bit-banging the SPI protocol as

an SPI master with CPOL=0, CPHA=0, and eight bits
per transfer. The example is written in the C programming language. Because this is CPOL=0 the clock must
be pulled low before the chip select is activated. The chip
select line must be activated, which normally means being toggled low, for the peripheral before the start of the
transfer, and then deactivated afterwards. Most peripherals allow or require several transfers while the select line
is low; this routine might be called several times before
deselecting the chip.

PROS AND CONS

Typically lower power requirements than IC

or SMBus due to less circuitry (including pull
up resistors)
No arbitration or associated failure modes
Slaves use the masters clock, and do not need
precision oscillators
Slaves do not need a unique address unlike
IC or GPIB or SCSI
Transceivers are not needed
Uses only four pins on IC packages, and wires in
board layouts or connectors, much fewer than parallel interfaces
At most one unique bus signal per device (chip select); all others are shared
Signals are unidirectional allowing for easy Galvanic
isolation
Not limited to any maximum clock speed, enabling
potentially high speed

/* * Simultaneously transmit and receive a byte on the

SPI. * * Polarity and phase are assumed to be both
Simple software implementation
0, i.e.: * - input data is captured on rising edge of
SCLK. * - output data is propagated on falling edge
of SCLK. * * Returns the received byte. */ uint8_t 3.2 Disadvantages
SPI_transfer_byte(uint8_t byte_out) { uint8_t byte_in =
Requires more pins on IC packages than IC, even
0; uint8_t bit; for (bit = 0x80; bit; bit >>= 1) { /* Shiftin the three-wire variant
out a bit to the MOSI line */ write_MOSI((byte_out &
bit) ? HIGH : LOW); /* Delay for at least the peers
No in-band addressing; out-of-band chip select sigsetup time */ delay(SPI_SCLK_LOW_TIME); /* Pull
nals are required on shared buses
the clock line high */ write_SCLK(HIGH); /* Shift-in a
No hardware ow control by the slave (but the masbit from the MISO line */ if (read_MISO() == HIGH)
ter can delay the next clock edge to slow the transfer
byte_in |= bit; /* Delay for at least the peers hold
rate)
time */ delay(SPI_SCLK_HIGH_TIME); /* Pull the
clock line low */ write_SCLK(LOW); } return byte_in; }
No hardware slave acknowledgment (the master
could be transmitting to nowhere and not know it)

Pros and cons

3.1

Advantages

Full duplex communication in the default version of

this protocol.
Push-pull drivers (as opposed to open drain) provide
good signal integrity and high speed
Higher throughput than IC or SMBus
Complete protocol exibility for the bits transferred
Not limited to 8-bit words
Arbitrary choice of message size, content, and
purpose
Extremely simple hardware interfacing

Typically supports only one master device (depends

on devices hardware implementation)
No error-checking protocol is dened
Without a formal standard, validating conformance
is not possible
Only handles short distances compared to RS-232,
RS-485, or CAN-bus
Many existing variations, making it dicult to nd
development tools like host adapters that support
those variations
SPI does not support hot swapping (dynamically
adding nodes).
Interrupts must either be implemented with out-ofband signals or be faked by using periodic polling
similarly to USB 1.1 and 2.0
Some variants like Multi I/O SPI and three-wire serial buses dened below are half-duplex.

Applications

or changing the clocks duty cycles. Consequently, the

JTAG interface is not intended to support extremely high
[7]
The board real estate savings compared to a parallel I/O data rates.
bus are signicant, and have earned SPI a solid role in SGPIO is essentially another (incompatible) application
embedded systems. That is true for most system-on- stack for SPI designed for particular backplane managea-chip processors, both with higher end 32-bit proces- ment activities. SGPIO uses 3-bit messages.
sors such as those using ARM, MIPS, or PowerPC and
with other microcontrollers such as the AVR, PIC, and
MSP430. These chips usually include SPI controllers
capable of running in either master or slave mode. In- 5 Standards
system programmable AVR controllers (including blank
ones) can be programmed using an SPI interface.[6]
The SPI bus is a de facto standard. However, the lack of a
Chip or FPGA based designs sometimes use SPI to com- formal standard is reected in a wide variety of protocol
municate between internal components; on-chip real es- options. Dierent word sizes are common. Every device
denes its own protocol, including whether it supports
tate can be as costly as its on-board cousin.
commands at all. Some devices are transmit-only; others
The full-duplex capability makes SPI very simple and ef- are receive-only. Chip selects are sometimes active-high
cient for single master/single slave applications. Some rather than active-low. Some protocols send the least sigdevices use the full-duplex mode to implement an e- nicant bit rst.
cient, swift data stream for applications such as digital
audio, digital signal processing, or telecommunications Some devices even have minor variances from the
channels, but most o-the-shelf chips stick to half-duplex CPOL/CPHA modes described above. Sending data
from slave to master may use the opposite clock edge as
request/response protocols.
master to slave. Devices often require extra clock idle
SPI is used to talk to a variety of peripherals, such as
time before the rst clock or after the last one, or between a command and its response. Some devices have
Sensors: temperature, pressure, ADC, touch- two clocks, one to read data, and another to transmit it
screens, video game controllers
into the device. Many of the read clocks run from the
chip select line.
Control devices: audio codecs, digital potentiomeSome devices require an additional ow control signal
ters, DAC
from slave to master, indicating when data are ready. This
Camera lenses: Canon EF lens mount
leads to a 5-wire protocol instead of the usual 4. Such a
ready or enable signal is often active-low, and needs to
Communications: Ethernet, USB, USART, CAN, be enabled at key points such as after commands or beIEEE 802.15.4, IEEE 802.11, handheld video tween words. Without such a signal, data transfer rates
games
may need to be slowed down signicantly, or protocols
may need to have dummy bytes inserted, to accommodate
Memory: ash and EEPROM
the worst case for the slave response time. Examples include initiating an ADC conversion, addressing the right
Real-time clocks
page of ash memory, and processing enough of a com LCD, sometimes even for managing image data
mand that device rmware can load the rst word of the
response. (Many SPI masters do not support that signal
Any MMC or SD card (including SDIO variant[5] )
directly, and instead rely on xed delays.)
For high performance systems, FPGAs sometimes use
SPI to interface as a slave to a host, as a master to sensors, or for ash memory used to bootstrap if they are
SRAM-based.

Many SPI chips only support messages that are multiples

of 8 bits. Such chips can not interoperate with the JTAG
or SGPIO protocols, or any other protocol that requires
messages that are not multiples of 8 bits.

Although there are some similarities between the SPI bus

and the JTAG (IEEE 1149.1-2013) protocol, They are
not interchangeable. The SPI bus is intended for high
speed, on board initialization of device peripherals, while
the JTAG protocol is intended to provide reliable test access to the I/O pins from an o board controller with
less precise signal delay and skew parameters. While
not strictly a level sensitive interface, the JTAG protocol supports the recovery of both setup and hold violations between JTAG devices by reducing the clock rate

There are also hardware-level dierences. Some chips

combine MOSI and MISO into a single data line (SI/SO);
this is sometimes called 'three-wire' signaling (in contrast
to normal 'four-wire' SPI). Another variation of SPI removes the chip select line, managing protocol state machine entry/exit using other methods. Anyone needing
an external connector for SPI denes their own: UEXT,
JTAG connector, Secure Digital card socket, etc. Signal
levels depend entirely on the chips involved.
SafeSPI is an industry standard for SPI in automotive ap-

RELATED TERMS

plications. Its main focus is the transmission of sensor 6.4 Logic analyzers
data between dierent devices.
When developing and/or troubleshooting the SPI bus, examination of hardware signals can be very important.
Logic analyzers are tools which collect, analyze, decode,
6 Development tools
and store signals so people can view the high-speed waveforms at their leisure. Logic analyzers display timeWhen developing or troubleshooting systems using SPI, stamps of each signal level change, which can help nd
visibility at the level of hardware signals can be important. protocol problems. Most logic analyzers have the capability to decode bus signals into high-level protocol data
and show ASCII data.

6.1

Host adapters

There are a number of USB hardware solutions to provide

computers, running Linux, Mac, or Windows, SPI mas- 7
ter and/or slave capabilities. Many of them also provide
scripting and/or programming capabilities (Visual Basic, 7.1
C/C++, VHDL etc.).
An SPI host adapter lets the user play the role of a master
on an SPI bus directly from PC. They are used for embedded systems, chips (FPGA/ASIC/SoC) and peripheral testing, programming and debugging.

Related terms
Intelligent SPI controllers

A queued serial peripheral interface (QSPI) is a type

of SPI controller that uses a data queue to transfer data
across the SPI bus.[10] It has a wrap-around mode allowing continuous transfers to and from the queue with only
intermittent attention from the CPU. Consequently, the
peripherals appear to the CPU as memory-mapped parallel devices. This feature is useful in applications such as
control of an A/D converter. Other programmable features in QSPI are chip selects and transfer length/delay.

The key parameters of SPI adapters are: the maximum

supported frequency for the serial interface, commandto-command latency and the maximum length for SPI
commands. It is possible to nd SPI adapters on the market today that support up to 100 MHz serial interfaces,
with virtually unlimited access length.
SPI controllers from dierent vendors support dierent
SPI protocol being a de facto standard, some SPI host feature sets; such DMA queues are not uncommon, aladapters also have the ability of supporting other proto- though they may be associated with separate DMA enused by
cols beyond the traditional 4-wires SPI (for example, sup- gines rather than the SPI controller itself, such as[11]
multichannel
buered
serial
port
(MCBSP).
Most
port of quad-SPI protocol or other custom serial protocol
SPI
master
controllers
integrate
support
for
up
to
four
[8]
that derive from SPI ).
chip selects,[12] although some require chip selects to be
Examples of SPI adapters (manufacturers in alphabet- managed separately through GPIO lines.
ical order):

6.2

Protocol analyzers

7.2 Microwire

[13]
SPI protocol analyzers are tools which sample an SPI bus Microwire, often spelled Wire, is essentially a predeand decode the electrical signals to provide a higher-level cessor of SPI and a trademark of National Semiconductor. Its a strict subset of SPI: half-duplex, and using SPI
view of the data being transmitted on a specic bus.
mode 0. Microwire chips tend to need slower clock rates
Examples of SPI protocol analyzers (manufacturers in
than newer SPI versions; perhaps 2 MHz vs. 20 MHz.
alphabetical order):
Some Microwire chips also support a three-wire mode,
which ts neatly with the restriction to half-duplex.

6.3

Oscilloscopes

Every major oscilloscope vendor oers oscilloscopebased triggering and protocol decoding for SPI. Most support 2-, 3-, and 4-wire SPI. The triggering and decoding
capability is typically oered as an optional extra. SPI
signals can be accessed via analog oscilloscope channels
or with digital MSO channels.[9]

7.3 Microwire/Plus
Microwire/Plus[14] is an enhancement of Microwire and
features full-duplex communication and support for SPI
modes 0 and 1. There was no specied improvement in
serial clock speed.

7.7

7.4

Intel Enhanced Serial Peripheral Interface Bus

Three-wire serial buses

As mentioned, one variant of SPI uses single bidirectional

data line (slave out/slave in, called SISO) instead of two
unidirectional ones (MOSI and MISO). This variant is
restricted to a half duplex mode. It tends to be used for
lower performance parts, such as small EEPROMs used
only during system startup and certain sensors, and Microwire. Few SPI master controllers support this mode;
although it can often be easily bit-banged in software.

7.5

Multi I/O SPI

As opposed to three-wire serial buses, multi I/O SPI uses

multiple parallel data lines (e.g., IO0 to IO3) to increase
throughput. Dual I/O SPI using two data lines has comparable throughput to fast single I/O (MISO/MOSI). Quad
I/O SPI using four data lines has approximately double
the throughput.[15] Multi I/O SPI devices tend to be half
duplex similar to three-wire devices to avoid adding too
many pins. These serial memory devices combine the
advantage of more speed with reduced pin count as compared to parallel memory.

7.6

mSPI

7
the bus master to issue a slave address (typically 8 bits)
as mandatory rst word in every transmission. Since all
slave devices share the same SS line, the address word
will be received by all of them at the same time. From
that point further, only the device with the specied address will connect its MISO line to the bus and start communicating, while all other slave devices will ignore any
data and wait for a new start of transmission and address.
mSPI solves some of the basic disadvantages of the standard SPI at the expense of a slight decrease in the overall
communication speed due to the initial addressing.

7.7 Intel Enhanced Serial Peripheral Interface Bus

Intel has developed a successor to its Low Pin Count
(LPC) bus that it calls the Enhanced Serial Peripheral Interface Bus, or eSPI for short. Intel aims to allow the reduction in the number of pins required on motherboards
compared to systems using LPC, have more available
throughput than LPC, reduce the working voltage to 1.8
volts to facilitate smaller chip manufacturing processes,
allow eSPI peripherals to share SPI ash devices with the
host (the LPC bus did not allow rmware hubs to be used
by LPC peripherals), tunnel previous out-of-band pins
through the eSPI bus, and allow system designers to trade
o cost and performance.[16]
The eSPI bus can either be shared with SPI devices to
save pins or be separate from the SPI bus to allow more
performance, especially when eSPI devices need to use
SPI ash devices.[16]

Typical mSPI bus: master and three independent slaves

mSPI (mini-SPI) is a modication initially developed by

Dimitech for their programmable modules. Unlike the
standard SPI, four signal lines are always required no matter of the number of slave devices. Its overall simplicity
allows the use of standard SPI controllers with a very thin
software layer.
All slave devices share the same SS (Slave Select; active
low) line, along with the other three SPI signals: SCLK,
MOSI and MISO. Additionally all slave devices normally
have their MISO line disconnected from the bus in a high
impedance state. As in the standard SPI, begin of transmission is marked by the activation of the SS line low and
the end is marked by its return to high. mSPI requires

This proposed standard denes an Alert# signal that is

used by an eSPI slave to request service from the master. In a performance-oriented design or a design with
only one eSPI slave, each eSPI slave will have its Alert#
pin connected to an Alert# pin on the eSPI master that is
dedicated to each slave, allowing the eSPI master to grant
low-latency service because the eSPI master will know
which eSPI slave needs service and will not need to poll
all of the slaves to determine which device needs service.
In a budget design with more than one eSPI slave, all of
the Alert# pins of the slaves are connected to one Alert#
pin on the eSPI master in a wired-OR connection, which
will require the master to poll all the slaves to determine
which ones need service when the Alert# signal is pulled
low by one or more peripherals that need service. Only
after all of the devices are serviced will the Alert# signal be pulled high due to none of the eSPI slaves needing
service and therefore pulling the Alert# signal low.[16]
This proposed standard allows designers to use 1-bit, 2bit, or 4-bit communications at speeds from 20 to 66 MHz
to further allow designers to trade o performance and
cost.[16]
All communications that were out-of-band of the
LPC bus like general-purpose input/output (GPIO) and
System Management Bus (SMBus) are tunneled through

10

EXTERNAL LINKS

the eSPI bus via virtual wire cycles and out-of-band message cycles respectively in order to remove those pins
from motherboard designs using eSPI.[16]

[6] AVR910 - In-system programming

This proposed standard will support standard memory cycles with lengths of 1 byte to 4 kibibytes of data, short
memory cycles with lengths of 1, 2, or 4 bytes that have
much less overhead compared to standard memory cycles, and I/O cycles with lengths of 1, 2, or 4 bytes of
data which are low overhead as well. This signicantly
reduces overhead compared to the LPC bus, where all
cycles except for the 128-byte rmware hub read cycle
spends more than one half of all of the buss throughput
and time in overhead. The standard memory cycle allows
a length of anywhere from 1 byte to 4 kibibytes in order
to allow its larger overhead to be amortized over a large
transaction. eSPI slaves are allowed to initiate bus master versions of all of the memory cycles. Bus master I/O
cycles, which were introduced by the LPC bus specication, and ISA-style DMA including the 32-bit variant introduced by the LPC bus specication, are not present in
eSPI. Therefore, bus master memory cycles are the only
allowed DMA in this standard.[16]

[8] SPI Adapter with support of custom serial protocols, Byte

Paradigm.

[7] IEEE 1149.1-2013

[9] N5391B.
[10] Queued Serial Module Reference Manual, Freescale
Semiconductor
[11] Such as with the MultiChannel Serial Port Interface, or
McSPI, used in Texas Instruments OMAP chips.
[12] Such as the SPI controller on Atmel AT91 chips like the
at91sam9G20, which is much simpler than TIs McSPI.
[13] MICROWIRE Serial Interface National Semiconductor
Application Note AN-452
[14] MICROWIRE/PLUS Serial Interface for COP800 Family National Semiconductor Application Note AN-579
[15] Serial Peripheral Interface (SPI) Flash Memory Backgrounder, Spansion
[16] https://downloadcenter.intel.com/Detail_Desc.aspx?

eSPI slaves are allowed to use the eSPI master as a proxy

lang=eng&changeLang=true&DwnldID=22112
to perform ash operations on a standard SPI ash mem[17] Intel 100 Series Chipset Family PCH Datasheet, Vol.
ory slave on behalf of the requesting eSPI slave.[16]
64-bit memory addressing is also added, but is only permitted when there is no equivalent 32-bit address.[16]
The Intel Z170 chipset has implemented this bus as well
as a version of the LPC bus that is missing its ISA-style
DMA capability.[17]

See also

10 External links
Intel eSPI (Enhanced Serial Peripheral Interface)
Introduction to SPI and I2C protocols
Serial buses information page

List of network buses

SPI Introduction

UEXT Connector.

SPI Tutorial

Microsecond Bus.

1 (PDF). Retrieved April 15, 2015.

References

[1] What is Serial Synchronous Interface (SSI)?". Retrieved

2015-01-28.
[2] SPI Block Guide v3.06; Motorola/Freescale/NXP; 2003.
[3] Better SPI Bus Design in 3 Steps. dorkbot pdx. Retrieved 3 September 2015.
[4] Maxim-IC application note 3947: Daisy-Chaining SPI
Devices
[5] Not to be confused with the SDIO line of the half duplex
implementation of the SPI bus, sometimes also called 3wire SPI-bus. Here e.g. MOSI (via a resistor) and MISO
(no resistor) of a master is connected to the SDIO line of
a slave.

11
11.1

Text and image sources, contributors, and licenses

Text

Serial Peripheral Interface Bus Source: https://en.wikipedia.org/wiki/Serial_Peripheral_Interface_Bus?oldid=729292519 Contributors: Damian Yerrick, Ray Van De Walker, Heron, Cyp, William M. Connolley, Glenn, HPA, Colin Marquardt, Darkhorse, Blades,
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11.2

Images

File:350px-mSPI_three_slaves_svg.png Source:
License: CC-BY-SA-3.0 Contributors:
Own work
Original artist:
Knivd

https://upload.wikimedia.org/wikipedia/en/f/fc/350px-mSPI_three_slaves_svg.png

File:Commons-logo.svg Source: https://upload.wikimedia.org/wikipedia/en/4/4a/Commons-logo.svg License: CC-BY-SA-3.0 Contributors: ? Original artist: ?

File:Folder_Hexagonal_Icon.svg Source: https://upload.wikimedia.org/wikipedia/en/4/48/Folder_Hexagonal_Icon.svg License: Cc-bysa-3.0 Contributors: ? Original artist: ?
File:Nuvola_apps_ksim.png Source: https://upload.wikimedia.org/wikipedia/commons/8/8d/Nuvola_apps_ksim.png License: LGPL
Contributors: http://icon-king.com Original artist: David Vignoni / ICON KING
File:SPI_8-bit_circular_transfer.svg Source: https://upload.wikimedia.org/wikipedia/commons/b/bb/SPI_8-bit_circular_transfer.svg
License: CC-BY-SA-3.0 Contributors: This vector image was created with Inkscape. Original artist: en:User:Cburnett
File:SPI_single_slave.svg Source: https://upload.wikimedia.org/wikipedia/commons/e/ed/SPI_single_slave.svg License: CC-BY-SA3.0 Contributors: This vector image was created with Inkscape. Original artist: en:User:Cburnett
File:SPI_three_slaves.svg Source: https://upload.wikimedia.org/wikipedia/commons/f/fc/SPI_three_slaves.svg License: CC-BY-SA3.0 Contributors: This vector image was created with Inkscape. Original artist: en:User:Cburnett
File:SPI_three_slaves_daisy_chained.svg Source: https://upload.wikimedia.org/wikipedia/commons/9/97/SPI_three_slaves_daisy_
chained.svg License: CC-BY-SA-3.0 Contributors: This vector image was created with Inkscape. Original artist: en:User:Cburnett
File:SPI_timing_diagram2.svg Source:
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https://upload.wikimedia.org/wikipedia/commons/6/6b/SPI_timing_diagram2.svg License:

SPI_timing_diagram.svg Original artist: SPI_timing_diagram.svg: en:User:Cburnett

11.3

Content license

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