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CMOSinterviewquestions
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CMOSinterviewquestions.
1)Whatislatchup?
Latchuppertainstoafailuremechanismwhereinaparasitic
thyristor(suchasaparasiticsiliconcontrolledrectier,orSCR)
isinadvertentlycreatedwithinacircuit,causingahighamount
ofcurrenttocontinuouslyowthroughitonceitisaccidentally
triggeredorturnedon.Dependingonthecircuitsinvolved,the
amountofcurrentowproducedbythismechanismcanbe
largeenoughtoresultinpermanentdestructionofthedevice
duetoelectricaloverstress(EOS).
2)WhyisNANDgatepreferredoverNORgatefor
fabrication?
NANDisabeergatefordesignthanNORbecauseatthe
transistorlevelthemobilityofelectronsisnormallythreetimes
thatofholescomparedtoNORandthustheNANDisafaster
gate.
Additionally,thegateleakageinNANDstructuresismuch
lower.Ifyouconsidert_phlandt_plhdelaysyouwillndthat
itismoresymmetricincaseofNAND(thedelayprole),but
forNOR,onedelayismuchhigherthantheother(obviously
t_plhishighersincethehigherresistancepmossareinseries
connectionwhichagainincreasestheresistance).
3)WhatisNoiseMargin?Explaintheproceduretodetermine
NoiseMargin
Theminimumamountofnoisethatcanbeallowedontheinput
stageforwhichtheoutputwillnotbeeected.
4)Explainsizingoftheinverter?
Inordertodrivethedesiredloadcapacitancewehaveto
increasethesize(width)oftheinverterstogetanoptimized
performance.
5)HowdoyousizeNMOSandPMOStransistorstoincrease
thethresholdvoltage?
6)WhatisNoiseMargin?Explaintheproceduretodetermine
NoiseMargin?
Theminimumamountofnoisethatcanbeallowedontheinput
stageforwhichtheoutputwillnotbeeected.
7)Whathappenstodelayifyouincreaseloadcapacitance?
delayincreases.
8)Whathappenstodelayifweincludearesistanceatthe
outputofaCMOScircuit?
Increases.(RCdelay)
9)Whatarethelimitationsinincreasingthepowersupplyto
reducedelay?
Thedelaycanbereducedbyincreasingthepowersupplybutif
wedosotheheatingeectcomesbecauseofexcessivepower,
tocompensatethiswehavetoincreasethediesizewhichisnot
practical.
10)HowdoesResistanceofthemetallinesvarywith
increasingthicknessandincreasinglength?
R=(*l)/A.
11)ForCMOSlogic,givethevarioustechniquesyouknowto
minimizepowerconsumption?
Powerdissipation=CV2f,fromthisminimizetheload
capacitance,dcvoltageandtheoperatingfrequency.
12)WhatisChargeSharing?ExplaintheChargeSharing
problemwhilesamplingdatafromaBus?
IntheseriallyconnectedNMOSlogictheinputcapacitanceof
eachgatesharesthechargewiththeloadcapacitancebywhich
thelogicallevelsdrasticallymismatchedthanthatofthe
desiredonce.Toeliminatethisloadcapacitancemustbevery
highcomparedtotheinputcapacitanceofthegates
(approximately10times).
13)Whydowegraduallyincreasethesizeofinvertersin
buerdesign?Whynotgivetheoutputofacircuittoone
largeinverter?
Becauseitcannotdrivetheoutputloadstraightaway,sowe
graduallyincreasethesizetogetanoptimizedperformance.
14)WhatisLatchUp?ExplainLatchUpwithcrosssectionofa
CMOSInverter.HowdoyouavoidLatchUp?
Latchupisaconditioninwhichtheparasiticcomponentsgive
risetotheEstablishmentoflowresistanceconductingpath
betweenVDDandVSSwithDisastrousresults.
15)GivetheexpressionforCMOSswitchingpower
dissipation?
CV2
16)WhatisBodyEect?
IngeneralmultipleMOSdevicesaremadeonacommon
substrate.Asaresult,thesubstratevoltageofalldevicesis
normallyequal.Howeverwhileconnectingthedevicesserially
thismayresultinanincreaseinsourcetosubstratevoltageas
weproceedverticallyalongtheserieschain(Vsb1=0,Vsb2
0).WhichresultsVth2>Vth1.
17)WhyisthesubstrateinNMOSconnectedtoGroundand
inPMOStoVDD?
wetrytoreversebiasnotthechannelandthesubstratebutwe
trytomaintainthedrain,sourcejunctionsreversebiasedwith
respecttothesubstratesothatwedontlooseourcurrentinto
thesubstrate.
18)WhatisthefundamentaldierencebetweenaMOSFET
andBJT?
InMOSFET,currentowiseitherduetoelectrons(nchannel
MOS)orduetoholes(pchannelMOS)InBJT,weseecurrent
duetoboththecarriers..electronsandholes.BJTisacurrent
controlleddeviceandMOSFETisavoltagecontrolleddevice.
19)Whichtransistorhashighergain.BJTorMOSandwhy?
BJThashighergainbecauseithashighertransconductance.This
isbecausethecurrentinBJTisexponentiallydependenton
inputwhereasinMOSFETitissquarelaw.
20)Whydowegraduallyincreasethesizeofinvertersin
buerdesignwhentryingtodriveahighcapacitiveload?
Whynotgivetheoutputofacircuittoonelargeinverter?
Wecannotuseabiginvertertodrivealargeoutputcapacitance
because,whowilldrivethebiginverter?Thesignalthathasto
drivetheoutputcapwillnowseealargergatecapacitanceof
theBIGinverter.Sothisresultsinslowraiseorfalltimes.Aunit
invertercandriveapproximatelyaninverterthats4times
biggerinsize.Sosayweneedtodriveacapof64unitinverter
thenwetrytokeepthesizinglikesay1,4,16,64sothateach
inverterseesasameratioofoutputtoinputcap.Thisisthe
primereasonbehindgoingforprogressivesizing.
21)InCMOStechnology,indigitaldesign,whydowedesign
thesizeofpmostobehigherthanthenmos.Whatdetermines
thesizeofpmoswrtnmos.Thoughthisisasimplequestion
trytolistallthereasonspossible?
InPMOSthecarriersareholeswhosemobilityisless[aprrox
half]thantheelectrons,thecarriersinNMOS.Thatmeans
PMOSisslowerthananNMOS.InCMOStechnology,nmos
helpsinpullingdowntheoutputtogroundannPMOShelpsin
pullinguptheoutputtoVdd.IfthesizesofPMOSandNMOS
arethesame,thenPMOStakeslongtimetochargeupthe
outputnode.IfwehavealargerPMOSthantherewillbemore
carrierstochargethenodequicklyandovercometheslow
natureofPMOS.Basicallywedoallthistogetequalriseand
falltimesfortheoutputnode.
22)WhyPMOSandNMOSaresizedequallyina
TransmissionGates?
InTransmissionGate,PMOSandNMOSaideachotherrather
competingwitheachother.Thatsthereasonwhyweneednot
sizethemlikeinCMOS.InCMOSdesignwehaveNMOSand
PMOScompetingwhichisthereasonwetrytosizethem
proportionaltotheirmobility.
23)Allofusknowhowaninverterworks.Whathappens
whenthePMOSandNMOSareinterchangedwithone
anotherinaninverter?
IhaveseensimilarQsinsomeofthediscussions.Ifthesource
&drainalsoconnectedproperly...itactsasabuer.But
supposeinputislogic1O/Pwillbedegraded1Similarly
degraded0;
24)AgoodquestiononLayouts.Give5importantDesign
techniquesyouwouldfollowwhendoingaLayoutforDigital
Circuits?
a)Indigitaldesign,decidetheheightofstandardcellsyouwant
tolayout.Itdependsuponhowbigyourtransistorswill
be.HavereasonablewidthforVDDandGNDmetal
paths.MaintaininguniformHeightforallthecellisvery
importantsincethiswillhelpyouuseplaceroutetooleasily
andalsoincaseyouwanttodomanualconnectionofallthe
blocksitsavesonlotofarea.
b)Useonemetalinonedirectiononly,Thisdoesnotapplyfor
metal1.Sayyouareusingmetal2todohorizontalconnections,
thenusemetal3forverticalconnections,metal4forhorizontal,
metal5verticaletc...
c)Placeasmanysubstratecontactaspossibleintheempty
spacesofthelayout.
d)Donotusepolyoverlongdistancesasithashugeresistances
unlessyouhavenootherchoice.
e)Usengeredtransistorsasandwhenyoufeelnecessary.
f)Trymaintainingsymmetryinyourdesign.Trytogetthe
designinBITSlicedmanner.
25)Whatismetastability?When/whyitwilloccur?Dierent
waystoavoidthis?
Metastablestate:Aunknownstateinbetweenthetwological
knownstates.ThiswillhappeniftheO/Pcapisnotallowedto
charge/dischargefullytotherequiredlogicallevels.
Oneofthecasesis:Ifthereisasetuptimeviolation,
metastabilitywilloccur,Toavoidthis,aseriesofFFsisused
(normally2or3)whichwillremovetheintermediatestates.
26)LetAandBbetwoinputsoftheNANDgate.SaysignalA
arrivesattheNANDgatelaterthansignalB.Tooptimize
delayofthetwoseriesNMOSinputsAandBwhichone
wouldyouplaceneartotheoutput?
Thelatecomingsignalsaretobeplacedclosertotheoutput
nodeieAshouldgotothenmosthatisclosertotheoutput.
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