Receivers Architectures
Receiver architectures by S. Vlassis
General considerations
Limited spectrum allocated to each user.
30kHz in IS-54 and 200kHz in GSM, 1020MHZ to 802.11
Receiver
Process the desired signal
Reject the strong interferers
Transmitter
Narrow band modulation
Amplification
Filtering to avoid leakage to adjacent channels
Receiver architectures by S. Vlassis
General considerations
900MHz receiver
Channel 30kHz
Interferer rejection at 60kHz (away)
LC filter : 60dB attenuation 45kHz (away) needs Q=107
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very difficult
Receiver architectures by S. Vlassis
General considerations
Band: the entire spectrum according to standard
GSM: 935MHz to 960MHz)
Band selection: out-of-band interferers rejection
Channel: refers to the signal BW of only one user
GSM:200kHz
Channel selection: out-of-channel interferers rejection
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Receiver architectures by S. Vlassis
General considerations
Frond-end filters
Finite BW
Finite out of band rejection
Eg. 30dB rejection@20MHz (away)
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Receiver architectures by S. Vlassis
General considerations
Need for low lon-linearities of LNA+MIXER
Odd-order non-linearity yields intermodulation (IM) product in the channel
3rd order distortion (IP3) sufficient high to avoid signal corruption with IM product
Need for low loss of front-end BPF
3dB loss (attenuation) gives 370mW loss of power
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Receiver architectures by S. Vlassis
General considerations
Dynamic range (DR)of signals
Signal fading+path loss need DR>100dB
Minimum detectable signals <uV need low noise and cross talk
Cross talk requires high isolation
TX power amp: 1W@50 =20Vpp with -26dBm leakage gives 30mVpp which is
compared to LNA 1-dB compression point (-25dBm)
Receiver architectures by S. Vlassis
Heterodyne receiver
Problems
Image frequency
Half IF frequency
Dual IF Topology
Receiver architectures by S. Vlassis
Heterodyne receiver
Problem of image
There are users (power) in the image freq.
High power than the desired signal
Need for image rejection
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Receiver architectures by S. Vlassis
Heterodyne receiver
Image reject filter (before
mixer)
Small loss in the desired
band
Large attenuation in the
image band
Depends on 2IF
Image Filters: SAW or
crystal devices. eg. 10.7MHz
50 input impedance
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Receiver architectures by S. Vlassis
High power to drive 50
Heterodyne receiver
High IF
Substantial rejection of
image
Lower Q(=1/IF) of
the channel select filter
Low IF
Low efficient image
rejection
Higher Q of the channel
select filter
Dont forget the image
reject filter loss
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Receiver architectures by S. Vlassis
Heterodyne receiver
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Receiver architectures by S. Vlassis
Dual IF Architecture
Heterodyne receiver
Partial channel selection
Progressively lower center frequencies
Filters Q relaxation
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Receiver architectures by S. Vlassis
Heterodyne receiver
The second downconversion offers both
In-phase (I) component
Quadrature in phase (Q) component
The signal spectrum translated to zero frequency
Next: Automatic control loop, A/D
Each Mixer generates many spurious components related to RF, IF signal and
LO
Need for frequency planning
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Receiver architectures by S. Vlassis
Homodyne Receivers
FLO=FRF
Need for a LP filter
FM/PM need
quadrature
demodulation
Advantages
Problem of image is
circumvented
No RF SAW image filters
LNA need not drive 50
IF SAW filter + IF mixer
replaced with
low pass filters
Baseband amplifiers
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Receiver architectures by S. Vlassis
Homodyne Receivers:
Channel Selection
Active filters: noise-linearity-power
trade offs compared with the passive
counterparts
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Receiver architectures by S. Vlassis
(a) LPF before Amp
LPF: suppress out-of-channel
interferers
Amp1 linearity relaxed
Amp1 with high gain
ADC (4 8 bits)
(b) Amp before LPF
LPF: noise specs relaxed
Amp1: higher performance
Need for extra Amp
(c) Digital filtering
ADC high linearity
ADC noise < 2mV
Homodyne Receivers:
DC offsets
Isolation between port is
not infinite
LO leakage Self mixing
DC offset
Time varying offset
1.
2.
3.
4.
5.
6.
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Gain(AX) ~ 80dB-100dB
GainLNA+Mixer ~ 30dB(40) and GainLPF+Amp ~ 50dB(315)
VLOpp=0.63V(~0dBm@50) appears with 60dB attenuation at port A
VLOpp@ portA=VLOpp/1000=0.63uV,
VLOpp@mixer_out=0.63mV*40=25mV (RF signal ~30uVrms)
VLOpp@mixer_out*GainLPF+Amp =25mV *315~8V RX chain saturated
Receiver architectures by S. Vlassis
Homodyne Receivers:
offset cancellation
HP filtering
Substantial energy near dc very
low corner frequency -- large
capacitors
Fails to track fast offset variations
Offset cancellation Techniques
1. Baseband signal encoded
little energy near dc (dc free coding)
2.
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Idle time interval (depends on standard)
Receiver architectures by S. Vlassis
Homodyne Receivers:
Quadrature generation
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Receiver architectures by S. Vlassis
Homodyne Receivers:
IQ mismatch
Amplitude mismatch
Phase mismatch
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Receiver architectures by S. Vlassis
Homodyne Receivers:
IQ mismatch
1. Amp mismatch <1dB
2. Phase mismatch <5o
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Receiver architectures by S. Vlassis
Homodyne vs Heterodyne Receivers:
IQ mismatch
Heterodyne RX:
Lower IF frequency less sensitive to mismatches
Lower frequency larger devices less mismatches
The signal is enough amplified before IQ separation less stages
afterwards
Homodyne RX:
Incorporates several stages (LPF+Amps) after IQ separation
more sensitive to mismatches
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Receiver architectures by S. Vlassis
RF section of a cellphone
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Receiver architectures by S. Vlassis
