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Testing Int 1 Aug

This document is an internal test for a VLSI circuits testing course. It contains 3 parts: Part A contains 10 short answer questions testing concepts like fault modeling, propagation cubes, test generation methods. Part B contains 5 long answer questions, asking students to explain delay models, find tests for single and multiple faults, determine output functions for faults, discuss fault simulation techniques. Part C contains 1 long answer question asking to explain the PODEM test generation algorithm in detail.

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RamJiDR
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286 views2 pages

Testing Int 1 Aug

This document is an internal test for a VLSI circuits testing course. It contains 3 parts: Part A contains 10 short answer questions testing concepts like fault modeling, propagation cubes, test generation methods. Part B contains 5 long answer questions, asking students to explain delay models, find tests for single and multiple faults, determine output functions for faults, discuss fault simulation techniques. Part C contains 1 long answer question asking to explain the PODEM test generation algorithm in detail.

Uploaded by

RamJiDR
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
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NARAYANAGURU COLLEGE OF ENGINEERING

Department of Electronics and Communication Engineering


INTERNAL TEST 1
VL7301 Testing of VLSI Circuits
S3 ME VLSI DESIGN
Time : 3 Hours Maximum : 100 Marks
ANSWER ALL QUESTIONS
PART-A (10x2= 20 Marks)
1. State the need for testing.
2. Define Fault dominance.
3. Define Stuck-at-fault
4. How are faults modelled at Gate levels in Digital Circuits?
5. State the Lemma rule.
6. Construct propagation D-cubes for two-input NOR gate.
7. Define D frontier
8. Mention any four methods used in test generation for combinational circuits?
9. Define homing and distinguishing tree.
10. Define Controllability and Observability.

PART-B (13x5 = 65 Marks)


11. a). Explain in detail about Delay model. (13)

(or)
b). For the circuit given below (13)
a. Find the set of all tests that detect the fault a s-a-0.
b. Find the set of all tests that detect the fault b s-a-0.
c. Find the set of all tests that detect the multiple fault (a s-a-0, b s-a-0).

12 a). Determine the output function of the circuit given below for the (13)
following faults:
a. AND bridging between inputs of gate G1.
b. The multiple faults {x3 s-a-1, x2 s-a-0}.
(or)
b). Discuss on Gate level Event driven simulation (13)

13 a). Discuss on the various types of fault simulation techniques used in digital (13)
circuits.
(or)
b). Write short notes on (13)
a. Reed-Muller Expansion technique
b. Syndrome-testable design

14 a). Explain D algorithm with a suitable example. (13)


(or)
b). Describe on Scan-path technique for testable sequential circuit design. (13)

15 a). Explain in detail about the following methods to generate test pattern of (13)
combinational circuits.
a. One-Dimensional path sensitization
b. Boolean Difference
(or)
b). Explain how sequential circuits are tested using time frame expansion (13)
method.

PART-C (15x1 = 15 Marks)


16 Explain in detail about PODEM algorithm. (15)

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