ARM Roadmap

Spring 2017

Robert Boys
bob.boys@arm.com

Version 9.0
 Agenda
 Roadmap
 Architectures ARM1™ die
 Issues
 What is NEW !
 big.LITTLE™
 64 Bit
 Cortex®-A15
 64 BIT
 DynamIQ

3 © ARM 2017
 In the Beginning…
 1985 32 years ago in a barn....
 12 engineers
 Cash from Apple and VLSI
 IP from Acorn Computers
 Proof of concept
 No patents, no independent
customers, product not ready
for mass market.
 A barn, some energy, experience and belief:
“We’re going to be the Global Standard”
4 © ARM 2017
 The Cortex Processor Roadmap in 2008
Application
Real-time
Microcontroller Cortex-A9
Cortex-A8
ARM11

Cortex-R4F
ARM9
Cortex-R4

ARM7TDMI Cortex-M3 SC300

ARM7
Cortex-M1

5 © ARM 2017
5
 Cortex-A73
ARM 2017 Processor Roadmap Cortex-A35
Cortex-A72
Cortex-A32
Not to scale

ARM 7, 9, 11 Cortex-A17 Cortex-A57

Application Cortex-A53
Cortex-A15
Real-time Cortex-A9 (Dual)
Microcontroller Cortex-A9 (MPCore)
Cortex-A8 Cortex-A7
ARM11(MP) Cortex-A5
ARM926EJ-S MMU Cortex-R52
No MMU Cortex-R8
200+ MHz Cortex-R7
ARM9 Cortex-R5
Cortex-R4 Cortex-M7
200+ MHz Cortex-M33
ARM7TDM 72 – 150 + MHz Cortex-M4
I Cortex-M3 SC300 Cortex-M23
ARM7
Cortex-M1 DesignStart™ Cortex-M0+
SC000
Cortex-M0
6 © ARM 2017
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 Versions, cores and architectures ?
Family Architecture Cores
ARM7TDMI ARMv4T ARM7TDMI(S)

ARM9 ARM9E ARMv5TE ARM926EJ-S, ARM966E-S

ARM11 ARMv6 (T2) ARM1136(F), 1156T2(F)-S, 1176JZ(F), ARM11 MPCore™

Cortex-A ARMv7-A Cortex-A5, A7, A8, A9, A12, A15, A17

Cortex-R ARMv7-R Cortex-R4(F), Cortex-R5, R7, R8 …
Cortex-M ARMv7-M Cortex-M3, M4, M7 (M7 is ARMv7-ME)

ARMv6-M Cortex-M1, M0, M0+

NEW ! ARMv8-A 64 Bit: Cortex-A35/A53/57/A72 Cortex-A73

Cortex-A32
NEW ! ARMv8-R 32 Bit: Cortex-R52
NEW ! ARMv8-M 32 Bit: Cortex-M23 & M33 TrustZone®
7 © ARM 2017
 What is New ? DynamIQ !
 AI (Artificial Intelligence), Machine Learning, autonomous vehicles
 For multi-core Cortex-A processors.
 Up to 8 cores on a single cluster. Can be different processors.
 Such as 1+3, 1+7 – different configurations possible.
 Makes big.LITTLE better. 2011. Is the next evolutionary step.
 New memory subsystems.
 ASIL D certification possible for the 1st time.
 This is the future for ARM multi-core Cortex-A…
 Search for ARM DynamIQ for more information.
 One more thing…..
8 © ARM 2017
 Processor Licenses (list is no longer complete)
 ARMv8-A: 27 ! AMD, Broadcom, Huawei (HiSilicon), STMicroelectronics, Samsung, MediaTek, Huawei, Altera(Intel), Qualcomm
and Rockchip, NXP, Xilinx…
 Cortex-A15: Broadcom, HiSilicon, Texas Instruments, Samsung, nVIDIA
 Cortex-A9: Xilinx, Altera, NEC, nVIDIA, STMicroelectronics, Toshiba, Broadcom Corporation, NXP, NEC, Texas Instruments,
Toshiba, Mindspeed Technologies, ZiLABS, Open-Silicon, eSilicon
 Cortex-A8: Broadcom Corporation, NXP, Panasonic, Samsung, STMicroelectronics, Texas Instruments, PMC-Sierra, Matsushita
 Cortex-A7: Broadcom, NXP, Fujitsu, HiSilicon, LGE, Samsung, STEricsson, Texas Instruments
 Cortex-A5: AMD, Atmel, NXP, Cambridge Silicon Radio, Open-Silicon, eSilicon
 Cortex-R: Broadcom, Texas Instruments, Toshiba, Infineon, Open-Silicon, eSilicon, Samsung, Marvell, LSI, Fujitsu, Cypress (Spansion)
 NEW ! Cortex-M7: NXP, Atmel, ST.
 Cortex-M4: NXP, Atmel, ST, Texas Instruments, Open-Silicon, eSilicon, Spansion, Ambiq
 Cortex-M3: Microsemi (Actel), Broadcom, Energy Micro, NXP, ST, TI, Toshiba, Zilog, Accent Srl, Broadcom Corporation, Cypress
Semiconductor, Ember, Fuzhou Rockchip Electronics CO. Ltd., Open-Silicon, eSilicon, Spansion (Fujitsu)
 Cortex-M0: Austriamicrosystems, Chungbuk Technopark, NXP, Triad Semiconductor, Melfas, Open-Silicon, eSilicon, Cypress,
Infineon, Nuvoton, STMicroelectronics
 Cortex-M0+: NXP, Atmel, Cypress (Spansion), Silicon Labs
Total: Cortex-A 178, Cortex-R 45, Cortex-M 240, ARM7 172, ARM9 271, ARM11 82

9 © ARM 2017
 Feature Set of Various ARM Processors

 ARM 9 ARM 11 Cortex-M,R,A 64 Bit

10 © ARM 2017
 Instruction Sets
 ARM (32 bit) now referred as AArch32
 Thumb® (16 bit)
 Thumb2: Cortex-Mx processors. Cortex-R, A have Thumb2 + ARM.
 A64 (64 bit) referred as AArch64

ARM now called AArch32

Thumb (actually includes all ARM 32 bit instructions)

Thumb-2

A64 AArch64

11 © ARM 2017
13 © ARM 2017
 Cortex-M Adds:
 Simpler register set. Main
 More interrupts and exceptions. NVIC r0
r1
 More breakpoints (to 6) r2
r3
 4 Watchpoints. r4

 SYSTICK timer for RTOSs. r5

r6
 Fixed address space. r7
r8
 Bit manipulation. r9

 Upgrade and downgrade paths. r10

r11

Cortex-M3
r12
Process
Memory Map sp
sp
lr
r15 (pc)

xPSR

14 © ARM 2017
 Cortex-M3 Exceptions
 Exception handling order is defined by programmable priority
 Reset, Non Maskable Interrupt (NMI) and Hard Fault have predefined pre-emption.
 NVIC catches exceptions and pre-empts current task based on priority
 Program Counter set to exception address in vector table which directs to handler code
Exception Name Priority Descriptions
Fault Mode
& Start-up

1 Reset -3 (Highest) Reset

Handlers

2 NMI -2 Non-Maskable Interrupt

3 Hard Fault -1 Default fault if other hander not implemented

4 MemManage Fault Programmable MPU violation or access to illegal locations

5 Bus Fault Programmable Fault if AHB interface receives error

11 SVCall Programmable System SerVice call
Handlers
System

6 Usage Fault Programmable Exceptions due to program errors

12 Debug Monitor Programmable Break points, watch points, external debug

14 PendSV Programmable Pendable SerVice request for System Device

… … … …
Handlers
Custom

16 Interrupt #0 Programmable External Interrupt #0

…
15
…Systick
…
Programmable
…
System Tick Timer
… … … …
255 Interrupt #239 Programmable External Interrupt #239
15 © ARM 2017
 SIMD – Single Instruction Multiple Data
 SIMD is a set of instructions that can operate on multiple data sets
contained in a register.
 Registers used are the 32 bit general purpose R in ARM.
 Some of the SIMD instructions start with a “S” (signed) or a “U” (unsigned) and
with a suffix denoting the size of the operand (I16). An example is UADDI16.
 Here is the SADD16 instruction:
Two sets of 16 bit operands are
taken from 32 bit registers R3 and
R0 and are added together (signed)
and the 16 bit result stored in the
32 bit register R1:

16 © ARM 2017
 NEON™:

17 © ARM 2017
 NEON:

18 © ARM 2017
 NEON: is also called Advanced SIMD:
 NEON is both a) another set of more instructions that
operate on b) 32 special 64 bit registers.
 NEON works on a 128-bit data path. So on the Cortex-A9, it normally
uses two of the 64-bit NEON registers for each of the operands and
puts the result back in one or two of them.
 NEON share many instructions with a FPU…and each have their own
instructions.
 NEON instructions begin with a “V”.
 VADD,VABS,VCGE,VCGT,VEOR,VQADD…
 See ARM appnote DHT0002A “Introducing Neon”.
 Cortex-A8, A9, A15, A64, some ARM11 devices.
19 © ARM 2017
 How to program SIMD and NEON:
 Programs are written using assembly language.
 You can also use Intrinsics.
 The compiler can also use automatic vectorization on C or C++
code. (you have to tell the compiler it can do this)
 NEON libraries: This is a good way to do this to avoid writing in
assembly. OpenMax and Ne10 are two. The executable code will use
SIMD and NEON whenever possible.
 See DHT0004A for more information.
 At this time, all ARM Cortex-A series processors have NEON.
 SIMD and NEON used in Video encode/decode, 2D/3D graphics, audio
processing…
20
 Cortex-A8, A9, A15, A64, some ARM11 devices.
© ARM 2017
 big.LITTLE™
 Two or more processers – share workload
 Processors not always the same.
 Especially helpful for power savings.
 Cortex-A15 and Cortex-A7 are the original.
 Freescale: A5 + M4
 NXP LPC4300 M4 + M0
 Samsung announced a 8 ARM core 5 Octa Processor
 Plenty of others now and more coming.

21 © ARM 2017
 ARM 64 Bit Architecture
 The latest from ARM….
 Instructions 32 bits.
 31 64 bit registers + PC + SP
 Two execution states: AArch32 and AArch64
 48 bit addresses to outside world on first chips.
 Microsoft: Windows 8 and RT will work on ARM
 NVIDIA demonstrated Windows 8 on Tegra 3 at CES.
 www.arm.com/files/downloads/ARMv8_Architecture.pdf
 http://www.linaro.org/engineering/armv8

22 © ARM 2017
CoreSight Debug & Trace
 CoreSight debug technology delivers
enhanced debugging modes and features
 Serial Wire Debug (SWD) Mode
 2 wire interface instead of 4 or 5. Most have JTAG too.
 Serial Wire Viewer (SWV)
 Data R/W, Exceptions, PC Samples
 Enhanced Trace Macrocell (ETM)
 Adds all the program counters.
 Provides Code Coverage, Timings,
Performance Analysis, crash reports.
 Program Trace Macrocell (PTM)
 Cortex-A9, A15. All program counters.
 Embedded Trace Buffer: small 4 – 8K trace buffer.
23 © ARM 2017
 Operating Systems
 Linux
 Windows, WinCE
 Android
 Micrium, ExpressLogic, Quadros, QNX and so on.
 Big differentiator between processors is the MMU.
 Linaro – an open source community supported by ARM.
 Keil RTX has BSD or Apache 2.0 license now – means this is free.
 CMSIS-Core – header files and startup files
 CMSIS-DSP – DSP libraries
 CMSIS-RTOS – for the RTOS market.
 CMSIS-Packs – distribution of processor files and examples.
24 © ARM 2017
World’s No. 1 Embedded Ecosystem

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Copyright © 2017 ARM Limited