PROGRAMMABLE LOGIC

[Lecture Notes for BEE-III, Electrical Engineering Department, Jadavpur University, Kolkata. Prepared
by Biswajit Bhattacharyya.]
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Programmable Logic Devices

Hardware in the form of semiconductor based Integrated Chips, used nowadays, are of
two kinds – one as fixed function ICs, and other as programmable ICs. The second one in
its early form is called as Programmable Logic Devices (PLDs).

#. Fixed Function ICs:

Each of the ICs of this group has some specific functions and can be used for specific
objectives. ICs for timers and counters may be used as a part of sequential circuit; ICs for
arithmetic operations (e.g., full adder) may be used as a part of combinational circuit.
Designer can select from available ICs for design and development purpose.
Some examples of fixed function ICs are mentioned below:
 ICs for Timers & Counters
 ICs for Arithmetic operations
 ICs for Logical operations
 ICs for Control operations
 ICs as Memory
 ICs for Customized functions

◙ Advantages of using fixed function ICs:

1. Low development cost up to some level of complexity
2. Fast turn around of designs
3. Relatively easy to test the circuits.

◙ Disadvantages of using fixed function ICs:

1. Large board space requirements
2. Large power requirements
3. Compatibility of various ICs need to be checked before connections
4. Lack of security: circuit may be copied by unauthorized persons
5. Modifying design incurs more cost, space, power, i.e., lack of flexibility for
upgrading

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#. Application Specific Integrated Circuits (ASICs):

To overcome the problem of fixed function ICs, ASICs were developed.

● Features:
1. ASICs are designed by users to meet specific requirements.
2. These are produced by IC-manufacturer from foundry level as per the
specifications supplied by user.
3. Designs are too complex to be implemented using fixed function ICs.

◙ Advantages:
1. Reduced space requirement
2. Reduced power requirement
3. Per unit cost is quite low for large scale production
4. Almost copy-protect implementation

◙ Disadvantages:
1. Initial development cost may be enormous
2. Testing method may have to be developed that adds to the cost and effort
3. Quite costly for small volume of production
4. Existing design may be upgraded, but during implementation, the entire process
starts from foundry shop. Hence, up gradation may not be cost-effective.

#. Programmable Logic Devices (PLDs):

● Features:

1. These are the ICs of ‘regular structure’ over its dimensions and allow the designer
to customize it for any specific application, i.e., the function of the IC is user
programmable.
2. ‘Regular structure’ or ‘general structure’ contained within a PLD may vary
widely although the ultimate logic function offered by combination of these
structures as a result of a particular program is same.
3. Earlier versions of PLDs were One-Time-Programmable (OTP). Later,
ReProgrammable (RP) PLDs were developed.

◙ Advantages:

1. Short design cycles

2. Low development costs
3. Reduction in board space requirements
4. Reduction in power requirements
5. Design security
6. Compact Circuitry
7. Higher switching speed
8. Easy realization of circuit from a design as foundry-level production is avoided
9. PLDs can be reprogrammed, thereby offering more flexibilities to designers

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● Basic structure of a PLD:

Functional block:

Fig-1

An example of the circuit realization of the block is shown below:

Fig:-2

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Each of the diodes in the figure is connected in series to a voltage-controlled switch. If

the control input of the switch carries appropriate bit, the switch will be closed
(connected), else open.
Closing a Dij switch connects corresponding row and column, thus generating a 1 at the
output.
The bit 1 or 0 at the control input is supplied through program. It is to be noted that these
control inputs are internal part of the chip, and are not taken outside as external pins. But,
statuses of these inputs are obviously dependent on program bits that enter deep into the
chip from program console, through cables and external pins.

If the switches D00, D03, D12, D13, D21 and D33 are programmed as closed, then:

column

Fig:-3

The corresponding bit pattern will be as per the following table:

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Dij j i Bit Input bit Min terms

pattern
A3 A2 A1 A0
A3 A2 A1 A0 stored

Dij 0 0 0 0 1 0000 m0
Dij 1 1 0 0 1 1100 m12
Dij 1 0 0 1 1 1001 m9
Dij 1 1 0 1 1 1101 m13
Dij 0 1 1 0 1 0110 m6
Dij 1 1 1 1 1 1111 m15

Fig:-4: Truth table for which o/p is 1

For all other combination of A3, A2, A1, A0, output will be zero. Thus, the logic function
for output will be:

Y = ∑m(0,6,9,12,13,15)
Y  A0 A1 A2 A3  A0A1 A2 A3  A0 A1 A2A3  A0 A1A2 A3  A0 A1A2 A3  A0 A1 A2 A3

Evidently, the logic function is implemented in Sum Of Product (SOP) form.

Here, no. of output, N = 1.
It is clear that using 4 inputs (A3 A2 A1 A0), maximum number of minterms that can be
generated is 16, although all of the minterms do not give rise to 1 as output.
In general, a P-input ROM can deliver 2p minterms. With N outputs, size of the ROM,
then, will be 2p x N.
To get N (> 1) output, such N circuits with different logic functions can be connected in
parallel.

. ◘ Programmable Switches:

Along with the basic structures, programmable switches are an integral part of PLDs, and
of all later versions of programmable hardware.
For PLDs programmable switches may be of the following form:

1. Fusible link (or fuse)

2. Switches generated out of AIM process
3. SRAM cell (Static Memory Cell)

These are illustrated in brief.

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1. Fusible link (or fuse):

Physically, each of the switches will be a fuse that can be blown off by applying a high
current through the switch. Fuse materials may be:

a) Nichrome
b) Polycrystalline silicon

It is to be noted that a memory with fuses is One-Time Programmable (OTP).

2. Switches generated out of AIM process:

The process AIM is the Avalanche Induced Migration process. The switch may be
implemented through diodes in avalanche breakdown, or through bipolar transistors.

a) Using diodes in avalanche breakdown:

c
row o
l
u
m
n
Fig:-5
A high current (200mA – 300mA) and high voltage in reverse-biased diode
causes an avalanche breakdown of the diode, thereby permanently shorting
(connecting) the ‘row’ and ‘column’ terminals. Corresponding memories
containing these switches are of OTP technology.

b) Using bipolar transistors

c
row o
Vcc l
u
m
n
programmable
link (fuse)
Fig:-6
From the figure, it is evident that as long as fuse-link is kept intact, row
remains connected to column.

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These mechanisms, however, do not work with MOS memory devices, where
resistance and current levels required for the fusing process are incompatible
with MOS impedance levels.

The basic MOS switch is:

Fig:-7

Commonly used MOS technologies for the fabrication of programmable memories are:
a) FAMOS
b) MAOS

● FAMOS technology (Floating gate Avalanche Injection MOS):

A programmable memory-device implemented through FAMOS technology is shown

below:

Fig:-8

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Device programming:

Fig:-9

i) Apply negative voltage to both the source (VSX) and the drain (VDX), for
inducing avalanche breakdown at both junctions.
ii) Simultaneously, apply a positive voltage to second gate G2 (VG2S).

The step (i) causes electrons to be injected into floating gate, while the step (ii)
accelerates the accumulation of charge at the gate. As electrons accumulate on the
floating gate, the channel appears between the source, and the device turns on.

When the applied voltage is removed, the charge remains trapped in the gate, since no
discharge path is available for the accumulated electrons because the gate is surrounded
by a very low-conductivity dielectric. The transistor now behaves as if an external
voltage were permanently connected to the gate terminal.

For the purpose of erasing, i.e., removing charge from gate, procedures will be:

i) Same as step (i) applied for device programming.

ii) A negative voltage is applied to the gate G2.

This results in the accumulation of holes on the floating gate, which neutralizes existing
charge. Thus, erasing is carried out electrically.

These devices are referred to as Electrically Erasable and Programmable ROMs

(EEPROMs or E2PROMs), and are reprogrammable. Sometimes these memories are also
referred to as Non-Volatile RAM (NOVRAM) or flash-memory.

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Instead of erasing electrically, the charge accumulated on the gate can be removed by
illuminating the FAMOS device with ultraviolet light. This results in the flow of a photo
current from the floating gate back to the silicon substrate, thereby discharging the gate.
These devices are called Erasable Programmable Read-Only Memory (EPROM) devices.
Here, erase gate does not exist.

These devices are packaged with a transparent quartz lid for exposing the device to UV
radiation, for the purpose of erasing. In case the device is packaged in inexpensive
package without quartz lid, it works as an OTP ROM which is same as a PROM.

● MAOS technology (Metal Alumina Oxide Silicon):

Another type of PROM uses the gate dielectric, such as alumina (Al2O3) and silicon
nitride itself, for charge storage and provides a reprogramming feature. This device is
known as MAOS memory element.

Fig:-10

For a p-channel device, a positive gate voltage of about 50V amplitude is required for 10
– 20 μs, for programming. Erase requires a voltage of opposite polarity on the gate.

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4. SRAM Cell (Static Cell):

It is used as another programmable switch, but mostly used in later versions of PLDs.

Fig:-11: Static MOS RAM Cell

______
When Ax = 1, the cell is connected to Data and Data line.
When Ay = 1, T7 and T8 are on.
Asserting W = 1 will make T9 on.

To write in to cell: Set W = 1, Ay = 1, Ax = 1.

At this, the input data bit will propagate through T9, T7 and T5, and will remain stored
within the flip-flop.

To read from cell: Set Ax = 1, Ay = 1, R = 1.

At this the bit already stored within flip-flop will move through T6, T8 and T10, and the
______
data will be available at Data output. This output, if required, can be inverted at
subsequent stage. Hence, in block level a SRAM cell can be shown as:

Din Dout
SRAM Cell

Ax Ay

Fig:-12

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This cell stores single bit per cell, and the bit can be used as an input to a programmable
switch for closing / opening the same. Pictorially,

row

Pass gate

l
el
C
AM column
SR

Fig:-13

When zero is stored in cell, pass transistor provides high resistance between two wire
segments.

For SRAM cells used in multiplexers (MUX), combination of bit values in cell selects the
particular input line which gets connected to the output. This is shown in figure below:

Cell 0
MUX
Cell 1

Fig:-14

◙ Advantage of using SRAM:

It provides fast re-programmability.

◙ Disadvantage of using SRAM:

1. At least five transistors are required to implement a memory cell. Hence, space
consumption is more for a given memory capacity.
2. SRAM cell is prone to radiation hazard, and hence is not suitable for space
application.

The ‘general structure’ of a PLD may consist of:

1. ROM
2. PROM / EPROM / EEPROM
3. Programmable Logic Array (PLA)
4. Programmable Array Logic (PAL)
They are, in general, called as simple PLDs (SPLDs).

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■1. ROM as a PLD: It is a combinational circuit as shown below:

P no. of ROM: N no. of

Address MxN Data
Input Output
Fig:-15

Evidently, there can be 2p bit combinations at the input. Each combination is called an
address. Thus, 2p distinct addresses are possible at input for each of which data of N bit
length are available at the output side. Therefore, effectively there are 2p memory
locations as maximum and each of the location can store a data of N-bit length. In
general, all the memory locations may not be present in a given ROM structure. Thus, the
size of ROM may be specified as M x N, where M ≤ 2p.

■2. PROM / EPROM / EEPROM as a PLD:

A programmable memory can be realized through programmable switches. By sending
appropriate voltage / current signal, these switches are made open or closed. Hence, these
memories are Reprogrammable (RP).

■3. Programmable Logic Array (PLA) as PLD:

PLA consists of two-level AND-OR circuits on a single-chip. The AND gates provide the
product terms and the OR gates logically sum these product terms, thereby giving rise to
a Sum Of Product (SOP) expression.

The number of AND and OR gates, and their inputs are fixed for a given PLA chip. The
block diagram of a PLA structure is shown below:

Fig:-16: Block diagram of a PLA device

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In the diagram as shown above, there are M inputs. Hence, 2M minterms are available as
maximum. But, for a practical PLA, number of available minterms is generally less than
2M, say ‘n’. Each of the logic functions can have n minterms maximum, and such N
number of logic functions generate a total of N outputs. Thus, the PLA becomes a M-
input, N-output programmable hardware.

Since all of the possible 2M minterms are not available, logic minimization may be
applied to construct a given logic function.

● Input Buffer:

Fig: a) Fig: b)
Fig:-17

Buffers are required to avoid loading of the input sources. It draws low current and
delivers relatively high current. Fig b) is the symbol of inverters shown in Fig a), where
two complementary outputs are generated against a single input. Such M complementary
pair of signals are generated using M number of blocks.

● AND Matrix:

Fig:-18: AND matrix

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In an un-programmed AND matrix, all the input lines are connected to all output lines
through fuse-links, or programmable switch. Fuse may be blown off to disconnect the
diode from resistor terminal thereby making the existence of diode insignificant in the
circuit. This type of programming is permanent in nature as the fuse condition cannot be
restored to its original healthy condition. This programming, therefore, is called OTP
(One-Time Programming). The Fig. as shown above can be represented in a way shown
below:

Fig:-19

In case a programmable switch is present in place of fuse to connect or disconnect diode

to or from the circuit, the related technology is called RP (Re-Programmable). The M-
input, 1-output AND as shown in the Fig above is shown in the following figure in the
form of a matrix of size M  1 .

Fig:-20: AND Matrix : Compact representation of the same un-programed column

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If any one of the inputs is zero, the corresponding diode with its healthy fuse (or
connected switch) along the input line will get a zero volt at its cathode, and therefore
will start conducting current from +Vcc to the input. The corresponding output line will
be drawn in to a zero potential, irrespective of the state of other inputs connected to the
output line.

Thus, for an un-programmed matrix:

P0  I 0 I 0 I 1 I 1 ... I M 1 I M 1
Since I i and I 0 are connected simultaneously, at least one of them must be zero. That
is, P0  0 for an un-programmed switch.
When some of the inputs are removed either by blowing off fuses, or, by opening
switches, that respective inputs do not come in the expression of that corresponding
output P.
In Field-Programmable Logic Array (FPLA), these links/switches are user-
programmable.
In compact representation, this AND matrix with n-outputs (i.e., n-columns) takes the
following form:

Fig:-21

In Boolean representation,

P  I 0 I 0 I 1 I 1 ... I M 1 I M 1 .
Here, each of AND gates has 2M inputs. An ‘x’ mark represents an interconnection
between input and output, which is entirely programmable. Absence of ‘x’ mark (not
shown in this Fig) indicates that the corresponding row and column are left unconnected.
‘n’ product terms are available as output.

The array of AND gates form what is called AND plane. The corresponding matrix
formed by the rows and columns is called AND matrix. A compact representation of
AND matrix is shown below:

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Fig:-22

● OR Matrix:
A sample OR matrix is shown below. There are n product terms as input. These terms,
after OR operation, gives rise to N outputs.

Fig:-23

If any one of P inputs is at logic 1, all the transistors in the particular column of that P-
line become on. Transistors, containing healthy fuses (or, closed switches) connect Vcc

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line to their emitter side. The respective S-outputs, connected to these emitter sides,
therefore, get connected to Vcc supply. This means that when any one of P-columns is at
logic one, a transistor with healthy fuse (or, closed switch) raises the entire row to logic
one, irrespective of the statuses of other P-columns. Effectively, this is an OR operation
and may be represented as:

S  P0  P1  ... Pn 2  Pn 1

When the link (i.e., fuse or switch whichever is applicable) is broken, that particular P-
term vanishes from the respective S-output. The following Fig represents this feature in
compact form:

Fig:-24

The same figure as shown above may be represented as shown below:

Fig:-25

All of the outputs can be described in matrix form as shown below:

Fig:-26

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Here, each of OR gates has n inputs. An ‘x’ mark represents an interconnection between
input and output, which is entirely programmable. Absence of ‘x’ mark (not shown in this
Fig) indicates that the corresponding row and column are left unconnected. n product
terms are available to use as input and N sum terms are available as output.

The array of OR gates form what is called OR plane. The corresponding matrix formed
by the rows and columns is called OR matrix. A compact representation of AND matrix
is shown below:

Fig:-27

Combination of AND plane and OR plane form a programmable matrix as shown below:

Fig:-28

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In general, the representation of programmable matrix does not contain AND / OR gates.
Pictorially, this is:

Fig:-29

● Invert / Non-Invert Matrix:

The output from OR plane often contains inverters, output buffers, flipflops etc.

A typical circuit for invert / non-invert matrix is shown below:

Fig:-30

Output of the circuit is either S 0 or S 0 depending on whether fuse is intact (alternatively,

whether switch is closed).

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● Output buffers:

Output buffers are required to increase the driving capability of the PLA. The output may
be totem-pole (active pull-up), open-collector (passive pull-up) or three-state. A three-
state buffer is shown below:

Fig:-31

● Output through flipflops and buffers:

Sometimes flipflops are connected at the final stage in order to implement sequential
logic. The relevant circuit is

Fig:-32

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■Example: Development of Full Adder.

Fig:-33

The two outputs, sum and carry, may be expressed in terms of inputs as
S  ABC  ABC  ABC  ABC
Cy  AB  BC  CA

In the programmable plane of PLA, these Boolean expressions may be represented as

Fig:-34: PLA with required interconnection

When PLAs were introduced in the early 1970s by Philips, their main drawbacks were
that they were expensive to manufacture and offered somewhat poor speed performance.
Both disadvantages were due to the two levels of configurable logic, because
programmable logic planes were difficult to manufacture and introduced significant
propagation delays.

To overcome these weaknesses, programmable array logic (PAL) devices were

developed.

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■4. Programmable Array Logic (PAL) as PLD:

PAL has programmable AND array and a fixed OR array. Each of the OR gates receives
input from some of the AND gates. That is, all of the AND gates are not connected to any
particular OR gate.

Pictorially, this is

Fig:-35

☺Note:

1) For M inputs and ‘n’ product terms, number of fusible link is 2 M  n .

2) Each of the OR gates gets few product terms as input.
3) Some of the OR-gate outputs may feedback as input to AND plane with / without
inversion.
4) Each of the OR gates may be connected to a flipflop followed by a buffer /
inverter, that again may be connected to AND plane. PAL with flip flop is called
as registered PAL.
5) OR gate output may be connected to a generic block called macrocell. A
macrocell contains circuitry with fuses. This circuit assumes different forms when
fuses are kept intact or blown off in different combinations. The device, therefore,
possesses immense flexibility in acquiring various configurations. PAL with one
or more macrocell is called a configurable PAL.

The figure shown below demonstrates one feedback scheme. Some of the outputs from
OR plane re-circulates via AND plane and are again available as outputs from other OR
gates.

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Fig:-36

#. A sample macrocell:

Generally, a macrocell contains a multiplexer (MUX) along with other elements like
logic gates, flip-flops etc.
A multiplexer is an n-input 1-output device where only one input out of n available goes
to output. Pictorially this is

Fig:-37

In terms of logic expression output is given by

a when f  0
y
b when f  1
In SOP form it is y  af  bf that adds more generality to macrocell output.
In the following figure, a sample macrocell is shown.

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Fig:-38: A Macrocell

The fuses (alternatively switches) may be intact or opened. Accordingly, the macrocell
takes following forms:

Fig-(a) Fig-(b)

Fig-(c) Fig-(d)
Fig:-39: Various forms of a single macrocell

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■. Commercially available SPLDs:

Two of the most popular SPLDs (Simple PLDs) are the PALs produced by Advanced
Micro Devices (AMD) known as the 16R8 and 22V10. Both of these devices are industry
standards and are widely second-sourced by various companies.

The name ‘16R8’ means that the PAL has a maximum of 16 inputs (there are 8 dedicated
inputs and 8 inputs / outputs), and a maximum of 8 outputs. The ‘R’ refers to the type of
outputs provided by the PAL and means that each of the outputs is ‘registered’ by a D
flip-flop.

Similarly, the ‘22V10’ has a maximum of 22 inputs and 10 outputs. Here, the ‘V’ means
that each output is ‘versatile’ and can be configured in various ways – some
configurations registered and some not.

Another widely used and second sourced SPLD is the Altera Classic EP10. This device is
similar in complexity to PALs, but it offers more flexibility in the way the outputs are
produced and has longer AND, OR planes. In the EP610, outputs can be registered and
the flip-flops are configurable as any of D, T, JK, or SR.

There are also other companies that offer SPLD including ICT, Lattice, Cypress, and
Philips-Signetics.

Complex Programmable Logic Devices (CPLDs)

● Features:
1. SPLDs have limited number of inputs, outputs and product terms. To implement
circuits with larger inputs, outputs, product terms and complexities, either
multiple SPLDs are to be interconnected properly for expansion of size and
complexities, or CPLDs are to be used.
2. A typical PAL has 8 macrocells whereas a CPLD has macrocells of the order of
512 or more. Each macrocell has greater variety also.
3. CPLDs consist of multiple SPLD-like blocks on a single chip. But these SPLD-
like blocks are even more complex than SPLD blocks.
4. CPLDs are mainly of EEPROM type.

CPLDs were pioneered by Altera, first in their family of chips called classic EPLDs
(Enhanced PLDs), and then in additional series, called MAX 5000, MAX 7000 and MAX
9000.

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■1. Altera CPLDs:

Altera has developed three families of chips that fit within CPLD category: MAX 5000,
MAX 7000 and MAX 9000.

1) MAX 5000 represent an older technology that offers a cost-effective solution.

2) MAX 9000 is similar to MAX 7000, except that MAX 9000 offers higher logic
capacity (The industry’s highest for CPLDs).
3) MAX 7000 series is widely used in situation where use of CPLD is sufficient, and
offers state of the art logic capacity and speed performance.

Fig:-40

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◘ MAX 7000 series:

This CPLD consists of a programmable circuit called Logic Array Block (LAB),
Programmable Interconnect Array (PIA) acting as a switch matrix to couple various
LABs in various fashions, and I/O Block to communicate with outside world.

Fig:-41

1) A LAB can be thought of as a complex SPLD-like structure, and so the entire chip can
be considered to be an array of SPLDs.

2) Each of the LABs may be configured as an array of inputs or an array of outputs. In

any of these cases, one side of the LAB is connected to one I/O Block to communicate
with external world; the other side is connected to other LABs through PIA.
Alternatively, a LAB may be configured as an array of both of inputs and outputs – that
is, of mixed type.

3) The I/O Blocks also may be connected directly to PIA.

4) MAX 7000 devices are based on EPROM and/or EEPROM technology. Therefore,
after the CPLD is powered-off and restarted again, the last configuration of the devices is
restored.

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5) Each LAB consists of two sets of eight macrocells.

The following figure shows one such macrocell:

Fig:-42

A macrocell comprises a set of programmable product-terms (part of an AND-plane) that

feeds an OR-gate and a flip-flop.

6) The flip-flops can be configured as D type, JK, T, SR or can be transparent.

7) As illustrated in the figure shown above number of inputs to the OR-gate in a

macrocell is variable; The OR-gate can be fed from any or all of the five product terms
within the macrocell, and in addition can have up to 15 extra product terms from
macrocells in the same LAB (as there are 16 macrocells within a single LAB).

8) The product select matrix provides required switching from AND matrix or from local
LAB interconnect, towards OR-gate.

9) As typical logic functions do not need more than five product terms, MAX 7000 series
LAB is very efficient in terms of chip area.

■2. Xilinx CPLDs:

Xilinx offers one family of CPLDs, called XC 7000, and a newer family, called XC 9500
family.
In XC 7000 family, two series of CPLDs are offered – one 7200 series, another 7300
series.

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◘ 7200 series:

1) These are moderately small devices, with about 600 to 1500 gates capacity.

2) They offer speed-performance of about 25 ns pin-to-pin delays. A pin-to-pin delay can

be computed as
Pin-to-pin delay = delay in unit length of signal-path × total length of signal-path
+ gate-delay × total no. of gates + delay in single switch ×
total no. of switches in signal-path.
3) Each chip consists of a collection of SPLD-like blocks and each of the blocks has nine
macrocells.

4) Each macrocell includes two OR-gates each of which is input to a two-bit Arithmatic
Logic Unit (ALU).

5) The ALU can produce any functions of its two inputs, and its output feeds a
configurable flip-flop.

◘ 7300 series:

It is an enhanced version of 7200 series, offering more logic capacity (upto 3000 gates)
and higher speed performance.

◘ XC9500 family:

It offers a logic capacity of 6200 logic gates, offers in-circuit programmability with 5 ns
pin-to-pin delays.

■ Programming a CPLD:

Two type of programming technique is available.

1) Out-of-board programming:

When the chip has relatively small number of pins and can therefore be taken out of the
circuit board without much of inconvenience this technique is used. Here, the chip is put
in a programming unit (called programmer). This technique is also called out-of-circuit
programming.

1) In System Programming (ISP):

In case of CPLDs, instead of relying on a programming unit to configure a chip, the chip
is programmed while it is attached to the circuit board itself. This method of
programming is called In System Programming / In-circuit Programming.

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Reasons for employing ISP:

1) CPLDs may have large number of pins (may even exceed 200) on the chip package,
and these pins are fragile and easily bent.

2) A socket is required to hold the chip in a programming unit. For large CPLDs the
packages used are very expensive, sometimes more expensive than the CPLD device
itself. The whole process of out-of-board programming is therefore complex and costly.

3) As a large number of programmable switches need to be configured, it is not

practically feasible for a user of these chips to specify manually the desired state of each
switch. For this purpose, ISP incorporates a Computer-Aided Design (CAD) system.

■ Computer – Aided Design (CAD):

A typical CAD system would include software for the following tasks:

a) Initial Design Entry:

Fig:-43

Initial design entry may be done either by

1) Creating a schematic diagram with a graphical CAD tool.

2) Using a text-based language to describe a design in a Hardware Description Language
(HDL).
3) Incorporating a mixture of the previous design methods.

This design entry is the only step performed manually by the designer – all other steps are
carried out automatically by most of the CAD systems.

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b) Merge & Translate:

All the designs are combined together and translated in to a form that can be used
subsequently for next stage processing.

c) Optimization of Equations:

The logic equations thereby formed are optimized through the use of certain algorithm.
The resulting equation is simplified in terms of number of logic gates and flip-flops,
interconnection among various circuit-elements etc.

d) Device Fitter:

Fitting into CPLD means that the logic equations are expressed and implemented through
the resources available within the hardware. In this stage hardware is not configured
physically. The detailed mapping of hardware, reflected in CAD software, is used to fit
equations in simulation environment to test whether the practical fitting is possible.
The device fitting consists of following steps:

 Basic logic blocks developed in a program are mapped into available logic
blocks of the targeted hardware, in software environment.
 If the available logic blocks are more than the blocks used in program,
which is the most frequent cases, some predefined algorithm is used to
select actual blocks over chip area.
 A ‘router’ program is used to allocate interconnect wires to connect
various blocks of the targeted hardware.
 Programmers sometimes impose pin-constraints and / or time-constraints.

Pin-constraints are nothing but assigning pins in advance for input-output

signals. Hardware, then, cannot allocate pins ‘freely’ following any
predefined algorithm.

Time-constraints are nothing but assigning maximum permissible pin-to-

pin delays that the user can tolerate. The hardware will try to allocate
interconnect wires in such a way so as to meet the criteria. This constraint
is useful in time-critical applications.

Drive strength sets the worst case minimum current that will be available.
Worst case is measured at hottest temperature, worst (slowest) process,
and lowest IO voltage.

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If the constraints are not fulfilled during device fitting (all being done in
software environment), an error message is conveyed regarding failure of
fitting.

Fitting is nothing but generating configuration bits for programmable switches in order to
open or close them. The configuration bits are stored in a file called configuration file
which acts as fuse map specifying the state of each switch in the targeted hardware.

e) Simulation:

Simulation is the artificial operation of the hardware developed through program, in

software environment. As if the hardware is configured and it runs on some test signal
input. The test signal itself is another signal generated by writing progam(s). The
consequent output waveform(s) too is/are obtained in the software environment. These
outputs indicate whether the targeted hardware will behave in a way desired by
programmer / developer.
Simulation is an optional stage before configuring hardware, although desirable for
checking the operation of the programmed hardware. If the hardware does not exist
physically, correct simulation will be the objective of the programmer. At this, only step
(a) is sufficient as prerequisite.

Fig-44

f) Program Downloading:

This is the last step for configuring the hardware as per the program. The circuitry on the
hardware, that allows In-System-Programming (ISP) has been standardized by the IEEE
and is usually called a JTAG port. In case of ISP technique, a small connector is included
in the Printed Circuit Board (PCB) containing hardware. This connector along with the
required circuitry is the JTAG port. JTAG stands for Joint Test Action Group. A cable,
called JTAG cable, runs from JTAG port to the port of a computer. The latter may be a
COM port, LPT port, or a USB port (of growing use). The JTAG cable contains six wires
of which four wires are used to transfer information between the computer and the device
being programmed. These six pins are:
i. TCK (clock) - Test clock
ii. TDI (data input) - Test data input
iii. TDO (data output) - Test data output
iv. TMS - Test mode select input
v. Vcc - Power supply
vi. GND - Ground

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Fig-45

Fig:-43

Fig-46

■ Applications of CPLDs:

1) CPLDs can realize reasonably complex designs, such as graphics controller, LAN
controllers, UARTs, cache control, and many others. As a general rule of thumb, circuits
that can exhibit wide AND / OR gates, and do not need a very large number of flip-flops
are good candidates for implementation in CPLDs.

2) A significant advantage of CPLDs is that they provide simple design changes through
re-programming. With in-system programmable CPLDs it is even possible to reconfigure
hardware without power-down. An example in this respect might be to change a protocol
for communication circuit.

3) Sometimes it is advantageous to segregate a single design in to some basic modules.

These basic modules (i.e., design pieces) may be mapped in to different areas of a chip.
As a CPLD is a complex combination of SPLD-like blocks, each block may shadow a
design piece quite easily. The result is more predictable in speed-performance where the
overall delay generation will be a combination of gate-delays within each block plus
interconnect delays.

Predictability of circuit implementation is of the strongest advantages of CPLD

architectures.

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◘ Disadvantages:

1) No internal clock source or clock circuit is available in CPLD. Hence, an external

clock source is mandatory.

2) CPLD is suited for implementing combinational and sequential circuits. It, however, is
not optimized for fabricating RAM / ROM within it.

3) Implementation of processor is not possible in CPLD as it does not have internal

memory structure and dedicated ALU.

Field Programmable Gate Arrays (FPGAs)

FPGAs are a special form of programmable devices with higher densities and
complexities to SPLDs and CPLDs. In SPLDs, programming technique may be either
through Mask-type or through CAD tool. In CPLDs, it is mostly through CAD tool, and
in FPGA, programming is entirely through CAD tool.

Logic chips that are programmed through Mask-based technologies are called Mask
Programmable Gate Arrays (MPGAs). MPGAs consist of an array of pre-fabricated
transistors that can be customized into the user’s logic circuit by connecting the
transistors with custom wires. Customization is performed during chip fabrication by
specifying the metal interconnect. This means that in order for a user to employ an
MPGA a large setup cost is involved and manufacturing time is long.

An FPGA differs from CPLDs (and obviously from SPLDs) and MPGAs on following
aspects:

1. FPGA configuration is performed through programming by the end user, using CAD
tool. This tool offers lot of flexibilities in the development process of a design and user-
specified constraints can be tackled quite easily.

2. Programmable switches employed here are either SRAM-based or based on antifuse

technology.

3. FPGA has extremely high logic capacity, even much higher than CPLDs of largest
logic capacity, in terms of number of equivalent gates as well as in terms of complexity
level of each low-level gate.

4. Memory blocks exist as in-built structure within chip, unlike CPLDs. Thus, along with
implementation of logic functions, a full-fledged processor may be implemented using
FPGA.

5. Presence of internal clock source within FPGA eliminates the need of external
oscillator while designing sequential circuit.

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■ Switching Technologies:
Programmable switches may be of following types:
1) SRAM based - already discussed.
2) Antifuse based

● SRAM based switch:

When FPGAs are powered off, configuration bits stored in RAM of FPGAs are
automatically erased.

Next time when power comes, FPGA cannot run since the programmable switches have
no more defined status, hence the connectivity too.

Thus, configuration bits need to be reloaded every time the system is powered up. This
reloading may be done by JTAG cable either from some computer or from other
equivalent devices (like E2PROM etc.), or there may be an automatic loader for this
purpose.

Lattice semiconductor, therefore, has constructed a two layer memories, the top layer
being the E2PROM containing the program (or, configuration bits permanently). The
bottom layer (or, running layer) containing SRAM reloads every time the power comes
up, the configuration bits from the top layer and runs subsequently.

◙ Disadvantages:
1. Loading of E2PROM is slow.

2. Loading of SRAM layer from E2PROM is slow because of slow speed of RAM.

3. SRAM cells themselves are not radiation hardened.

4. Hence, Quicklogic has removed SRAM layer and developed fast E2PROM, a
costly alternative used many where, e.g., in space applications.
● Antifuse:

Fig:-47: Actel Antifuse

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An antifuse is an electrical device that performs the opposite function to a fuse. Whereas
a fuse starts with a low resistance and is designed to permanently break an electrically
conductive path (typically when the current through the path exceeds a specified limit),
an antifuse starts with a high resistance and is designed to permanently create an
electrically conductive path (typically when the voltage across the antifuse exceeds a
certain level). Antifuses are suitable for FPGAs because they can be built using modified
CMOS technology. As an example, Actel’s antifuse structure, known as PLICE, is
depicted in the figure above.

The figure shows that an antifuse is positioned between two interconnect wires and
physically consists of three sandwiched layers: top and bottom layers are conductors, and
the middle layer is an insulator. When unprogrammed, the insulator isolates the top and
bottom layers, but when programmed the insulator changes to become a low-resistance
link.

PLICE uses Poly-Si and n+ diffusion as conductors and ONO as an insulator, but other
antifuses rely on metal for conductors, with amorphous silicon as the middle layer.

Fig:-48: Actel Antifuse

Quick logic’s antifuse structure, called ViaLink, consists of a top layer of metal, an
insulating layer of amorphous silicon, and a bottom layer of metal. When compared to
Actel’s PLICE antifuse, ViaLink offers a very low on-resistance of about 50 ohms
(PLICE is about 300 ohms) and a low parasitic capacitance.
Following table shows most important characteristics of the programming technologies.
The left-most column of the table indicates whether the programmable switches are One-
Time Programmable (OTP), or can be Re-Programmable (RP). The next column lists
whether the switches are volatile, and the last column names the underlying transistor
technology.

Name Re-Programmable Volatile Technology Chip area

Fuse no no Bipolar relatively large
EPROM yes (out of circuit) no UVCMOS small
EEPROM yes (in circuit) no EECMOS 2xEPROM
SRAM yes (in circuit) yes CMOS large
Antifuse no no CMOS+ small

Fig:-49: Summary of programmable technologies

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FPGA Structure
The structure of FPGA consists of logic block as its logical unit. This logic block can be
as simple as a transistor or as complex as a microprocessor. It is typically capable of
implementing many different combinational and sequential logic functions. Current
commercial FPGAs employ logic blocks that are based on one or more of the following:

1) Transistor pairs
2) Basic small gates such as two-input NANDs or exclusive-Ors.
3) Multiplexers
4) Look-up tables (LUTs)
5) Wide fan-in AND-OR structures

For all the logic blocks mentioned above it will be shown how the logic functions:
f  a.b  c
can be implemented with different circuit realizations.

■1. f  a.b  c using transistors:

The FPGA from Crosspoint solutions uses a single transistor pair in the logic block as
shown below:

Fig:-50

Fig:-51

A series of transistor pairs run parallel of which some pairs are taken for interconnecting
among themselves, rests being kept isolated.

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Fig:-52: Transistor Pair with biasing

Fig:-53: Transistor Pair connected appropriately

Fig:-54: Transistor Pair connected appropriately

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Fig:-55: Implemented logic:- f = a.b

Fig:-56: Implemented logic:- f = a.b

● A transistor like 1 through 5 can be used as a closed switch when corresponding base
terminal receives logic 1.

● A transistor like 1 through 5 can be used as a closed switch when corresponding base
terminal receives logic 0.

Now,

1. When a = 1, s is connected to t; but p decoupled from q.

2. When b = 1, t is connected to u; but q decoupled from r.
Thus, when a.b = 1, s is connected to u; but p decoupled from r.

Therefore, u, r & p, being connected together, are grounded, as s is grounded.

3. It means that m is also grounded.

4. Hence, w is connected to v. As w = 1 (being connected to +5V), v = 1. Hence, f = 1.

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Thus, when a.b = 1, f = 1.

5. When c = 0, i.e., c  1 , z is connected to w, i.e., z = 1. Hence, f = 1.

Thus, when c  1, f  1.

As a whole, f  a.b  c

■2. f  a.b  c using basic small gates:

Fig:-57: f  a.b  c using basic small gates

■3. f  a.b  c using multiplexers:

Fig:-58: Basic multiplexers

When s = 1, f = a.
When s = 0, f = b.
Thus, f  s.a  s.b
Evidently,
1. When b = 0, f = s.a, i.e., AND function is implemented.
2. When a = 1, f  s  s.b  s  b , OR function is implemented.
By connecting together a number of multiplexers and basic logic gates, a logic block can
be constructed which can implement a large number of functions in this manner.

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In order to implement f  a.b  c , Actel Act-1 logic block is used here as an example. It
consists of three multiplexers and one logic gate and has a total of 8 inputs and one
output.

Fig:-59: Actel Act-1using multiplexers

__ __ __________
Here, P  S1 .x  S1 .w , Q  S 2 .z  S 2 . y And f  S 3  S 4 .Q  S 3  S 4 .P
 __
 __________  __

Hence, f  S 3  S 4 . S 2 .z  S 2 . y   S 3  S 4 . S1 .x  S1 .w 
   
By setting each of the variables to an input signal, or to a constant, 702 logic functions
can be realized.
In the present case, by setting w = 1, x = 1, S1 = 0, y = 0, z = a, S2 = b, S3 = c and S4 = 0,
the function f  a.b  c is realized.

The Act-2 logic block is similar to Act-1, except that the separate multiplexers on the first
row are joined and connected to a Two-point AND gate as shown.

Fig:-60: Actel Act-2 using multiplexers

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The Act-2 combinational logic module can implement 766 logic functions.

Note:

Multiplexer – based logic blocks have the advantage of providing a large degree of
functionality for a relatively small number of transistors.

This is, however, achieved at the expense of a large number of inputs, which when
utilized, place high demands on the routing resources. Such blocks are, therefore, more
suited to FPGAs that use programmable switches of small size such as antifuses.

■4. f  a.b  c using Look – Up Tables (LUTs):

A lookup table is an array of output against another array of input combinations with one-
to-one correspondence between them. SRAM is used mainly as programmable switch.
The truth table for a k – input logic function is stored in a 2k x 1 SRAM.

The address lines of the SRAM function as inputs and the output of the SRAM provides
the value of the logic function. The example of f  a.b  c is shown below.

a b c f
0 0 0 1
0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 1

Fig:-61: f  a.b  c using Look – Up Tables (LUTs)

It is seen from the truth table that the bit – 1 is stored in cells with addresses 000, 010,
100, 110 and 111 only. Effectively, this is a memory of capacity 8 x 1.

Fig:-62: LUT as block

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The advantage of Lookup Tables is that they exhibit high functionality – a k-input LUT
k
can implement any function of k-inputs and there are 2 2 such functions.

The disadvantage is that they are unacceptably large for more than about five inputs,
since the number of memory cells needed for a k-input lookup table is 2k.

While the number of functions that can be implemented increases very fast, these
additional functions are not commonly used in logic designs and are also difficult to
exploit for a logic synthesis tool. Hence, it is often the case that a large LUT will be
largely underutilized.

■5. f  a.b  c using wide fan-in AND-OR structures:

The architecture of some FPGAs has evolved from the PLA based architecture of
traditional PLDs with its logic block consisting of wide fan-in (20 to over 100 inputs)
AND gates feeding into an OR gate with three to eight inputs.

Altera MAX 5000 series logic is the example of this kind:

Fig:-63: Altera MAX 5000

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Fig:-64: Altera MAX 5000 for the said logic

Using the floating gate transistor-based programmable switch, any vertical wire passing
by an AND gate can be connected as an input to the gate.

The advantage of this type of block is that the wide AND gate can be used to form logic
functions with few levels of logic blocks, reducing the need for programmable
interconnect.

It is difficult, however, to make efficient use of all of the inputs to all of the gates,
resulting in loss of density.

Another disadvantage of the wired-AND configuration is the use of pull-up devices that
consume static power. An array full of these pull-ups will consume significant amount of
power. To mitigate this, each gate in the MAX 7000 series block can be programmed to
consume about 60% less power but at the expense of about 40% increase in delay. This
feature can be used in non-critical paths to reduce power consumption.

Nowadays, logic blocks of FPGAs are getting more complicated to eliminate various
disadvantages encountered in any particular form as mentioned above. These blocks
consist of features which are the result of combination of various architectures. As an
example, Altera FLEX 8000 contains logic element that consists of LUTs, sequential
circuit (flip flop) and multiplexers. AT & T ORCA FPGA contains LUTs, multiplexers
and sequential circuits.

■ Xilinx SRAM-based FPGAs :

 Xilinx introduced first FPGA family, XC2000 series, in about 1985.

 Three more generations came after that: XC3000, XC4000, and XC5000, out of
which XC4000 family is most popular and is under consideration for the present
illustration purpose.

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 XC5000 is cheaper but similar with XC4000 although with same sacrifice in
speed.

 These FPGAs are SRAM based. But Xilinx has recently introduced an FPGA
family based an anti-fuses, called the XC8100.

 A new version of this family, the 4000E, has the additional feature that the RAM
can be configured as a dual part RAM with a single write part and two read parts.

Features:
 The basic structure of the Xilinx is array based.

 The Xilinx4000 family devices range in capacity from about 2000 to more than
15000 equivalent gates.

 The XC4000 features a logic block, called a Configurable Logic Block (CLB) that
is based on look-up tables (LUTs).

 Constructed a two layer memories, the top layer being the E2PROM containing
the program (or, configuration bits permanently).

 The bottom layer (or, running layer) containing SRAM reloads every time the
power comes up, the configuration bits from the top layer and runs afterwards.

Fig:-65: Xilinx XC4000 CLB

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 The XC4000 CLB contains three separate LUTs, as shown. There are two 4-input
LUTs that are led by CLB inputs, And the third LUT can be used in combination
with the other two.

 This arrangement allows the CLB to implement a wide range of logic functions of
upto nine inputs, two separate functions of four inputs or other possibilities.

 Each CLB also contains two flipflops with which sequential circuit can also be
implemented.

 The XC4000 chips have “system oriented” features. For instance, each CLB
contains circuitry that allows it to efficiently perform arithmetic (ie., a circuit that
can implement a fast carry operation for adder like circuits).

 The LUTs in a CLB can be configured as read / write RAM cells.

 Besides logic, the other key feature that characterizes an FPGA is its interconnect
structure. The XC4000 interconnect is arranged in horizontal and vertical
channels.

Each channel contains some number of short wire segment that span a single CLB ( the
number of segments in each channel depends on a specific part number), larger segments
that span two CLBs, and very long segments that span the entire length or width of the
chip.

Fig:-66: Xilinx XC4000 CLB: wire segments

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Programmable switches are available to connect the inputs and outputs of the CLBs to the
wire segments, or to connect one wire segment to another.
The speed performance of an implemented circuit depends in part on how the wire
segments are allocated to individual signals by CAD tools and therefore may vary from
the specification in initial design entry.

Evolution of Xilinx FPGAs in terms of memory capacity and clock speed are given in
the following figure.

Fig:-67: Evolution of Xilinx FPGA

There is a trend of decreasing voltage of logic circuitry after the advent and advancement
of CMOS technology. This is presented below:

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In terms of other features these are:

IP Core:

In electronic design a semiconductor intellectual property core, IP core, or IP block is a

reusable unit of logic, cell, or chip layout design that is the intellectual property of one
party. IP cores may be licensed to another party or can be owned and used by a single
party alone. The term is derived from the licensing of the patent and/or source code
copyright that exist in the design. IP cores can be used as building blocks within ASIC
chip designs or FPGA logic designs.

The IP core can be described as being for chip design what a library is for computer
programming or a discrete integrated circuit component is for printed circuit board
design.

When IP cores are of type soft core, they are typically offered as synthesizable RTL.
Synthesizable cores are delivered in a hardware description language such as Verilog or
VHDL. These are analogous to high level languages such as C in the field of computer
programming.

As hard core, they come as a particular hardware entity for analog, mixed signal and
digital logic circuit with a particular layout for their use by a chip maker.

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 Example: Implementable design of…

-- Signal processing algorithm like

Transform, Encryption algorithm, Deciphering algorithm, Adaptive filter

-- Communication protocol like

Hyper Text Transfer Protocol (HTTP), File Transfer Protocol (FTP), Bluetooth
Protocol

-- Bus Controller

USB controller, PCI Bus Controller

■ Applications of FPGAs:
FPGA is a digital hardware that is user-configurable. It is a programmable structure that
acquires the final configuration for functioning in a desired way. The configurability is
achieved by using a CAD tool and a standard Hardware Description Language (HDL).

FPGA finds application in:

a) Signal processing, especially in time-critical and computation-intensive signal

processing and control

b) Prototyping of designs later to be implemented in gate arrays and also emulation of

entire large hardware systems.

c) Custom computing machine which is only beginning to be developed. This involves

using the programmable parts to ‘execute’ software, rather than compiling the software
for execution on a regular CPU.

[Compilation means converting a source code, upon debugging, into a form which is
understood by a fixed hardware, i.e., processor, and executed by a processor thereafter.

In custom computing machine, hardware configures itself to a form demanded by

software so that the software will be executed (run) on the newly configured hardware in
machine.]

It is possible that the success of the FPGA in the digital world may be reproduced in the
analog domain, with a field programmable analog array (FPAA). Such work has already
begun.

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