What is meants by 7.5 Track and 9 Track ?
Tracks are path drawn on an SoC as soon as it is manufactured. All the connections between
various cells of the SoC can be made only and only through tracks. We can think Tracks as
parallel lines where transfer can take place together. 9 tracks implying 9 lanes of roads where 9
vehicles can travel at the same time. It is the part of Architecture used by an SoC.
The above image is from ARM 16ffc Datasheet it shows an architectural view of the 7.5
Track technology. Here 7 track is 64nm wide and there is one track 32nm wide thereby
constituting 7.5 Track. Apart from this there is a similar 9 Track technology.
HOW ARE NETS DIFFERENT FROM TRACKS?
NETS are nothing but the connections made between various cells on a SoC. All the NETS
between cells are made only through tracks.
For eg., 16ffc has two track support 9 and 7.5
WHAT ARE CELLS? WHAT DO WE MEAN BY COMBINATIONAL,
SEQUENTIAL AND COMPLEX COMBO CELLS?
Any functional unit over an SoC are called cells. The cells that takes clocks as input are
called Sequential cells and those without clocks are combinational cells. The smallest unit
constituting these cells are the UNIVERSAL NAND gates. Each cells needs PG_PIN which
in lower language is nothing but a ground pin.
HOW ARE HOLD TIME INDEPENDENT OF FREQUENCIES?
can we fix this HOLD time violation by changing frequency?
Consider the below example:
data1 = data at ff1
data2 = data at ff2
clock1= launch clock
clock2= capture clock
At the clock1, data1 is being sampled at ff2, and at clock2 data2( data of ff1 that is data1) is
already reach to ff2 already
from the figure setup checks equation , that is
Tc2q(ff1) + Tcomb = Tclk - Tsetup
data1 of ff1 at clock1 should reach at ff2 in clock2 before the setup time of ff2.
from the hold checks,that is Tc2q + Tcomb >= T(hold)
data1 should not arrive at ff2 at clock2 before hold time because it override the data2.
which means that data is overridden by next data because data comes to much fast that override
the previous data that is captured by previous clock edge, so, functionality of chip is getting
failed.
If the delay of combo logic and Tc2q delay is less than the hold time of ff2 than data comes too
much fast that which does not give setup violation but result in hold violation, so, due to this
condition data that is already capture data at ff2(data2) overrides by the data1 at the clock2 edge.
so, it is only depends on the Tcombo and Tc2q, and Tcombo and Tc2q is not depends upon the
clock period or working frequency.
so, Hold is independent of frequency.
what do we mean by SIGMA IN SoC physical design? How do we derive it?
calculating sigma in MATHS:
• Work out the Mean (the simple average of the numbers)
• Then for each number: subtract the Mean and square the result.
• Then work out the mean of those squared differences.
• Take the square root of that and we are done!
What does it means by 3sigma in SoC?
3sigma means that out of the 100 chips that are manufactured by the foundry 99.7 lies within
the range of reasonable products that aren't defected and are good to go. The timing corners
that we talked about in our discussions are nothing but the USL(Upper Specification Limit)
and LSL(Lower Specification Limit) defined by the customer.
We learn about this concept in a better way when we learn about Cp and Cpk.
WHAT IS Cp AND Cpk?
This is the most basic flow of any SoC or any other product manufactured at any other
company. What is the role of Cp and Cpk is that both of these measure how much the
manufactured product is in-line with the specifications given by the customer.
NOTE: one assumption that we take while calculating Cp or Cpk that the performance
is a controlled performance. This is in no turn related to design specification
eg., consider a CAR manufacturing firm where 210 products are manufactured whose
customer requirement was comfortable seat. So the designer decided to use Foam seats with
the density say 465kg/m3 with + or - 15kg/m3 of tolerance allowed. In statistics we start with
plotting a control chart for these 210 CARS so as to gain a view upon how many of the
products lie within the range of 450kg/m3 to 480kg/m3.
NOTE: Control chart only takes subgroup averages however the individual product might
still lie outside these limits
What are the subgroups we have formed?
we have divided these 210 cars in group of 10, taken the average of the foam density of
individual cars in each group and then plotted the subgroup average over the graph.
An excel screenshot on how we will we
dividing the data values into subgroups and calculating their averages.
The histogram for individual CAR will be widely dispersed however this will be
narrower if divided into subgroups. see graph below
Now to decide if the product manufactured by us lies withing the range of specifications
and tolerance we need a variable that establishes relation between specification width
and process width.
Specification width is nothing but USL-LSL given by customer
Process width is 3 x. All individual value lies within this width.
Cp= Specification width/ Process width
x is standard deviation of subgroup averages to calculate of individual product we
have various statistical methods.
Why to move to Cpk?
The problem with Cp is that it takes each process to be centred around the
mean of the distribution curve however this isn't the case always so we take
another variable Cpk which is the indicator of how centred the process is.
In real practice Cp and Cpk should be used together as Cpk gives the estimate
of how centred the process is while Cp gives the estimate of how variables are
distributed within the given range.
HOW DO WE DEFINE CORNERS? WHAT IS MEANT BY WORST CORNER AND
BEST CORNER FOR A DESIGN?
HOW ARE POWER, AREA AND PERFORMANCE CHARACTERISTICS/
CONSTRAINT DECIDED OVER A SoC?
