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6502 Processor Data Sheet

Data sheet of 6502 processor.

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Gioser Zamora
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1K views16 pages

6502 Processor Data Sheet

Data sheet of 6502 processor.

Uploaded by

Gioser Zamora
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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) Rockwell R650X @ R651X R650X and R651X Microprocessors (CPU) DESCRIPTION The B-bit FG5OO microprocessor devices are produced with N-channel, scan gate technology. Performance speeds are enhanced by advanced system architecture. This Innovative architecture results in smaller chips—the semiconductor threshold is cost-etfectivity. System cost-efectvity is further enhanced by providing a family of 10 sottware-compatible microprocessor (CPU) devices, described in this document. Rockwell also provides single chip microcomputers, memory and Peripheral devices—as well as low-cost design aids and ‘documentation. ‘Ten CPU devices are available. All are software-compatible, ‘They provide options of addressable memory, intrrupt input, ‘on-chip clock oscilators and drivers. All are bus-compatioe with ‘earlar generation microprocessors like the M8800 devices. ‘The RESOX and R651X family includes sic microprocessors with ‘on-board clock oscitators and drivers and four microprocessors ¢21000, eon Baa ira oo vee or 40 Boz as Eos 42 Bios 43 Eos a Eos as For a8 Ean a E ato 6507 FEATURES: ‘© 8k addressable bytes of memory (A0-A12) = Onrchip clock = ROY signal © 26-pin DIP 6512 FEATURES + 84K addressable bytes of memory (A0-A15) ‘= Two phase clock input + FRO intorrupt = Ri interrupt = ADY signal * SYNC signat Data Bus Enable + 40-pin DIP 28} o (oun 2Eeoum asain 25-00 2aBa01 232 zbos aifos 20f3 05 1B os abo? var wean Pato “Pins 37 a 39 are conacted narraty R650X, R651X R6500 Microprocessors (CPU) 6513 FEATURES ‘* 4K addressable bytes of memory (AQ-A11) ‘¢ Two phase clack input © TRO interrupt «eR interrupt * 28-pin DIP 6514 FEATURES 8K addressable bytes of memory (AO-A12) Two phase clack irput TRG interrupt 28-pin DIP 6515 FEATURES | © 4K addressable bytes of memory (AQ-A11) ‘= Two phase clock input FFG intorrupt ‘¢ ROY signal + 26-pin DIP R650X, R651X R6500 Microprocessors (CPU) FUNCTIONAL DESCRIPTION ‘The intemal organization ofall R8500 CPUS is identical except ‘or some variations in clock interface, the number of address ‘output ines, and some unique inputoutput lines between versions. CLOCK GENERATOR “The clock generator develops al intemal clock signals, and (where picabe) extemal clock signals, associated wih the device. itis the clock ganerator that drives the timing contol unit andthe exter- ral timing for slave mode operations TIMING CONTROL ‘The timing control unit keeps track ofthe instruction cycle being ‘monitored. The unitis set to zoro each ime an instruction fetch ‘executed and is advanced at the beginning of each phase one. dock puise for as many cycles as Is required to complete the: istration. Each data transl which takes place between the reg- {stors depends upan decoding the contents of both the instruction ngister and the timing control unit PROGRAM COUNTER ‘The 16-bit program counter provides the addresses which step the microprocessor through sequential instructions in a program. Each time the microprocessor fetches an instruction from pro- ‘gram memory, the lower byte of the program counter (PCL) is placed on the low-order bits of the address bus and the higher byte of the program counter (PCH) is placed on the high-order Bits. The counter is sncremented each time an instruction oF dala is fetched fromprogram memory, INSTRUCTION REGISTER AND DECODE Instructions fetched from memory are gated onto the internal ‘dala bus. These instructions are latched into the instuction regis ter, then decoded. along with iming and interrupt signais, to gen erate control signals for the various registers. ARITHMETIC AND LOGIC UNIT (ALU) Al aritetic and logic operations take place in the ALU including Incrementing and decrementing intemal registers (except the oro: ‘gram counter). The ALU hasno intemal memory andi used only to perform logical and transient numerical operations, ACCUMULATOR, ‘The accumulator is a general purpose &-bit register that stores {he results of most arithmatic anc logic operations, and in add tion, the accumulator usually contains one of the two data words ‘used in these operations. INDEX REGISTERS ‘There are two &-bitindox registers (X and Y}, which may be used ‘toccount program steps orto provide an index value to be used in generating an elfectve address. \When executing an instruction which specifies indexed adaressing the CPU fetches the op code and the base address. and modifies the address by adding the index register tot prior to performing he ‘desired operation. Pre- or postindexing of indirect addresses is possible (see addressing modes). STACK POINTER “The stack pointaris an 8-bit register used to control the ackrassing ‘ofthe variable-length stack on page one. The stack pointe Is auto: ‘matically incremented and decremented under contro ol the micro- processor to perform stack manipulations under direction of either {he program or interrupts (“Mi and 1G). The stack alows simple implomentation of nested subroutines and multiple level interupts. ‘The stack pointer should be intialized before any interrupts or stack ‘operations cccur PROCESSOR STATUS REGISTER ‘The B-bt processor status registor contains seven status flags. ‘Some of the flags are controled by the program, others may be ‘onivoled bath by the program and the CPU, R650X, R651X R6500 Microprocessors (CPU) + aeaisren section CONTROL SECTION —p> 5 0 wm 7 f] [ace FS} oe os : | o+ “FR soopess T H “| memo fey ects, a fe pala be oe a aje~ ane eo | ee ncoaren i Pharr une Jone | ose ne oe nore 1. CLOCK GENERATOR IS NOT INCLUDED ON 6512. RE5I2, RESI4 AND RESIS, 2. ADDRESSING CAPABILITY AND CONTROL OPTIONS VARY WITH EACH OF ‘THE CPUs, 9, R502, REEO9, RES04, RESOS, REEO6 AND ESOT. 4. 6512, RESTS, RSS14 AND RES4S. 5. R512 ONLY. 6. A502 AND Résos. 5OX and RBSIX Internal Architecture R6S50X, R651X R6500 Microprocessors (CPU) INSTRUCTION SET ‘The R6500 CPU has 56 instruction types which are enhanced by up to 19 addressing modes for each instruction. The Alphabetic Listing of Instruction Set ‘Accumulator. index registers, Program Counter, Stack Pointer ‘and Processor Status Register are ilustrated below. Sem = me rae #5e | ~ edsanay ws Aan Coy noma liens cus as fe || aac ence oe toy | cance eee, co S| oe i repose mr | cae i eee tea S| oy Socenence See ncaa Be pesos | | Se | ceases ee ee | eeaee ee | coe a | oe See | coors a oo er os See | ro hancsseonr ena By || bated Soe | cece | eee Bo || fate fen || Reo encores 2 a eee ert | coarse A nace Se | coe =) ee ee oe | eevee ce | comer eos So es et conte ees S Stores ace SA Sorc ey |e | Shove ee scene oo Me | woceer os = oo be cee os 7 caiaetace oo tac erenest eee oo | iene tecernece = Cacti ; : ; ; A ACCUMULATOR A iN] ¥]+[8]0]1]Z[C} processor staus REG ‘P” —s<) : (=F necro y || Lecame terme FF ner nese x | reno senesuir zero. | [Fe ——]rwonma cauiren “ne ee ee GF j BLS sraex owen» ——ecuat wooe rere ey Eee x econ Programming Model RG50X, R651X R6500 Microprocessor (CPU) ADDRESSING MODES The 6500 CPU family has 13 addressing modes. In the following discussion of these addressing modes, a bracketed ‘expression follows the ttle of the mode. This exprassion is tho term used in the Instruction Set Op Code Matrix table (later in this product description) to make it easier to identily the actual addressing mode used by the instruction ACCUMULATOR ADDRESSING [Accum]—This form of ‘addressing is represented with a one byte instruction, implying fan operation on the accumulator. IMMEDIATE ADDRESS [IMM]—In immediate addressing, the second byte of the instruction contains the operand, with io further memory addressing required. ABSOLUTE ADDRESSING [Absolute]—in absolute ‘addressing, the second byte of the instruction specifies the eight low order bits o! the effective address while the third byte specifies the eight high order bits. Thus, the absolute address- ing mode allows access to the entire 64K bytes of addressable memory ZERO PAGE ADDRESSING [2P]—The zero page instruc tions allow for shorter code and execution times by fetching only the second byte of the instruction and assuming a zero high address byte, Careful use of the zero page can result in signi ‘cant increase in code efficiency. INDEXED ZERO PAGE ADDRESSING [ZP, X or VJ—This {orm of addressing is used with the index register ana is fetorred to.as "Zero Page, x” or "Zero Page, Y". The ettective address Js calculated by adding the second byte to the contents of the index register. Since this isa form of "Zero Page” addressing, the content of the second byte relerances a lacalion in page 220 ‘Additionally, ue to the ""Zero Page" addressing nature ofthis, ‘mode, no cerry is added to the high order eight bits of memory and crossing of page boundaries does not occur. INDEXED ABSOLUTE ADDRESSING [ABS, X or YJ— This form of addressing is used in conjunction with X and V index register and is referred to as "Absolute, X" and "Absolute, Y.” The effective address is formed by adding the contents of X or Y to the address contained in the second and third bytes of the instruction. This mode allows the index register to contain the index oF count value and the instruction to contain the base address. This type of indexing allows referencing of any loca- tion and the index may modily multiple fields, resulting in reduced coding and execution time IMPLIED ADDRESSING [Implied]—in the implied adiross- ing mode, the address containing the operand is implicitly stated in the operation code of the instruction. RELATIVE ADDRESSING [Relative]—Relative addressing is used only with branch instructions and establishes a destina- tion forthe conditional branch. ‘The second byte of the instruction is an operand. This operand is an offset which is added to the program counter when the ‘counter is set at the next instruction, The range of the offset is ~128 to +127 bytes. INDEXED INDIRECT ADDRESSING [(IND, X)}—In indexed indirect addressing (retered to as (indirect, X), the second byte ofthe instruction is added to the contents of index register X siscarding the cary. The result of this addition points to a ‘memory location on page zero which contains the low order byte of the effective address. The next memory location in page 2670 contains the high order byte of the effective address. Both ‘memory locations specitying the etfective address must be in page zero. INDIRECT INDEXED ADDRESSING {(IND), Y)]—I0 inrect indexed adéressing (refered to as (Indirect), Y), the second byte of the Instruction points to a memory location ia page zero. The contents of this memory location are added to the contents of index register Y. The results the low order byte of the effective address. The carry from this addition is added to the contents of the next page zero memory location, 10 form the high order byte ofthe effective address. ABSOLUTE INDIRECT [Indirect]—The second byte of tho instruction contains the low order byte of a memory location ‘The high order eight bits of that memory location are contained Inthe third byte ofthe instruction. The contents ofthe fully spect fied memory location are the low order byte of the effective ‘address, The next memnory location contains the high order byte of the effective address which is loaded into the sixteen bits of the program counter. (JMP (IND) only) R650X, R651X R6500 Microprocessors (CPU) INSTRUCTION SET OP CODE MATRIX “The following mari shows the Op Codes associated withthe numberof nstuton bytes, and the number of machine cycles 6500 family of CPU devices, The matrix denies tho hex: asaocated wih each Op Code. Also, ror to the instruction sot decimal code, the mnemonic code the addressing mode, the summary for adcttonal information on these Op Codes Mo 1 ek 8 s 6 7 8 ¢ A 8 c¢ bo fe F 2 PamTomy | om | a | AA] ASL | Ci mpeg (40.0) | zm | 'o nes | 8s ° eee Yale's jae | Pe | TP fms om PA j / Lame | ani | aasre|aasx| | + Paley Les mio | RC an | me | ro ce | sos | 08 | As 2 | [es | es Aree | [axe [Ao “aN | RO | | zeox | amx ss. | a8 2 | rales ses Teor Pca gar gon | ak | ele as | ies | Ses | fe | Pats) Pal ae | oe | [ere eon] ven bart TP eon Tn 5 | ats mY sex | ax | wefan) | s ere le llavailiaie! Se |S mrs] x00] Troe | Ron “we | ne | RR 6 | meres ew | | | wee 485 | ABS . | um [i's PELs |e i 7 Tse Ten ro , | tex | are abeox |b 7 Lees Pe |S ar ae Pe] sr] oa | ore . pe aos | 508 | Ses . jesizolaa aajaaloe sty | sta | six | ‘STA orev] | Lax ax | ay ass . ze | 26 2sizaiea 23] or | wa tor tore | uo tox] tox 4 iat Jeno ee | ae nos | ses 4 rene 2s gales) ate or Tov aoe Pe] a | ioe 8 Rama | wx mx| my esx] aB6-x | ano. ° as peizelee De See cor 1 ea | bee cev | enw oe ¢ ae ae | te « 7 cme | DEC = ° | | ame] ae ° PR Pa ore | ae | we € . , wx | mx! F Pe 7a eee ener Bees eeeree ° “Aa 10 page boundary is costes “Ade 119 Nil branch occurs Wo samo page: aK | —oP cove ‘206 2 19 Nil branch occurs fo aaerent page | imotes | —Adoressing Mose 17) | —tnsitucton Bytes: Machine Cyctes 10 R650X, R651X R6500 Microprocessors (CPU) INSTRUCTION SET SUMMARY R650X, R651X R6500 Microprocessors (CPU) R650X CLOCK TIMING R65XX READ WRITE TIMING R650X, R651X R6500 Microprocessors (CPU) AC CHARACTERISTICS Resi ReBOR Rano (oti) (amie) em) Characteristic Symbot_ [win] Max | Win] Max | Min | Max | Unw FRESOK CLOGK THING (boek Oye Tne Tee wo [ o [ os | w | os | 1 | os #0. Low Pulse Wah Toe wo | — | | — |. - [ro 90 0M High Pulse Width Tre Ce ee oe UN) ise and Fa Tine? Tro Tro =e ee #1 (GUT High Pulso Wah Tron wo | - ps >] fs fp ps 2 OUT) High Puce Wie Toone | - pe > pep ps Belay Betwoen #1 (OUT) and @2 (OUT) | To ° = ° = o = [ss 41 (OUT, #2 (OUT) Riso od Fal Te = pas p> fas ffs pw Time’? RESIK CLOCK TMING Cioc Gye Te Tove 1] | [0 [os | | 90) igh Pulse Wie [Few @ [pes [os pp 2h igh Pace With Towne ~o]|-|=s|{[-|;"l—-lf-. ‘alay Botweon 61 and 82 To ones |e (om |e on ee 01 (A, 92 WW) Fee ana Fan Tina’? | Ta Tr ~[es [-f,*» |- [*s [Te 65K READWAITE THING FAV Sop Tire Tove ==) )- De ps PA Fo Tire i am wo | - |» | - | * | — [= ‘ass Soup Tne Troe es a “acs Hold Time Ta. EJ = 30 = 15 =| oe ead Aecoss Tine Toes = free [= 0 od Data Sap Time Tow wo | - |» |- |» |-f* ‘eed Data HS Time [oe w | |] - | [ps [Wie Dota Soup Tino Twos =e ee Wite Date Hol Tire Thee »|- t= )- |= p- fe SWC Haid Tre Tee Se ea a DY Setup Time Trov wo | — 30 = 6 = [as ‘SO Setup Tene Teo ce 30 = s = [os ‘SYNC Seip Time Tow —[p# >- [« [— [0 [= Noes: {. Loecs: All output except clocks = 1 TTL + 120 pF. Clock outputs = 1 TTL + 90 pF 2 Measuted between 0.8 and 2.0 pons on wavolorm toad ‘3. Measured between 10% ard 90% pons on wavelrms, ‘4 "ROY must reve awich states within Fay 0 end FB 8 R650X, R651X 6500 Microprocessors (CPU) EXAMPLE OF TIME BASE GENERATION FOR R6S02 1K A) | reso | Poofac on ou " 13K von [7.06 | pase + Ot 20m} —> 2 (ome mie “CRYSTAL: CTS KNIGHTS MP SERIES, OR EQUIVALENT R6E50X, R651X R6500 Microprocessor (CPU) ABSOLUTE MAXIMUM RATINGS* _ Parameter | Symbot Value Voit Sano vonage {Vee _[ 2931 «78 | vee Tet VoRage Va | -0810 +70 | vee Operating Terpeaie Range | Ts °C | Commercial ' | Indi! a0 +e |_| [Bioege Tenporaie Te Lose rio [oe OPERATING CONDITIONS Parenter Symbol Vous Say vorage “Vee av 36% Tengeratue Range [Th Commerc orc +70¢0 wea a6 0 156 DC CHARACTERISTICS “NOTE: Stresses above those listed may cause permanent ‘damage to the device. This s a stress rating only and functional ‘operation of the device at these or any other conditions above those indicated in the other sections of this document is not Implied, Exposure to absolute maximum rating conditions for extended periods may affect device reliability. (og = 5.0V £5%, Veg = 0; Ta = T.t0 Ty, unless otherwise noted) Parameter ‘Symbol _|__ Min. Type Max. “Unit! | Test Conditions: Input Figh Votiage Vn v | Loois ~ Vee oun) = Vee. 94 0h), 62 0n) =_| Nee #025 input Low Votage Va v ‘Logie | - 08 600,94 ON 82) = | oa ‘pit Leakage Cure tw TA | Vy = OV 5250 Logie (Exe! ROY, 80) - - 25 | vow ov 62 (a9. 92.0N) = = 100 60 «ny _ : = = 10 input Leakage Current for Three State Ortt hs: A | Vm = O4V10.2.4V 00-97 ae S - 20 Vee = 5.250 ‘utput High Vatane Vow V [how = = 10004 | 'SYNC, DO-07. AO-A1S. Ri. 61 (OUT), 62 (OUT) ise | - | Voo= a7ev "| ‘Output Low Voriage = | vo | V [how = .8 me SYNC, 00-D7, A0-ANS, RA, 81 (OUT). 82 OU) | = - 1 Vere 475 Power Dissipetion TP. mi ane 2 Miz ! = «50 700 Sue | = 500 0 Gepaciance ¢ [pF | Voc = 0v Logie on . = 10 Var = OV o-o7 2 = | 13 Nie AO-A15, RA, SYNC Cour 2 |S 2 Th = 25°C sum) Bonn, = = 15 | 108) cor . 20 50 62 40) ce = 50 20 Wotes: ral uns are drect current (de) oxcopt for capactance ‘and NM require 3K pullup resister. 3 4493 (N) and 82 (IN) apply Yo FESI2, 13, 14, ng 15; #0 (IN) applios Yo ABSC2, 03, 04, 05. 06 and 07 i 5 Typical values shown fot Vec = §.0V and T, = 25°C. 2. Negative ign incicstas outward current Now. postive Insicates inward Now. 8 WORLDWIDE HEADQUARTERS Rockwell Senizonductor Systems S31 Jamboree Read, PO.bac Newport Beach, CA 9268-8902 Phone. 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