e 9 olf & yl or 0 School of Electronics Engineering, VIT Vellore Programme: M. Tech. VLSI Design £ é Subject: Computer Aided Design for VLSI (ECES019) wt an ' Examination: CAT1, Slot: D2 oy wee Date: 16.08.2018, Time: 2-3.3C p.m., Total Marks: 50 wh os the big-0 notation. b). Determine the correctness of the following inequality f(a) = 6n°/( 1+ log n) = O(n’) Use the Kerighan-tin 20m algorithm to equi-partition the weighted graph of the nodes A-F such that each block contains 3 nodes. | ae" 8 equal sized blocks C1-C8 Starting with an initial partition A =(C1-C4) and 10M and the netlist: __ B= (C5-CB) use simulated annealing to find the NA = (C1, C2, C4} with wi = 2 partition with the lowest cutcost. The N2 = (C2, C4, C6, C7} with w2=2 simulacion parameters are T = 10, alpha = 0.9 NB = (C3, CB} with w3 = 1 MM = 3 and beta = 1. Terminate the simulation (C4, C1, C3, C5} with w4=3 after T=9 and before Tless than 9, NS = (C5, C1, C3, C7,CB} with w Use the following set of random numbers and (C6, C5, C7} with w6 =1 swapping sequences: (C7,C1, C3, C5, CB} with wi L077, (C1,C5) (C8, C6, C7} with ws 0.381, (C2, CB) 0.546, (C5,C7) 0.563, (C2, C3} 0.95, (C3, C7) 0.972, (C6, C8) 8 Given thescngHoorpian determine the sequence pair tom st w un . & y? ead@ i dead) @ ea @ a a a3 as School of Electronics Engineering, VIT Vellore Programme: M. Tech. VLSI Design Subject: Computer Aided Design for VLSI (ECES019) FS 2018-19: CAT1 Examination, Slot: D1 Date: 16.08.2018, Time: 9.30-11.00 a.m., Total Marks: 50 Given the cartesian points a(2,4), (4,2), c (3,3) and dl5,2). Draw: i) a rectilinear 10m Prana Wee (8ST) andi) a rectilinear Steiner tree, Are the trees minimum spanning trees? ' Use the Kernighan-Lin algorithm to equi- Partition the weighted graph of the nodes A-F such that each block contains 3 nodes, n 3 20M L 20 10, 4, “ah ca veal 20 v ze oO 6 ee ores vw fire ice sccm: mene eee ae ; Vertical Constraint Graph (vec). | A iFten blocks C-Cip are to be equi-parttioned then determine the total number of 10m ways in which the blocks can be partitioned. Express in the big-O notation the order Of the computational complexity What i the cass ofthe problem of finding the Partition with the lowest cut-cost? What generic class of algorithms can be used to find the partition with the lowest cost?F-2U- dH}. 2G 5 3-9 -deh 24) Ser tnwro 2 why wr FOO (844 (OVS tae 2a BE be Ws-s=4 Xo'N9 B- 8-1-0 7% 9 *b-1- € 9G Oi= B-Fet ens EG bay Gry s 2G v- 2-6-1 > 3G h- 2 9" Geter 2% e FBG 22g oi 7 O1- 0 2 ag We sad - FeV ag tis(ayp- Fen 7 wh beer een 7G)School of Electronics Engineering, VIT Vellore Programme: M. Tech. VLSI Design Subject: Computer Aided Design for VLSI (ECES019) Examination: CAT2, Slot: D2 Date: 26.09.2018, Time: 9.30-11.00 p.m., Total Marks: 50 Quadratic Placement 15 Given:l) A placement with three fixed points p1(75, 200) p2(100,0) and p3(250, 350) and 2) Three fixed blocks a,b,c and 3) the nets Ni, N2, N3 and N4 such that N1(P1,3,b), N2(P2,b,c), N3(a, b,c), and N&(c,P3). Use quaaratic placement to find the co-ordinates, of the blocks a,b,andc. Assume all the nets have weight unity, te te Dikstras Algorithm tofnd the minimum cost path rom the source node S-k 20a? tothe target node T= 0. ‘J S p61) @m (a2 62) C'S” @” @ (2.2) (42) (13,16) (8.2) Ee Leh) 2 Oj Gwinn (3.6) (3,8) ee” ee oo (20,13) (a (0243) @5) : 2 2 138g (2 5 (2.2) @ 2en Qe te aw) 25) (ea) (2) ee” @ és) (43) @ Left-Edge Algorithm a5 Given achanne! with the fotowing pin connection (om et to eght) TOP=14000£0C00€ scoo|and BOTTOM -[9F DADE ODE0000G—) A1_Find Sol For coldmns 2-0 and the minimum numberof routing ace DY Draw the HCG and veG 1 Use the left edge algorithm to route ths channel, Draw the channel withthe fully routed netsFinal Assessment Test - November 2018 Course: ECE5019 Computer Aided Design for Vist Class NBR(s):1169 Time: Three Hours Slot: 014101 Max. Marks: 100 General Instructions : Graph Sheet to be provided ‘Answer ALL Questions . (100 Marks) [20] ‘The weight of the edges are as follows: AB=1, AC=3, AH=6, CG=1, CH=5, BH=2, Bl=1, CF=6, Fist, Fei DE=2, Di Gle1, Hi=3 and U=4 Given the floorplan below generate: the slicing tree, the polish expression and the sequence pair; <*> [10] and , 8 c A D E F 6 H Page 1 of 2Given three blacks a, b, ¢ along with their size options (width x height): a(1x3) and a(3xt); b(2x4) and (4x2) and ; c(1x4) and c{4x1). Determine; a) the shape functions for each blocks a, b,c b) the minimum area of the top-level floorplan using the Polish expression acVbH ©). the shape function of the top-level floorplan Given:1) A placement with three fixed points p1(50, 250) p2(150,0) and p3(250, 300) and 2) Three fixed blocks a,b,c and 3) the nets N1, N2, N3 and N4 such that N1(P1-a,P1-b), N2(P2-b,P2-c, b-c), N3{a- b- c), and N4(c-P3). Where Ni(P1-a, P1-b) block b, The weights of the nets are: W(N1) = 2, W(N2)= 1, W(N3)= 4, W(N4) = 3. Use quadratic placement \dicates that the net N1 has connections: P1 to block a and P1 to to find the co-ordinates of the blocks a, b and c. Use the greedy channel router algorithm of Rivest and Fidducia, to route the channel: TOP = (54030214030 10203001}, Bottom = {0143 0.80505020403120}. Where 0 indicates no connection. Given the nets on each side of a switch box, (ordered left-to-right) BOT = {H B B H G00}, TOP = {CCEHF DO} (ordered bottom-to-top) LEFT = (BH ACEC}, RIGHT=( AOD FG 0} Route the switchbox using the Luk’s moc cation of the greedy channel algorithm of Rivest and Fiduca. For each column, mark the routed nets and their corresponding tracks. Draw the switchbox with all the nets. Given the following locations of a clock source SO and eight sinks S1-S8: $0 (7,1), $1(2,2), $2(4,2), $3 (2,12), S4(4,12), $5(8,8), S6(8,6), $7(14,8), $8(14,6) a) Draw the clock tree generated by MMM b) Draw the clock tree topology generated by MMM ¢) Calculate the total wirelength (in terms of units) and the clock skew using the linear delay model. {as} [15] (15) {15} [10] Page 2 of 2an a2 as School of Electronics Engineering, VIT Vellore Programme: M. Tech. VLSI Design Subject: Computer Aided Design for VLSI (ECE5019) FS 2018-19: CAT1 Examination, Slot: 01 Date: 26.09.2018, Time: 2.00-3.30 p.m., Total Marks: 50 Linear Ordering Algorithm: For the netlist with five blocks a-e and six weighted nets N1-N6, determine the linear ordering that minimizes the total wirelength. Let the starting block bec, Place the block g C first in the left most position. Draw the resulting placement. The nets are: Na(a,b)=2, N2(a,e)=4, N3(a,b,c}=3, NAla,d)=5, N5(b,,e)=4 and N6(dhe)=3 ae Note: The nets are weighted. Place the block c first in the leftmost position, Given a placement of blocks on 2 chip as shown below. Find a Hamiltonian Path through the blocks and then route the power and ground networks. GND Given the pin points p1(0,3), p212,3) 0314.7), paTB), 95190), BB{O), BITS.) and, 98(0.5). Construct a heuristic Steiner minimum tre using the sequential tejner Tree Heuristic. TOP=[00.CD BB AO] and BOTTOM =D D0C COB Al al Find S{col) for columns a-h and the minimum number of routing tracks. b) Draw the HCG and VCS Ps Use the dogleg left edge algorithm to route this channel. Draw the channel with the fully routed nets. Gu» BS ~ TL be ot) @ ?a 4, Dogleg Left-Edge Algorithm fey ® Given a channel with the Flowing pin connection (fom eftoright) APE Ps isFinal Assessment Test - November 2018 Course: ECES019 ~ Computer Aided Design for VLSI Class NBR(s):1170 Slot: D2#TD2 Time: Three Hours Max. Marks: 100 General Instructions : Graph Sheet to be provided ‘Answer ALL Questions (100 Marks) ‘The weight of the edges are as follows: AB=1, AC=3, AH=6, ‘Al=4, BD=4, BF=3, BG. CG=1, CHS, Cl=3, DE=2, DG=3, Dis sa , BH=2, Bi=1, CF=6, EG=4, EH=6, El=9, FG=3, FH=2, Fi=1, Fl=2, Gla 2. Given a placement of blocks on a chip as shown below. Find a Hamiltonian Path through the blocks and xg} then route the power and ground networks. 'e leftmost position. Draw the resulting placement. The nets are: N1{4-b,e), Need), N3BCA.N, NA (3460), NS (cf), NEla,b,,d,e,), The weights of the nets are W(N4) = 2, W(N2) = 3, ‘W(N3) = 1, W(NA) = 1, WINS) = and, W(N6) = 5 Page 1of24, Given a channel with the following pin connections (from left to right) oe stettcc 5 20550640] and BOT =[2036420100464035060205) Ro} Find S(col) for columns a-v and the minimum number of routing tracks. b) Draw the HCG and VCG Use the dogleg left edge algorithm to route this channel. Draw the channel with the fully routed nets. Given the nets on each side of a switch box, [15] (ordered left-to-right) BOT = {0D G F AO}, TOP = {D BEC AO} {ordered top-to-bottom) LEFT = {0 G E C D0}, RIGHT=(0 B FAG 0} Route the switchbox using the Luk’s modification of the greedy channel routing algorithm of Rivest and Fidducia. For each column, mark the routed nets and their corresponding tracks. Draw the final switchbox with all the routed nets. ‘Given the following locations of a clock source S» and eight sinks Sy [20] a) Draw the clock tree generated by RGM. Use the linear delay model when constructing tapping points. Let each sink have no delay, ie. ti(5)=0, where 1 <=i <= 8 b) Draw the clock tree topology generated by RGM ©) Calculate the total wirelength (in terms of grid units) and the clock skew using the linear delay model. $0 (7,1), $1(2,2), $2(4,2), $3 (2,12), $4(4,12), $5(8,8), 56(8,6), $7(14,8), $8(14,6) eee giabus Page 2 of 2Final Assessment Test - November 2018 Course: ECESO17 Digital Design with FPGA Class NBR(s):1154 Slot: F2, Time: Three Hours Max. Marks: 100 PART ~ A (10X 5 = 50 Marks) Answer any TEN Questions *ssignment were used? Compare it with the seme code in a combinatorial block, 3. Draw the hardware logic that get infers for the following code module example (clk,CS,NS); input clk; input [3:0] cs; output [3:0] Ns; reg [3:0] NS; plays @ (clk or Cs) begin integer temp; if (clk) tempe cS; NS=temp; end endmodule 4. Write behavioral Verilog code for 2:4 decoder circuit using for loop. 5. Consider the data p= 4’b000x q a) yR&s; b) y= ree ao yepta d) y=ras; ©) ¥= (263},2{r),2’b19} & Define half-adder and fulladder as function and write behavioural Verilog code for 64-bit adder using them. "b2112 r= "60101 s= 4'b1100, Obtain the output for the following. 7. Using the following input wave form for input a, plot the different wave forms generated from the following statements. Explain the differences, Why are there so many ‘ways to describe a circuit? The statements: ot #2 (b, a}; assign #2 always @(a) #2b= always @(a) b= #2~a; Page 1 of 410. 1. 12. 13. snows et © #2b always @(a) be= #2"a; = a 8 12 16 20 time Write behavioral verilog code to count the number of occurrence of prime number from 1 to 1000, Use only ifelse construct. Design an FSM state graph that has an input w and an output z. The machine is @ sequence detector that produces z=1 when the previous two values of w were Oi or 10; otherwise 2-0. Write verlog code by considering FSM coding guidelines. Draw the FPGA Generic Architecture and brief about each component. Do the two code fragments below do the same, thing? If not, how do they differ? _ // Fragment A. S7 5 es if(foo>bar)x=x+1;elsey=y+t; Ye | wed uel 1/ Fragment B. ° case ( foo > bar) - c Axexth ¢ default: endease a SI t u yeh Act Write a User Defined Primitive definition to realize the output logic of S-R Flip Flop. Consider rsing edge clock and clear. PART ~ B (5 X 10 = 50 Marks) ‘Answer any FIVE Questions Draw the state graph, state table and wr verilog code to design the control circuit shown in Fig.1 using FSM coding guidelines. Also write the test bench to verify the functionality of the same. The following are the operation to be performed by the control circuit. ‘The contents of R2. are first loaded into R3, using the contro! signals R2out =1 and R3in=1. Then the contents of Ri are transferred to R2, using control signals Rlout=1 and R2in=1. Finally the contents of R3 (which are the previous contents of R2) ae transferred into R1, using RZout=1 and Riin=1, Since this step completes the required swap, we will indicate that the task is completed by setting the signal Done=1- ‘Assume that the swapping is performed in response to a pulse on an input signal called w, which has duration of one clock cycle. Page 2 of 414. 15. w | __,. tout [> ran Control Circuit [-——> aout dock >} nummer con [> aout [— ain Fig. A tachometer measures rotation rate by detecting marks on a disk using photo detectors as illustrated below. In the illustration there are two rings of marks, in this only the outer ring (the one with lots of marks) will be used. As the disk spins the number of marks passing under the disk is counted. At fixed intervals a rotation rate is updated. Write Verilog behavioral description for hardware that determines the rotation rate using the photo detector output and also the test bench. The module has the following declaration: module tach1(rpx,pd,clk); input pd, clk; output rpx;, wire pd, clk; reg [9:0] rpx; parameter freq = 500; parameter marks = 4; Parameter update_interval = 0.5; parameter perwhat = 60; 'nput clk is a square wave for use by the module. Input pd is the photodetector output. itis 1 when a mark is under the photodetector. Output rpx is the rotation rate. Parameter freq is the frequency of clk and marks is the number of marks on a disk. Parameter update_interval is the number of seconds between updates of rpx. For example, if update_interval were 3 then rpx would have to be updated every 3 seconds. Parameter perwhat is the time unit for measuring revolutions, in seconds. If itis 60 then ‘Px should be in revolutions per minute, if itis 1 then rpx should be in revolutions per second, etc. Follow the rules when writing the hardware description, (The rules do not apply to test bench code.) © Do not use multipliers or dividers. © Donotuse delays: #3 You can use event controls: @ (posedge clk) ‘Write Structural level Verilog code for the circuit shown in Fig.2. Also write the test bench such that it display the output whenever there is a change in the output. Page 3 of 4en add_sub |. p Parity Checker Fig.2 16. Draw the state graph and state table to identify the overlapping sequence 11001. Write behavioural verilog code by adhering FSM coding guidelines. Also write the test bench to generate the inputs and display the output whenever there is a change in the output. 17, Write Verilog code to generate multiphase clock signal as shown in Fig.3 using the circuit shown in Fig. 4 using the following, a. Using behavioral level description b. Using task definition te AAPL Fig.4 18. Draw the architecture of Cyclone IV FPGA and explain it’s modes of operation. eee Page 4 of 4Vi Vellore Institute of Technology @ SCHOOL OF ELECTRONICS ENGINEERING Continuous Assessment Test - I Course: Digital Design with FPGA. Course Code: ECES017 Max. Marks: 50 Max. Time: 90 Min Branch: M.Tech, VLSI Design Slot: FL _AC List out the syntax errors in the following verilog code 5] > module 12mux (1.3.9); input [1:0] 1; fl ouput ys] Spebbiny wn Cee! spiny whe assign Y= (~s & I[0]) | (S & I[1]): endmodule; 26 We are often sloppy with the term wire in verilog. Actually verilog has several types of [10] nets, wor, wand and wite is one of them. You can actually do logic on certain types of 3 | nets. Write a description of a half adder that only uses buffers and invertors these are gate + primitives and do all ofthe logic on the nets. Use the module header below. module wired Add(output sum, carryout, input A, B); Seo > warileg tuk dow Hhak ° myo Tire the eae Tor half adder as a de above using wand and wor. b. Change all net types to “wire” but keep everything else the same. c. Explain the difference between part a and b. _D~ 4 losie circuit which has two control inputs and two data inputs. The system performs [10] addition when control input is 0, subtraction when control input is 1, 1's complement of inputs when control input is 2 and 2°s complement of inputs when control input is 3. Design the logic circuit and write data flow level Verilog code. 0 Page 14, Write Structural level Verilog for the following logic circuit (15) Halt Halt Subtractor Subtractor s Parity 4 Maltiplexer Checker 4 v Xoe 5. For each of the parts below write verilog code that implement the functionality shown in [10] the schematic. Your verilog code just has to produce the same values for its outputs ~ it doesn’t have to replicate the schematic logic gate-for-gate. Be sure to include the appropriate declarations for any wires used in your code. a. Accircuit that tests an 8-bit value to see if it’s zero. b. A logic function implemented as a multiplexer-based lookup table. a8 (ey | 00 eps shure trv code oO wo [77 Zot an | Ax (om) > Lone Sebirtien " (AB) Se Page 2.SCHOOL OF ELECTRONICS ENGINEERING CONTINUOUS ASSESMENT TEST - I Course: Digital Design with FPGA Course Code: ECE S017 Max. Marks: 50 Branch: M.Tech (VLSI Design) 1. Fill in the table showing the values for the four registers at the given times. Legal (51 answers are 0, 1, x, z, and indeterminate. <= #1 1°60; qa Pol; ‘bL; wait ( "00; "60; a HOT; end Signal | Value at the end of time 0_| Value at the end of time 1 4 o eS —_ jndates. ry) 4 s Fncdet oO tt FA module assgQ; reg [15:0] a, bs initial List the changes (values and times) to a and b in the module below. t:0 arly be tea ar 2 bs bee asl £23 as it b&b dbo Ee RPO4 3; bad bem b= #0 6; ba; #20; end endmodule Write behavioral verilog description for full subtractor by using function call for 15] obtaining it’s outputs Write behavioral Verilog code to count the sequence 0001, 0010, 0100, 1000, 0001, {10} 0010, 0100..... use if-else construct only to realize the logic. Also write test bench to generate clock with duty cycle of 10 tu and display the output in decimal form. Re-write the module in behavioral form. The delays can be assumed to be inertial [10] delays. module expl_str(x,y,4b,0); input a, b, ¢; output x, y3 wire a, b, 6X, ¥F wire na, nb, nc, 13, 15, 16; not nI (naa); not n2(nb,b); not n3(nc,e); and #1 al (t3,na,b,0)3 and a2(S,a,nb,0); and a3(t6,a,bne); or o1(x3,16); or #3 02(7,a,15)5 endmodule Write Verilog behavioral description so that it operates as follows. 5} Compute 32-bit output eq_time so that itis the number of consecutive positive edges of input elk for which 32-bit inputs siga and sig remain equal. The counting should start on the first positive edge of elk after siga becomes equal to sigh; the count starts at zero at the moment they become equal, and while they remain equal the count is incremented at each positive edge. The count should go back to zero at the first positive edge of elk after siga becomes unequal to sigh.The count goes to zero even if siga and sigh become equal again before the posit ive edge. Write the test bench to verify the same. = Page 2 ——_____—@ Final Assessment Test - November 2018 (y VAT course: eceso17 —~ igitat Design with rP0a 3 WoreinsiateoTecknaieg Class NBR(s): 1153 Slot: F1 a Time: Three Hours Max, Marks: 100 PART ~ A (10 X 5 = 50 Marks) Answer any TEN Questions Explain the port connection rules and data type deciaration with the help of an example. Why a blocking assignment should be used for combinational logic and what would happen if @ non-blo. assignment were used? Compare it with the same code in a sequential block. Draw the hardware logic that will infer for the following code. ‘module multiphase (clk,A,B,C,E}; input clk,A,B,C; output E; regeE,0; always @ (posedge clk) Eee D1G always @ (negedge clk) D<= A&B; endmodule Write behavioural Verilog code for shift register with following specifications. Shift Load Register Operation 0 0 No Change 0 1 Load Parallel Data 1 X (don’t care) | shift Right Consider the input a=4'b0010; b=4’b1011; c=4’bixd; d= 410d; Write the output for the following? yr ace2; yeallc; © yea nb; ¥= {2{a},3{d},101); y= {a,c,d}; ye cR&e; Define divide by 2 counter and divide by 4 counter as task and write behavioural verilog code to divide the given clock by 2 and 4. Page 1 of 410. 1. & @ Using the following input wave form shown in Figure 2 for input b, plot the different wave forms generated from the following statements. Explain the differences. Why are there so many ways to describe a circuit? The statements: not #2 (a, b); assign #2 a=“b; always @(b) #a=b; always @(b) a=#2~b; always @(b) f2a Fig. Explain about 1/0 Structure of generic FPGA device. Design an FSM state graph that has an input w and an output 2. The machine is a sequence detector that produces 2=1 when the previous two values of w were 00 or 11; otherwise 2=0. Write verilog code by considering FSM coding guidelines. Write behavioral verilog code to count the number of zero’s in the incoming serial data. Use only if-else construct. Explain how each of the three statements below behaves differently with unknown values. In particular, explain what has to be unknown and how the results of each statement are different. Statement:1 mi=a>b?c:d; Statement:2 if(a>b)m2= Statement:3 ; else m2 = dj case(a>b) 1:m3=c; default: m3 = d; endcase Write a User Defined Primitive defini clock and clear for the logic. ion to realize the output logic of J-K Flip Flop. Consider rising edge of Page 20f4PART~B (5 X 10 = 50 Marks) Answer any FIVE Questions 13. A sequence generator is to have four binary output designated W, X, Y, Z. They have to follow cither of tg seayenes depending onthe vale of Belean arable I, the Sequence tobe follows 00 1100,0160,0110,0010,0611,6001,1081,1000. tf, yo Sg the sequence to be followed is 1001,0001,0011,0110,0100,1100,1000,1001. Where W is the MSB and Z is the LSB, Draw the state graph, transit Write behavioral verilog code for the same. n table and design using Jk Flip Flop. 14. Write behavioural verilog description and test bench of a FIFO-like module which has a 3-bit data input, in; a 7-bit output, out; 1-bit inputs inclk and outelk; and 1-bit outputs full and empty. The module operates like a FIFO (first in, first out) except that the width of the data input and output ports are different. It reads data 3 bits at a time (on a positive edge of inclk) and outputs 7 bits at a time (consisting of data from two input words plus one bit of a third). Unless the module has less than 3 bits of space left, on a positive edge of inclk the value on in is stored. The oldest 7 bits stored by the module always appear on output out. On a positive edge of outelk the oldest 7 bits are removed and the output displays the next. 7 bits. Output full is 1 if the module cannot accept another 3 bits of input and is 0 otherwise; output empty is 1 if the module is empty and is 0 otherwise. Use parameter storage for the total number of bits stored by the module. ‘An example of the module operating is shown in the timing diagram of fig.2 below. inet Le LPI in oot — 610 ort Hoo tor fx — 1 fo00 ~~ joo 010 —font 00 out | 1 lama — cit = oss joras yrorono1 forgo “ietttior | pos ‘a _ A m empty = eee eee tribe r ee tee ei ba Q 10 2 Fig.2 15. Write Structural level Verilog code for the circuit shown in Figure 3. Also write test bench such that it display the output whenever there is a change in the output. mo noe no Jo te Page 3 of 4oO 16. Draw the state graph and state table to identify the overlapping sequence 10101, Write behavioural Verilog code by adhering FSM coding guidelines. Also write test bench to generate the inputs and display the output whenever there is a change in the output. 17. Write Verilog code for n-Bit universal shift register shown in Fig.4 using generate Loop statement. Also write test bench such that it display the output whenever there is a change in the output. sion 3} ena tt x) ten in ssc ‘ral wo eo a ee AT it ipa ipa Up Lp ay ea ant ae] | [Tene vet | E f Y ont) sou Ll Parallel data input Right shift i ll i A Left shift serial input serial input reset —pdcue 2 © BA ste — spode control otk PK Oy On Op Sf Wt Parallel data output Fig.4 18. Draw thé architecture of Cyclone Il FPGA and explain the different modes of operation. od Page 4 of\ a Final Assessment Test - November 2018 ve V I I Course: ECE5017 Digital Design with FPGA * Winginti theming Class NBR(s):1254 Slot: F2 = Time: Three Hours Max. Marks: 100 PART —A (10 X 5 = 50 Marks) ‘Answer any TEN Questions Can | use multiple assign statements targeting the same wire? Justify your answer with an example. Why a nonblocking assignment should be used for sequential logic and what would happen if a blocking assignment were used? Compare it with the same code in a combinatorial block. Draw the hardware logic that get infers for the following code module example (lk,CS,NS}; input clk; input [3:0] cS; ‘output [3:0] NS; reg [3:0] NS; always @ (clk or CS) begin integer temp; if (clk) temp= CS; Ns=temp; end endmodule a Write behavioral Verilog code for 2:4 decoder circuit using for loop. 9 Consider ‘the data p= 4’b000x q= 4’bz11z r= 4’b0101 s= 4’b1100. Obtain the output for the following. a) y= &s; b) ys reed od yepta d) y=r4s; e) y= {2{s},2(r},2’b10} @ Define half-adder and full adder as function and write beha ural Verilog code for 64-bit adder using them. Using the following input wave form for input a, plot the different wave forms generated from the following statements. Explain the differences. Why are there so many ways to describe a circuit? The statements: not #2 (b, a); assign #2 b= ~a; always @(a) #b="a; always @(a) Wa; Page lof 4