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Course - Uvm Debug - Session2 Uvm Connectivity Debug - Tkiley

The document discusses debugging UVM connectivity by viewing UVM component connections using a schematic viewer, viewing virtual interfaces in the source code and waves, and browsing the design hierarchy to find the actual interface connected to a virtual interface.

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Sujay M
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104 views8 pages

Course - Uvm Debug - Session2 Uvm Connectivity Debug - Tkiley

The document discusses debugging UVM connectivity by viewing UVM component connections using a schematic viewer, viewing virtual interfaces in the source code and waves, and browsing the design hierarchy to find the actual interface connected to a virtual interface.

Uploaded by

Sujay M
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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UVM Debug

UVM Connectivity Debug

Tom Kiley
Verification Technologist

info@verificationacademy.com | www.verificationacademy.com
© 2017 Mentor Graphics Corporation
Session Overview

• Viewing UVM Connections


• UVM Schematic Viewer
• Viewing Virtual Interfaces
• In source drop down
• Wave window
• Find the actual interface for a virtual interface
• Browsing the design hierarchy

© 2017 Mentor Graphics Corporation


UVM Connectivity
• The UVM is composed of a static component hierarchy that uses FIFO’s
to pass information (sequence items) between them

• The UVM is connected to the DUT with Virtual interfaces


Analysis Ports

Agent
Monitor

FIFO’s
Virtual Interface DUT

Sequencer Driver

© 2017 Mentor Graphics Corporation


UVM Schematic Viewer
• Visualizer™ Debug
Environment UVM Schematic
of a simple Agent

• Agent contains sequencer,


driver, and monitor plus
analysis ports

• The schematic shows both


the FIFO connections and
the virtual interface
connections

© 2017 Mentor Graphics Corporation


UVM Schematic Viewer
• UVM Schematic of a simple
Agent with missing
connections

• Notice that the


seq_item_port is not
connected to the sequencer

• The missing connection will


cause a fatal simulation
runtime error

• Fatal errors can be very


difficult to debug

© 2017 Mentor Graphics Corporation


Virtual Interface Connectivity
• User’s commonly want to go to the instantiation of an actual interface

• It is not obvious what interface the virtual interface points to

Analysis Ports

Agent
Monitor

FIFO’s
Virtual Interface DUT

Sequencer Driver

© 2017 Mentor Graphics Corporation


UVM Connectivity Debug

• Viewing UVM Connections


• UVM Schematic Viewer
• Viewing Virtual Interfaces
• In source drop down
• Wave window
• Find the actual interface of a virtual interface
• Browsing the design hierarchy

© 2017 Mentor Graphics Corporation


UVM Debug
UVM Connectivity Debug

Tom Kiley
Verification Technologist

info@verificationacademy.com | www.verificationacademy.com
© 2017 Mentor Graphics Corporation

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