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NMOS Circuit Analysis Guide | PDF | Mosfet | Electronic Circuits
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NMOS Circuit Analysis Guide

The document analyzes an NMOS circuit by writing the Kirchhoff's voltage law equations for the gate-source and drain-source loops. Solving the equations results in a quadratic equation that has two possible solutions for VGS. Only one solution satisfies the original assumption that the MOSFET is in saturation. Using this solution, the document determines the drain current ID and drain-source voltage VDS. It confirms that the solutions are consistent with the saturation mode inequalities.

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Tim Price
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518 views4 pages

NMOS Circuit Analysis Guide

The document analyzes an NMOS circuit by writing the Kirchhoff's voltage law equations for the gate-source and drain-source loops. Solving the equations results in a quadratic equation that has two possible solutions for VGS. Only one solution satisfies the original assumption that the MOSFET is in saturation. Using this solution, the document determines the drain current ID and drain-source voltage VDS. It confirms that the solutions are consistent with the saturation mode inequalities.

Uploaded by

Tim Price
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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10/22/2004 Example NMOS Circuit Analysis.

doc 1/4

Example: NMOS Circuit


Analysis
Consider this DC MOSFET circuit:

5.0 V

iD
1K

K = 0. 4 mA 2
V

Vt = 2. 0 V

1K

-5.0 V

Let’s ASSUME the NMOS device is in saturation.

Jim Stiles The Univ. of Kansas Dept. of EECS


10/22/2004 Example NMOS Circuit Analysis.doc 2/4

Thus, we must ENFORCE the condition that:

ID = K (VGS −Vt )
2

Now we must ANALYZE the circuit.

Q: What now? How do we proceed with this analysis?

A: It’s certainly not clear. Let’s write the circuit equations


and see what happens.

From the Gate-Source loop KVL: 5.0 V

0.0 −VGS − (1)ID = −5.0


1K
ID
Therefore, rearranging:

ID = 5.0 −VGS

And from the Drain-Source loop KVL:


1K
5.0 − (1)ID −VDS − (1)ID = −5.0

Therefore, rearranging:

VDS = 10.0 − 2ID


-5.0 V

Jim Stiles The Univ. of Kansas Dept. of EECS


10/22/2004 Example NMOS Circuit Analysis.doc 3/4

Look! We can equate the NMOS device equation and G-S


equation to find VGS .

ID = K (VGS −Vt ) = 5. 0 −VGS


2

∴ 0 = K VGS2 +VGS (1 − 2 K Vt ) + (K Vt 2 − 5. 0 )

A quadratic equation!

The solutions to this equation are:

VGS = 3. 76 V or VGS = −2. 26 V

Q: Yikes! Two solutions! Which one is correct?

A: Note we assumed saturation. If the MOSFET is in


saturation, we know that:

VGS > Vt = 2. 0

Only one solution of the quadratic satisfies this conidtion,


i.e.:
VGS = 3. 76 > Vt

Thus, we use VGS = 3. 76 V --the solution that is consistent with


our original assumption.

Jim Stiles The Univ. of Kansas Dept. of EECS


10/22/2004 Example NMOS Circuit Analysis.doc 4/4

Inserting this voltage into the Gate-Source KVL equation, we


find that the drain current is:

ID = 5. 0 −VGS
= 5. 0 − 3. 76
= 2. 24 mA

And using the Drain-Source KVL, we find the remaining voltage:

VDS = 10.0 − 2.0 ID


= 10.0 − 2(2.24)
= 5.52V

Even though we have answers (one current and two voltages), we


still are not finished, as we now must CHECK our solution to see
if it is consistent with the saturation mode inequalities.

3.76 =VGS >Vt = 2.0

5.52 =VDS >VGS −Vt = 1.76

Both answers are consistent! Our solutions are correct!

Jim Stiles The Univ. of Kansas Dept. of EECS

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