Introducing VCS Basic 1
VCS Basic has all the capabilities and adjacent technologies of VCS
except the following:
• Testbench technology, neither SystemVerilog testbench
constructs nor OpenVera testbench constructs
• Assertions technology, neither SystemVerilog assertions
constructs nor OpenVera assertions constructs
• Coverage technology, no type of code coverage (coverage
metrics) or functional coverage (testbench and assertions
coverage)
• Mixed signal simulation with NanoSim
If your design source code contains testbench or assertions
constructs, VCS Basic displays error messages and halts
compilation.
Introducing VCS Basic
1
The fcovReport utility, for reporting on OpenVera assertions
coverage, does not work in VCS Basic.
The assertCovReport utility, for reporting on SystemVerilog
assertions coverage, does not work in VCS Basic.
The cmView utility, for displaying code coverage results or writing
code coverage reports, does not work with VCS Basic.
Note:
You can use OpenVera testbench constructs if you cosimulate
your design with Vera.
Licensing
VCS Basic requires a different license file from the one used for VCS.
Disabled Compile-Time Options
You should not include the following compile-time options when
compiling your design.
For SystemVerilog Assertions Constructs
-assert -sv_pragma
The -sverilog compile-time option is for enabling the use of
SystemVerilog constructs but using it to enable the use of
SystemVerilog assertions constructs, results in an error condition.
Introducing VCS Basic
2
For OpenVera Assertions Constructs
-cm_assert_hier -ovac
-ova_cov -ova_cov_events
-ova_cov_hier -ova_debug
-ova_debug_vpd -ova_file
-ova_filter_past -ova_enable_diag
-ova_inline -ova_lint
-ova_lint_magellan
For OpenVera Testbench Constructs
-ntb -ntb_cmp
-ntb_define -ntb_filext
-ntb_incdir -ntb_noshell
-ntb_opts -ntb_shell_only
-ntb_sfname -ntb_sname
-ntb_spath -ntb_vipext
-ntb_vl
For Coverage Metrics
-cm -cm_cond
-cm_count -cm_constfile
-cm_dir -cm_fsmcfg
-cm_fsmopt -cm_fsmresetfilter
-cm_hier -cm_ignoreSignals
-cm_instSignals -cm_libs
-cm_line -cm_listSignals
-cm_name -cm_noconst
-cm_opfile -cm_pp
Introducing VCS Basic
3
-cm_resetfilter -cm_scope
-cm_sigfile -cm_stoppropagation
-cm_tglfile
For Mixed Signal Simulation
+ad
Disabled Runtime Options
You should not include the following runtime options when simulating
your design.
For SystemVerilog Assertions Constructs
-assert -cm assert
-cm_assert_dir
For OpenVera Assertions Constructs
-ova_quiet -ova_report
-ova_verbose -ova_name
-ova_filter -ova_max_fail
-ova_max_success -ova_simend_max_fail
-ova_success -ova_cov
-ova_cov_name -ova_cov_db
For OpenVera Testbench Constructs
+ntb_cache_dir
+ntb_debug_on_error
+ntb_enable_solver_trace
Introducing VCS Basic
4
+ntb_enable_solver_trace_on_failure
+ntb_exit_on_error
+ntb_load
+ntb_random_seed
+ntb_solver_mode
+ntb_stop_on_error
For Coverage Metrics
-cm -cm_dir
-cm_glitch -cm_log
-cm_name -cm_tglfile
Introducing VCS Basic
5
Introducing VCS Basic
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