ELEC 3300
Introduction to Embedded Systems
Topic 3
Basic Computer Structure
Prof. Vinod Prasad
ELEC 3300 : Fall 2021 Vinod Prasad 1
Assembler
Instruction Set Architecture
Course Overview
Memory I/O System
More about
Datapath & Control Embedded Systems
Introduction to Basic Computer
Embedded Systems Structure
MCU Main Board
Digital and Analog
Interfacing USART, IEEE1394,
USB, I2C and SPI
Microcontroller Structure
A/D Port
Buffering and
Serial Port Direct Memory Access
CPU
(DMA)
External Memory Port
Memory,
Interfacing to Memory,
External Interrupt Port
Memory Timing
Interrupt and applications
External Timer Port Interfacing LCD
Organization Timer and
Counter Simple I/O Port
Motor Interfacing
In this course, STM32 is used as a driving vehicle for delivering the concepts.
To be covered In progress Done
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Expected Outcomes
• On successful completion of this topic, you will be able to
– Understand the basic system components and operations including
• Data buses
• Address buses
• Control buses
• Memory
– Understand basic concepts of advanced computer architecture
• Memory-mapped I/O
• Bus Protocols
– Analyze CPU Timing diagram of instruction codes
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Basic System Components and Operations
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The Address Bus
The address bus indicates which memory locations and I/O devices to be / being
accessed.
Address bus
memory memory memory
0 00 000 Information
1 01 001 (Data)
10 010
11 011
100
101
1-bit address 110
111
2-bit address 3-bit address
e.g. a 8088 or 8086 have 20-bit
address buses, and their address
spaces contain 220 = 1M
addressable memory locations
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The Data Bus
The data bus transfers information between a particular memory location or I/O
device
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The Control Bus
• Control bus includes a set of signals controlling how the processor
communicates with the rest of a system
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Memory Organization
• Memory can be thought of as a linear array of bytes 1 byte
• Most of processors support byte-addressable memory
(i.e. The basic memory unit is byte)
• Therefore, with 20, 24 and 32-bit address lines, the
processors can address 220 = 1Mbyte, 224 = 16Mbytes
and 232 = 4Gbytes of memory
Little-endian Addressing
(e.g. Intel machine codes)
Alternative: Big-endian
Least significant value in the
Most significant value in sequence is stored first.
the sequence is stored
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Cache Memory
ARM architecture
Bytewise
Blockwise
in ns in ms
Stores recently used data
Source: ARM Corporation
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Advanced Computer Architecture: Memory-mapped I/O
• CPU needs to talk with I/O devices such as
keyboard, mouse, video, disk driver, LEDs, I/O Port 0
etc. I/O Dev 1 mouse
I/O Port 1
I/O Port 2 I/O Dev 0 keyboard
I/O Port 3
CPU
• In design, not all the I/O devices are being I/O Port 4
I/O Port 5 I/O Dev 4 LCD
accessed simultaneously. Do those devices I/O Port 6
share the I/O port of CPU and access them
at different time? Can we increase the I/O
capacity? Control Signals
• Solution: Special
• Memory-mapped I/O Peripheral
interface
I/O Port 0 I/O Dev 1 mouse
I/O Port 1
I/O Port 2
I/O Port 3 I/O Dev 0 keyboard
CPU I/O Port 4
I/O Port 5
I/O Dev 4 LCD
I/O Port 6
Control Signals
Tradeoff?
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An Example: 8255 Programmable Peripheral Interface
8255 occupies 4 memory locations: Port A, Port B, Port C
and Control Register (CR).
Port A, Port B, Port C are configurable I/O ports
They are configured by the Control Word which is kept in
the Control Register (CR).
Special A1, A0 are the selectors for Port A, Port B, Port C and CR.
Peripheral
interface Start
How do you write the driver of 8255A for transferring
data between microcontroller and peripherals? Initialization
Step 1: Initialization Select the port
Configure the type of Ports
Write / Read
(input and/or output ports)
Yes
Next operation ?
Step 2: Implementation
No
Select an appropriate port Yes
New port ?
Set a write/read operation command
No
End
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Advanced Computer Architecture: Bus Protocols
• Protocol refers to the set rules agreed upon by both the bus master and
bus slave
– Synchronous bus – transfers occur in relation to successive edges of a clock
– Asynchronous bus – transfer bear no particular timing relationship
– Semi-synchronous bus – operations/control initiate asynchronously but data
transfer occurs synchronously
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About Timing Diagram
• The timing diagram represents a set of signals in the time domain. It
describes how the device is being operated.
– Example: the timing diagram of the port P1 when the following instructions
are executed one-by-one. 1 machine cycle 1 machine cycle
MOV P1, R0 ; at time 0; R0 = 36H
R0 R0 R1
MOV P2, R4 ; at time 1; R4 = 4AH
MOV P1, R1 ; at time 2; R1 = 58H P1.7
move R1 to P1
P1.6
Assume all are 8-bit ports P1.5
P1.4
P1.3
P1.2
P1.1
P1.0
Time 0 Time 1 Time 2
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About Timing Diagram
• For simplicity, it usually represents as
MOV P1, R0 ; at time 0; R0 = 36H
MOV P2, R4 ; at time 1; R4 = 4AH Assume all are 8-bit ports
MOV P1, R1 ; at time 2; R1 = 58H
Update the value
Keep the value
Update the value
R0 R0 R1
P1 36H 36H 58H
P2 unknown 4AH 4AH
Old value R4 R4
Time 0 Time 1 Time 2
Keep the value Update the value
Keep the value
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About Timing Diagram
• An example of EEPROM Timing diagram for Read Access
How many bits are there?
What is the value of this
address information?
How many bits are there?
What is the value of this
CE information?
How many bits are there?
What is the value of this
new data information?
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About Timing Diagram
Here is a timing diagram of a character type LCD device
Interval 1 Interval 2
Description
Interval 3 Abstract idea of project
(Define the functionality of the system)
Interval 4 Data format / representation
Programming Language
Communication Protocol
Physical connection (Pins assignment)
Hardware devices
(Microcontroller, Peripherals)
hardware
Interval 5 Interval 6
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In-class activities
Lecture 4
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Reflection (Self-evaluation)
• Could you ….
– List out the basic system components and operations ?
– Understand the following items and their operating principles in
advanced computer architecture ?
• Memory-mapped I/O
• Bus Protocols
– State the two basic steps in writing a device driver ?
– List 64-bit computing in computer architecture?
– Read CPU Timing diagram of instruction codes?
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Assembler
Instruction Set Architecture
Course Overview
Memory I/O System
More about
Datapath & Control Embedded Systems
Introduction to Basic Computer
Embedded Systems Structure
MCU Main Board
Digital and Analog
Interfacing USART, IEEE1394,
USB, I2C and SPI
Microcontroller Structure
A/D Port
Buffering and
Serial Port Direct Memory Access
CPU
(DMA)
External Memory Port
Memory,
Interfacing to Memory,
External Interrupt Port
Memory Timing
Interrupt and applications
External Timer Port Interfacing LCD
Organization Timer and
Counter Simple I/O Port
Motor Interfacing
In this course, STM32 is used as a driving vehicle for delivering the concepts.
To be covered In progress Done
ELEC 3300 : Fall 2021 Vinod Prasad 19
