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PLL Based High Frequency FM Modulator

TECHNICAL REPORT · MAY 2011

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PLL Based High Frequency FM Modulator

ABSTRACT
FM modulation refers to the process of modulating a carrier wave with respect
to the input message signal. Our project deals with the design of an FM modulator
using PLL for a frequency range of 1.5 GHz. A phase locked loop system used for
performing indirect frequency modulation.
A phase locked loop is comprised of a phase detector coupled to a low pass
filter and a voltage controlled oscillator with a feedback loop to the phase detector.
Input signals provided by a crystal controlled oscillator are fed to the phase detector.
A phase difference other than 90° between the voltage controlled oscillator output and
the input signal will result in the phase detector generating an error voltage which is
filtered by the low pass filter to alter the voltage controlled oscillator until its phase is
90° from the input signal.
A modulating signal is injected into the phase locked loop which causes the
voltage controlled oscillator to momentarily change frequency until the output of the
phase detector changes enough to balance the modulating signal. This proposed
system overcomes the stability problems of direct FM modulation technique. The
creation of such a system would combine the advantage of high stability offered by
indirect FM modulation technique with the simplicity of direct FM modulation
technique.

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PLL Based High Frequency FM Modulator

1. INTRODUCTION
1.1 Frequency modulation
Frequency modulation uses the instantaneous frequency of a modulating signal
(voice, music, data, etc.) to directly vary the frequency of a carrier signal. Modulation
index, β, is used to describe the ratio of maximum frequency deviation of the carrier to
the maximum frequency deviation of the modulating signal. Suppose the baseband
data signal (the message) to be transmitted is:

and is restricted in amplitude to be

and the sinusoidal carrier is

Where fc is the carrier's base frequency and Ac is the carrier's amplitude. The
modulator combines the carrier with the baseband data signal to get the transmitted
signal,

In this equation, is the instantaneous frequency of the oscillator and is the

frequency deviation which represents the maximum shift away from fc in one
direction, assuming xm(t) is limited to the range ±1. FM signals can be generated using
either direct or indirect frequency modulation.

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PLL Based High Frequency FM Modulator

Direct FM modulation can be achieved by directly feeding the message into the
input of a VCO. Indirect FM modulation, the message signal is integrated to generate
a phase modulated signal. This is used to modulate a crystal controlled oscillator, and
the result is passed through a frequency multiplier to give an FM signal

1.3 EXISTING SYSTEM:

In Existing systems like Armstrong modulators an audio signal is passed
through a pre-emphasis network and then an integrator, a special network whose
output is the time integral of the input signal. The pre-emphasized integrated signal is
used to phase modulate a crystal oscillator. Mathematically, it can be shown that PM
using the integral of the audio signal is identical to FM using the audio signal itself. In
this way an FM signal is generated.
The Armstrong modulator cannot produce much deviation, so combination of
multipliers and mixers are used to raise the carrier frequency and the deviation. The
multipliers are used to multiply the carrier and the deviation.
The mixers are used to decrease the carrier, while keeping the deviation
constant so that additional multiplier stages can be used to obtain more deviation.
Armstrong modulator is the DSB modulator and so power efficiency is low.

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PLL Based High Frequency FM Modulator

1.4 FM MODULATION USING PLL

A PLL circuit can be used to create an FM signal. The input to the phase
comparator is the carrier signal, and assuming that the carrier frequency is within the
capture range of the PLL, the VCO output frequency will be equal to the carrier
frequency. Now, if the VCO control voltage is the sum of the message waveform and
the loop error voltage, then the VCO output frequency will vary about the carrier
frequency according to the message. Thus, the VCO output is the desired FM signal.

PHASE LOOP SUMMER

COMPARATOR FILTER

VCO

Figure 1.4.1 FM modulation using PLL

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PLL Based High Frequency FM Modulator

BLOCK DIAGRAM:

Power Supply
89s52
Micro LCD
Controller (20×1 line)

Key Pad
(4×4 Matrix)

Phase Locked Loop

LMX 2326 Loop Filter VCO

The desired frequency, ranges from 1.450 GHz to 1.550GHz, is set by the user
using the 4×4 matrix key pad. This input is processed by the 89s52 Microcontroller
and the corresponding counter values are generated and loaded into the phase locked
loop (PLL).The output frequency from the Voltage Controlled Oscillator (VCO) is
displayed on the 20×1 line Liquid Crystal Display (LCD).

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PLL Based High Frequency FM Modulator

2. Phase-locked loop:

2.1 What is PLL?

A phase-locked, or phase-lock, loop (PLL) is an electronic control system that

generates a signal that is locked to the phase of an input or "reference" signal. A
phase-locked loop circuit responds to both the frequency and the phase of the input
signals, automatically raising or lowering the frequency of a controlled oscillator until
it is matched to the reference in both frequency and phase. Phase-locked loops are
widely used in radio, telecommunications, computers and other electronic applications
to generate stable frequencies, or to recover a signal from a noisy communication
channel.

2.2 Block Diagram

Fig. 2.1 Phase Locked Loop

2.2.1 Phase detector
The phase detector is the core element of a phase locked loop, PLL. Its action
enables the phase differences in the loop to be detected and the resultant error voltage
to be produced.
There is a variety of different circuits that can be used as phase detectors, some
that use what may be considered as analogue techniques, while others use digital
circuitry. However the most important difference is whether the phase detector is
sensitive to just phase or whether it is sensitive to frequency and to phase.

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PLL Based High Frequency FM Modulator

S 1(t)

Figure
S 2(t)

The output of multiplier is given by,

S 3(t)

2.2.2 Loop filter

The PLL filter is needed to remove any unwanted high frequency components
which might pass out of the phase detector and appear in the VCO tune line. They
would then appear on the output of the Voltage Controlled Oscillator, VCO, as
spurious signals. To show how this happens take the case when a mixer is used as a
phase detector. When the loop is in lock the mixer will produce two signals: the sum
and difference frequencies. As the two signals entering the phase detector have the
same frequency the difference frequency is zero and a DC voltage is produced
proportional to the phase difference as expected. The sum frequency is also produced
and this will fall at a point equal to twice the frequency of the reference. If this signal
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PLL Based High Frequency FM Modulator

is not attenuated it will reach the control voltage input to the VCO and give rise to
spurious signals. When other types of phase detector are used similar spurious signals
can be produced and the filter is needed to remove them. The typical loop filter is
shown below:

Fig 2.2 Configuration of a typical loop filter

The filter also affects the ability of the loop to change frequencies quickly. If
the filter has a very low cut-off frequency then the changes in tune voltage will only
take place slowly, and the VCO will not be able to change its frequency as fast. This is
because a filter with a lower cut-off frequency will only let lower frequencies through
and these correspond to slow changes in voltage level. Conversely a filter with a
higher cut-off frequency will enable the changes to happen faster. However when
using filters with higher cut-off frequencies, care must be taken to ensure that
unwanted frequencies are not passed along the tune line with the result that spurious
signal are generated. The loop filter also governs the stability of the loop. If the filter
is not designed correctly then oscillations can build up around the loop, and large
signals will appear on the tune line. This will result in the VCO being forced to sweep
over wide bands of frequencies. The proper design of the filter will ensure that this
cannot happen under any circumstances.

2.2.3 Voltage Controlled Oscillator

Phase locked loop having a voltage controlled oscillator, a phase comparator
and filtering means all of which are integrated into a single monolithic block. The
comparator is of the balanced bipolar analog multiplier type and is supplied a control
voltage by a multivibrator of the voltage controlled oscillator. The collector load of

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PLL Based High Frequency FM Modulator

the multivibrator is provided by the diode drops of the comparator's transistors. The
multivibrator is driven by a differential current divider which in turn is provided
current by a constant common current source.

2.2.4 Frequency Divider

A frequency divider is an electronic circuit that takes an input signal with a
frequency, fin, and generates an output signal with a frequency:

Where n is an integer. Phase-locked loop frequency synthesizers make use of

frequency dividers to generate a frequency that is a multiple of a reference frequency.
Frequency dividers can be implemented for both analog and digital applications.

2.2.5 Reference Oscillator:

Crystal oscillators are mainly preferred as reference oscillators for PLL because
of low cost and minimum size. It is piezoelectric quartz crystals that mechanically
vibrate between two slightly different shapes. Crystals have very high Q, and can only
be tuned within a very small range of frequencies. Crystal oscillators are typically
used as the frequency reference for other PLLs, and can be found in nearly every
consumer electronic device. Because the crystal is an off-chip component, it adds
some cost and complexity to the system design, but the crystal itself is generally quite
inexpensive.

2.2.6 Keypad

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PLL Based High Frequency FM Modulator

Key pad is used here to set the desired frequency range available from 1.45
GHz to 1.55 GHz. It requires two ports to scan the pressed button. The ports used here
are port 2 pins from p2.0 to p2.4 and port 1 pins from p1.1 to p1.4. The basic principle
of scanning the pressed button from the key pad is as follows:
The microcontroller, 89ls52, accesses both rows and columns through ports p2
and p1. Initially the column ports are set at high level and row ports are set at low
level. When the key is pressed the corresponding row and column come into contact
and hence any one of the four columns will become low (i.e. grounded). Now the
controller scans the column and identifies the grounded column and in order to find
out exact location of the key (i.e. in which the row the pressed key belongs to) it
ground the row one by one and read the columns and finds the pressed key.

The basic schematic diagram of interfacing 4×4 matrix keypad with

microcontroller ports P1 (P1.0 to P1.3) and P2 (P2.0 to P2.3) is shown below

D0

D1

D2

D3

D3 D2 D1 DO

FIG

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PLL Based High Frequency FM Modulator

If the data read from columns is D3 – D0 =1111, no key has been pressed and
the process continues till key press is detected. If one of the column bits has a zero,
which mean that a key press has occurred. For example, if D3 – D0 = 1101, this
means that a key in the D1 column has been pressed. After detecting a key press,
microcontroller will go through the process of identifying the key.
Starting with the top row, the microcontroller grounds it by providing a low to
row D0 only. It reads the columns, if the data read is all high, no key in that row is
activated and the process is moved to the next row. It grounds the next row, reads the
columns, and checks for any zero this process continues until the row is identified.
After identification of the row in which the key has been pressed it go through the
process of finding out in which column the pressed key belongs to.
Once the key is identified the microcontroller generates the corresponding
ASCII value for that particular key by going through the ASCII look up table and
stores it in a register for further process.
PROGRAM:
org 0000h
begin:
mov r7,#00h
mov r0,#31h
K1:
MOV P2,#0FH
MOV P1,#0h
MOV A,P2
ANL A,#00001111B
CJNE A,#00001111B,K1
K2: LCALL DELAY
MOV A,P2
ANL A,#00001111B
CJNE A,#00001111B,OVER
SJMP K2
OVER: LCALL DELAY

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PLL Based High Frequency FM Modulator

MOV A,P2
ANL A,#00001111B
CJNE A,#00001111B,OVER1
SJMP K2
OVER1: MOV P1, #11111110B
MOV A,P2
ANL A,#00001111B
CJNE A,#00001111B,ROW_0
MOV P1,#11111101B
MOV A,P2
ANL A,#00001111B
CJNE A,#00001111B,ROW_1
MOV P1,#11111011B
MOV A,P2
ANL A,#00001111B
CJNE A,#00001111B,ROW_2
MOV P1,#11110111B
MOV A,P2
ANL A,#00001111B
CJNE A,#00001111B,ROW_3
LJMP K2
ROW_0: MOV DPTR,#KCODE0
SJMP FIND
ROW_1: MOV DPTR,#KCODE1
SJMP FIND
ROW_2: MOV DPTR,#KCODE2
SJMP FIND
ROW_3: MOV DPTR,#KCODE3
FIND: RRC A
JNC MATCH
INC DPTR

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PLL Based High Frequency FM Modulator

SJMP FIND
MATCH: CLR A
MOVC A,@A+DPTR
mov r6,a
cjne r6,#43h,GO
mov a,#01h
acall comnwrt
lcall delay
LJMP begin

2.2.4 Liquid Crystal Display

Liquid Crystal Display (LCD) is used here to display the frequency value
which is fed through using keypad. It allows the user to make sure whether the desired
value of frequency and processed value are within one to one correspondence. 20×2
line LCD is connected to the microcontroller port P0 with external pull ups and port 1
pins from P1.4 to P1.6 are act as control pins. The potentiometer is added to adjust the
contrast level.

The schematic diagram of interfacing LCD with the microcontroller is shown

below,

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PLL Based High Frequency FM Modulator

The three control lines are referred to as EN, RS, and RW.

The EN line is called "Enable." This control line is used to tell the LCD that we
are sending it data. To send data to the LCD, program should make sure this line is
low (0) and then set the other two control lines and/or put data on the data bus. When
the other lines are completely ready, bring EN high (1) and wait for the minimum
amount of time required by the LCD datasheet (this varies from LCD to LCD), and
end by bringing it low (0) again.

The RS line is the "Register Select" line. When RS is low (0), the data is to be
treated as a command or special instruction (such as clear screen, position cursor,
etc.). When RS is high (1), the data being sent is text data which should be displayed
on the screen. For example, to display the letter "T" on the screen, RS should be high.

The RW line is the "Read/Write" control line. When RW is low (0), the
information on the data bus is being written to the LCD. When RW is high (1), the
program is effectively querying (or reading) the LCD. Only one instruction ("Get
LCD status") is a read command. All others are write commands, so RW will almost
always be low.

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PLL Based High Frequency FM Modulator

Finally, the data bus consists of 4 or 8 lines (depending on the mode of

operation selected by the user). Here we use an 8-bit data bus; the lines are referred to
as DB0, DB1, DB2, DB3, DB4, DB5, DB6, and DB7.

Code (Hex) Command to LCD Instruction Register

01 Clear display screen
02 Return home
04 Decrement cursor (shift cursor to left)
06 Shift display right
05 Shift display left
07 Display off, cursor off
08 Display off, cursor on
A Display on, cursor off
C Display on, cursor blinking
E Display on, cursor blinking
F Shift cursor position to left
10 Shift cursor position to right
14 Shift the entire display to the left
18 Shift the entire display to the right
80 Force cursor to beginning to 1st line
C0 Force cursor to beginning to 2nd line
38 2 lines and 5x7 matrix

PROGRAM:
MOV A,#38H
lCALL COMNWRT
LCALL DELAY
MOV A,#0EH
ACALL COMNWRT
LCALL DELAY
MOV A,R7

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CJNE A,#00H,SKIP
MOV A,#80H
ACALL COMNWRT
LCALL DELAY
SKIP:
acall datawrt
LJMP load
COMNWRT:
LCALL WAIT
MOV P0,A
CLR P1.5
CLR P1.4
SETB P1.6
CLR P1.6
RET
datawrt:
LCALL WAIT
mov a,r6
MOV P0,A
SETB P1.5
CLR P1.4
SETB P1.6
CLR P1.6
Ret

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PLL Based High Frequency FM Modulator

2.3 APPLICATIONS OF PLL

2.3.1 Frequency multiplication

A PLL can be readily used to generate a fixed integer multiple of an input

frequency. This is achieved with a signal divider placed in the feedback loop between
the VCO and phase comparator. There are, however, many other (possibly easier)
ways of performing frequency multiplication. The PLLs key distinguishing feature,
however, is its ability to lock onto and follow 20 regular input signals—even where
noise is present on that waveform. This means that the reproduced signal is a clean
copy (or clean multiple) of the input signal—a process of noise-rejection.

2.3.2 FM demodulation

In frequency modulation, the original waveform is encoded in a carrier signal

by variation of its frequency. A typical phase-locked loop can therefore be locked to
the incoming signal for demodulation. As the voltage is varying, the VCO’s output
frequency is proportional to the original waveform. This is therefore the desired
demodulated signal.

2.3.3 Clock regeneration

In data transmission, pulses are synchronized to a transmitting-side clock

signal, and typically sent across a single channel link. At the receiving end, a clean
clock signal needs to be generated for comparison. This allows the received pulses,
which may be distorted or noisy from the transmission medium, to be interpreted. By
locking a standard PLL to the received data signal, a regenerated clock signal can be
sourced from the output of the VCO.

2.3.4 Clock recovery

Some data streams, especially high-speed serial data streams (such as the raw
stream of data from the magnetic head of a disk drive), are sent without an
accompanying clock. The receiver generates a clock from an approximate frequency
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PLL Based High Frequency FM Modulator

reference, and then phase-aligns to the transitions in the data stream with a PLL. This
process is referred to as clock recovery. In order for this scheme to work, the data
stream must have a transition frequently enough to correct any drift in the PLL's
oscillator.

2.3.5 Clock generation

Many electronic systems include processors of various sorts that operate at

hundreds of megahertz. Typically, the clocks supplied to these processors come from
clock generator PLLs, which multiply a lower-frequency reference clock (usually 50
or 100 MHz) to the operating frequency of the processor. The multiplication factor
can be quite large in cases where the operating frequency is multiple of GHz and the
reference crystal is just tens or hundreds of megahertz.

2.3.6 Spread spectrum

All electronic systems emit some unwanted radio frequency energy. Various
regulatory agencies (such as the FCC in the United States) put limits on the emitted
energy and any interference caused by it.

The emitted noise generally appears at sharp spectral peaks (usually at the
operating frequency of the device, and a few harmonics). A system designer can use a
spread-spectrum PLL to reduce interference with high-Q receivers by spreading the
energy over a larger portion of the spectrum. For example, by changing the operating
frequency up and down by a small amount (about 1%), a device running at hundreds
of megahertz can spread its interference evenly over a few megahertz of spectrum,
which drastically reduces the amount of noise seen by FM receivers which have a
bandwidth of tens of kilohertz.

2.3.7 Jitter and noise reduction

One desirable property of all PLLs is that the reference and feedback clock
edges be brought into very close alignment. The average difference in time between
the phases of the two signals when the PLL has achieved lock is called the static
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PLL Based High Frequency FM Modulator

phase offset. The variance between these phases is called tracking jitter. Ideally, the
static phase offset should be zero, and the tracking jitter should be as low as possible.
Phase noise is another type of jitter observed in PLLs, and is mostly caused by
the amplifier elements used in the circuit. Some technologies are known to perform
better than others in this regard. The best digital PLLs are constructed with emitter-
coupled logic (ECL) elements, at the expense of high power consumption. To keep
phase noise low in PLL circuits, it is best to avoid saturating logic families such as
transistor-transistor logic (TTL) or CMOS.
Another desirable property of all PLLs is that the phase and frequency of the
generated clock be unaffected by rapid changes in the voltages of the power and
ground supply lines, as well as the voltage of the substrate on which the PLL circuits
are fabricated. This is called supply and substrate noise rejection.

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PLL Based High Frequency FM Modulator

3. DESIGN OF FREQUENCY SYNTHESIZER USING LMX2326:

The operation of PLL is mainly based on the reference frequency. Phase
detector checks the phase difference of the reference and the VCO signal. It produces
the output according to the phase difference. The output of the phase difference is
given to loop filter. Loop filter is one which produces voltage according to the phase
detector output. Voltage controlled oscillator produces different frequencies
depending upon the input voltage.
The frequency synthesizer is designed to operate from 1.45 GHz to 1.55 GHz
with the frequency step of 10MHz and the output level of -5dBm.The PLL chip
LMX2326 is preferred for this design because of very stable, minimum size and low
cost and LMX2326 employs digital phased locked loop technique. The LMX2326
also have FAST-LOCK mode and power down mode.
The LMX2326 derives the resonant frequency from the voltage controlled
oscillator CMV 14B15 with respect to the reference frequency of 10MHz. VCO can
tune from 1.45-1.55GHZ. The ATMEL AT89LS52 microcontroller plays a main
part in the operation of PLL. The R and N Counter values and functional latch values
are programmed in micro controller and synchronized to LM2326. The ports are
assigned to be connected to the PLL in respective pins. Port 2 is assigned to the PLL.
The circuit diagram is shown below:

Fig. 3.1 Circuit Diagram of AT89LS52

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PLL Based High Frequency FM Modulator

3.1 LMX2326:
The LMX2326 is monolithic, integrated frequency synthesizers with pre-scalar
that are designed to be used to generate a very stable low phase noise signal for
controlling the local oscillator of an RF transceiver. They are fabricated using
National’s ABiC V silicon BiCMOS 0.5μ process.
The LMX2326 contains a 32/33 dual modulus pre-scalar. The LMX2326
employ a digital phase locked loop technique. When combined with a high quality
reference oscillator and loop filter, the LMX2326 provide the feedback tuning voltage
for a voltage controlled oscillator to generate a low phase noise local oscillator signal.
Serial data is transferred into the LMX2326 via a three wire interface (Data,
Enable, and Clock). Supply voltage can range from 2.3V to 5.5V. The main features
of LMX2326 are an ultra low current consumption device (4 mA at 5.5V) and also
having digital lock detect.
The LMX2326 have wide application in portable wireless communication
(PCS/PCN, cordless) systems, wireless local area networks, and cable TV tuners and
in other communication systems. The LMX2326 synthesizers are available in a 16-pin
TSSOP surface mount plastic package. The internal block diagram of LMX2326 is

Fig. 3.2 Block diagram of LMX2326

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PLL Based High Frequency FM Modulator

3.1.1 Functional Description

The simplified block diagram above shows the 21-bit data register, a 14-bit
R Counter, an 18-bit N Counter, and a 18-bit Function Latch (intermediate latches
are not shown). The data stream is shifted (on the rising edge of LE) into the
DATA input, MSB first. The last two bits are the Control Bits.
The DATA is transferred into the counters as follows:

Control
DATA Location
C1 C2
0 0 R Counter

1 0 N Counter
0 1 Function Latch
1 1 Initialization

3.1.2 Programmable Reference Divider

If the Control Bits are [C1 , C2 ] = [0, 0], data is transferred from the 21-bit
shift register into a latch that sets the 14-bit R Counter. The 4 bits R15–R18 are
for test modes, and should be set to 0 for normal use. The LD precision bit, R19,
is described in the LOCK DETECT OUTPUT CHARACTERISTICS section.
Serial data format is shown below.

The value of R counter is derived as

R= fOSC / fPD
Where fOSC is reference oscillator frequency and fPD is input frequency of the phase
detector.
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PLL Based High Frequency FM Modulator

3.1.3 Programmable Divider (N Counter):

The N counter consists of the 5-bit swallow counter (A counter) and the 13-
bit programmable counter (B counter). If the Control Bits are [C1, C2 ] = [1, 0],
data is transferred from the 21-bit shift register into a 5-bit latch (which sets the
Swallow (A) Counter), a 13-bit latch (which sets the 13-bit programmable (B)
Counter), and the GO bit (See Section 1.3.4 Fast Lock MODES section) MSB
first. For the LMX2326 the maximum N value is 65535 and the minimum N value
is 56. For the LMX2316/26, the maximum N value is 262143 and the minimum N
value is 992. Serial data format is shown below.

The value of N counter is derived as

N=fvco = [(P x B) + A] x fosc/R, where

 fvco: Output frequency of external voltage controlled oscillator (VCO)

 B: Preset divide ratio of binary 13-bit programmable counter (3 to 8191)

 A: Preset divide ratio of binary 5-bit swallow counter (0 ≤ A ≤ 31; A ≤ B
for LMX2316/26) or (0 ≤ A ≤ 7, A ≤ B for LMX2326)

 fosc: Output frequency of the reference frequency oscillator

 R: Preset divide ratio of binary 14-bit programmable reference counter (3 to
16383) P: Preset modulus of dual modulus pre-scalar for the LMX2326 is P
= 32

3.1.4 FUNCTION AND INITIALIZATION LATCHES:

Both the function and initialization latches write to the same registers.

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3.1.4.1 Functional Description:

F1:- The Counter Reset enable mode bit F1, when activated, allows the reset of
both N and R counters. Upon powering up, the F1 bit needs to be disabled, then
the N counter resumes counting in “close” alignment with the R counter.

F2 & F18:- POWERDOWN bits which is enable when device is in programming

mode.

F3–5:- Controls output of FoLD pin.

F6:- Phase Detector Polarity. Depending upon VCO characteristics, F6 bit should
be set accordingly. When VCO characteristics are positive F6 should be set HIGH;
When VCO characteristics are negative F6 should be set LOW

F7:- Charge Pump TRI-STATE is set using bit F7. For normal operation this bit
is set to zero.
F8:- When the Fast Lock Enable bit is set the part is forced into one of the four
Fast Lock modes.

F9:- The Fast Lock Control bit determines the mode of operation when in Fast
Lock (F8 = 1). When not in Fast Lock mode, Flo can be used as a general purpose
output controlled by this bit. For F9 = 1, FLo is HIGH and for F9 = 0, FLo is
LOW.

F10:- Timeout Counter Enable bit is set to 1 to enable the timeout counter.
F11–14:- Fast Lock Timeout Counter is set using bits F11-14.
F15–17:- Function bits F15–F17 are for Test Modes, and should be set to 0 for
normal use.

F19. Function bit F19 is for a Test Mode, and should be set to 0 for normal use.
3.1.5 DEVICE PROGRAMMING:
When programming the LMX2326 first determine the frequencies and mode

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of operation desired. Data register is programmed with a 21-bit data stream shifted into
the R counter, N counter, or the F latch. Consider an example, the RF output is
locking at 1.5 GHz (fvco) with a 2 MHz channel spacing (fcomparison ). The
crystal oscillator reference input is 10 MHz (fosc) and the pre-scalar value (P) is
32.
The last two bits (control bits C1 and C2) of each bit stream identify which
counter or FLo mode will be programmed. For example, to program the R counter,
C1 and C2 will be 0, 0. Immediately preceding these two bits is the N, R, or F bits
providing the divide ratios and Fast Lock mode information.

Control
DATA Location
C1 C2
0 0 R Counter
1 0 N Counter
0 1 Function Latch
1 1 Initialization

For example, to load the N counter, the last two bits C1 and C2 must be 10.
Once the control bits have been determined, the frequency information must be
determined. To begin, determine the N and R counter values as follows:

N = fvco/fcomparison

&

R = fosc/fcomparison
For this example R and N are determined as follows:
R = 10MHz/2MHz = 5 and N = 1500MHz/2MHz = 750
N COUNTER:
The calculated value of N and the value of P are now used to determine the
values of A and B where both A and B is integer values:

N=P*B+A

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Where B is the divisor and A is the remainder. Therefore:

B = div (N/P)
&

A = N − (B * P)

For this example, B and A are calculated as follows:

B = div (750/32) = 23 = 0000000010111

&

A = 750 − (23 * 32) = 14 = 01110

To load the N counter with these values, the programming bit stream would
be as follows. The first bit, the GO bit, (MSB) N [19] is used for Fast Lock
operation and will be discussed in the F Latch section. The next 13 bits, (N [18]–N
[6]) shifted in, are the B counter value, 0000000010111b. Bits N [5]–N [1] are
the A counter and are 01110b in this example. The final two bits (the control bits)
are 1, 0 identifying the N counter. In programming the N counter, the value of B
must be greater than or equal to A, and the value of B must be greater than or
equal to 3. In programming the counter, data is shifted in MSB first.

R COUNTER:
Programming the R counter is done by shifting in the binary value of R
calculated previously (05d = 101b ). The first bit shifted in is R[19] the LD
precision bit.
The next 4 bits (R[18]–R[15]) shifted in, are used for testing and
should always be loaded with zeros. The R [14]–R[1] bits are used to program the
reference divider ratio and should be 00000000000101b for this example.
The final two bits, C[1] and C[2] denote the R counter and should be 0,

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0. The resulting bit stream looks as follows:

F LATCH:

To program the device for any of the Fast Lock modes, C [1] = 0 & C [2] = 1
which direct data to the F latch. The FUNCTION AND INITIALIZATION LATCH
section discusses the 4 modes of Fast Lock operation. The user must first determine
which Fast Lock mode will be used.

When using any of the Fast Lock modes, the programmer needs to
experimentally determine the length of time to stay in high gain mode. This is
done by looking at the transient response and determining the time at which the
device has settled to within the appropriate frequency tolerance.

Fast Lock mode should be terminated just prior to “lock” to place the
switching phase glitch within the transient settling time. The counter reset
mode (F[1] bit) holds both the N and R counters at load point when F[1] =
HIGH.

Upon setting F[1] = LOW, the N and R counters will resume counting in
close phase alignment. Other functions of the F latch such as FoLD output
control, Phase detector polarity, and charge pump TRI-STATE are defined in
the FUNCTION AND INITIALIZATION LATCH section also.

Program Into Lmx2326 : Sorry, the Program was removed (Think and do it yourself)

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3.2 Voltage Controlled Oscillator CMV 14B15:

The VCO CMV 14B15 can operate from 1300MHz to 1600MHz with tuning
voltage required from 0.1 to 5.5V. It is MINI-14S style package. The specification of
this VCO is tabulated below:

PERFORMANCE SPECIFICATIONS VALUE UNITS

Oscillation Frequency Range 1300 – 1600 MHz
Phase Noise @ 10 kHz offset (1 Hz BW,
-107 dBc/Hz
typ.)
Harmonic Suppression (2nd, typ.) -5 dBc
Tuning Voltage 0.1 - 5.5 Vdc
Tuning Sensitivity (avg.) 51 MHz/V
Power Output 4.25 3.75 dBm
PERFORMANCE SPECIFICATIONS VALUE UNITS
Load Impedance 50 Ω
Operating Temperature Range -40 to 85 °C
Power Supply Requirements
Supply Voltage (Vcc, nom.) 5 Vdc
Supply Current (Icc, typ.) 12 mA

3.3 LOOP FILTER:

R1
In Out
C1 2.4k Ω
20nF C2
156nF
C3
2nF
R2
716Ω

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Fig. 3.3 3rd Order Low Pass Filter

The Phase detector produces the sum and difference frequencies with two times
the input frequency. Sum with multiple of input frequency must be removed before it
reaches to or else it tends to produce large spurious signals in the output which is
undesirable. In order to block such frequencies, loop filter with relatives(it should not
be narrow or wide and varies according to the application) band width is required, In
this case, Low Pass Filter with third order passive loop filter is implemented.
A simple passive loop filter is sufficient for this application because of low noise.
C1, C2, C3, R1, and R2 form a third order filter. The VCO creates an extra pole.
Therefore, the complete structure of the loop filter creates a third order loop. The
complete R2 and C2 represent the core of the loop filter, whereby the other
components C1 and the cascaded low pass R1 and C3 are used to further enhance the
system performance by adding higher order attenuation.
Bode plot for this filter is plotted in order to observe the attenuation level with
respect to frequency. The loop filter is designed for the loop bandwidth of 6 KHz.
Bode plot for this filter is shown below:

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Fig Bode Plot for the Loop Filter

From the plot it can be seen that while the frequency approach 6 KHz the
attenuation tends to -1.441 dB. Hence it is evident that frequency above 6 KHz is
attenuated more and hence blocked reaching the Voltage Controlled Oscillator (VCO)
which in turn reduce the spurious signals out from the Voltage Controlled Oscillator
(VCO).Hence Loop Filter plays the vital role while designing the Phase Locked Loop.
It is possible to omit low pass filter, R1-C3 in many applications. Consider the
following when optimizing any PLL frequency synthesizer:
 The time it takes to step from one frequency to another
 The suppression of reference side bands
 The minimum in-band phase noise to obtain
3.4 ATMEL microcontroller AT89LS52:
The AT89LS52 is a low-voltage, high-performance CMOS 8-bit
microcontroller with 8K bytes of in-system programmable Flash memory. The device
is manufactured using Atmel’s high-density nonvolatile memory technology and is
compatible with the industry-standard 80C51 instruction set and pin out.
The on-chip Flash allows the program memory to be reprogrammed in-system
or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit
CPU with in-system programmable Flash on a monolithic chip, the Atmel AT89LS52
is a powerful microcontroller which provides a highly-flexible and cost-effective
solution to many embedded control applications.
The AT89LS52 provides the following standard features: 8K bytes of Flash,
256 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, three 16-bit
timer/counters, a six-vector two-level interrupt architecture, a full duplex serial port,
on-chip oscillator, and clock circuitry. In addition, the AT89LS52 is designed with
static logic for operation down to zero frequency and supports two software selectable
power saving modes.

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The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial
port, and interrupt system to continue functioning. The Power-down mode saves the
RAM contents but freezes the oscillator, disabling all other chip functions until the
next external interrupt or hardware reset.

Fig. 3.4 Pin Diagram of AT89LS52

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3.4.1 Block Diagram:

Fig. 3.5 Block Diagram of AT89LS52

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AT89LS52 contains four I/O ports for sending and receiving the data. Port 1,
Port2 and port3 is an 8-bit bidirectional I/O port. These ports provide internal pull-
ups. Port0 is also an 8-bit bidirectional but it requires an external pull-ups. Port 0 can
also be configured to be the multiplexed low-order address/data bus during accesses to
external program and data memory. In this mode, P0 has internal pull-ups.
When 1s are written to Port 1 pins, they are pulled high by the internal pull-ups
and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low
will source current (IIL) because of the internal pull-ups.
In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external
count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively,
as shown in the following table. Port 1 also receives the low-order address bytes
during Flash programming and verification.

PORT PIN ALTERNATE FUNCTIONS

P1.0 T2 (external count input to Timer/Counter 2), clock-out
P1.1 T2EX (Timer/Counter 2 capture/reload trigger and direction control)
P1.5 MOSI (used for In-System Programming)
P1.6 MISO (used for In-System Programming)
P1.7 SCK (used for In-System Programming)

3.4.2 RST
Reset input. All I/O pins are reset to 1s as soon as RST goes high. Holding the
RST pin high for two machine cycles while the oscillator is running resets the device.
Each machine cycle takes 12 oscillator or clock cycles.

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3.4.3 Oscillator Characteristics

XTAL1 and XTAL2 are the input and output, respectively, of an inverting
amplifier which can be configured for use as an on-chip oscillator, as shown in Figure
1.7. Either a quartz crystal or ceramic resonator may be used.

Fig. 3.6 Oscillator Connections

Note: C1, C2 = 30 pF ± 10 pF for Crystals = 40 pF ± 10 pF for Ceramic Resonators

3.4.4 Programming the Flash

The AT89LS52 is shipped with the 8K bytes of on-chip EPROM code memory
array in the erased state (i.e., contents = FFH) and ready to be programmed. The code
memory array is programmed one byte at a time. Once the array is programmed, to re-
program any non-blank byte, the entire memory array needs to be erased electrically.

3.4.5 Internal Address Counter

The AT89LS52 contains an internal EPROM address counter which is always
reset to 000H on the rising edge of RST and is advanced by applying a positive going
pulse to pin XTAL1.

3.4.6 Programming Algorithm

To program the AT89LS52, the following sequence is recommended.
1. Power-up sequence: Apply power between VCC and GND pins Set RST and
XTAL1 to GND.
2. Set pin RST to “H”

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3. Apply the appropriate combination of “H” or “L” logic levels to pins P3.3,
P3.4, P3.5, and P3.7 to select one of the programming operations shown in the
PEROM Programming Modes table.
To Program and Verify the Array:
4. Apply data for Code byte at location 000H to P1.0 to P1.7.
5. Raise RST to 5V to enable programming.
6. Pulse P3.2 once to program a byte in the EPROM array or the lock bits. The
byte-write cycle is self-timed and typically takes 1.2 ms.
7. To verify the programmed data, lower RST from 5V to logic “H” level and set
pins P3.3 to P3.7 to the appropriate levels. Output data can be read at the port
P1 pins.
8. To program a byte at the next address location, pulse XTAL1 pin once to
advance the internal address counter. Apply new data to the port P1 pins.
9. Repeat steps 5 through 8, changing data and advancing the address counter for
the entire 2K bytes array or until the end of the object file is reached.
10. Power-off sequence: set XTAL1 to “L”
Set RST to “L”, Turn VCC power off.

4. Circuit design:
4.1 Design of R Counter and N Counter:
To determine the R and N counter values as follows

N = fvco /fcomparison

&

R = fosc/fcomparison
Given parameters,
fOSC – 10 MHz,
fVCO – 1.45-1.55 GHz,
f Comp – 2 MHz, and
P- 32 then the value of R is calculated as
R = 10 MHz/2 MHz = 5, and the corresponding bits are

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C1 C2 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19
0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value = 5

Now the value of R, fVCO and the value of P are used to determine the values of N,
N=P*B+A
Where, B is the divisor and A is the remainder. Therefore
B = div (N/P)
&

A = N − (B * P)
If fVCO is 1500 MHz, then

N = fvco /fcomparison
N= 1500MHz/ 2MHz = 750
fvco = [P×B + A] * [fosc/R]
750 = [32×B + A] * [10/10]
750 = 32×B + A
B = 23
A = 14
The corresponding bits for N Counter for 1500 is
C1 C2 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19
1 0 0 1 1 1 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0

Similarly the derived values of N for RF output – 1.45 GHz to 1.55 GHz.
N Counter for 1510
C1 C2 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19
1 0 1 1 0 0 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0

N Counter for 1520

C1 C2 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19
1 0 0 0 0 0 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0

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N Counter for 1530

C1 C2 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19
1 0 0 1 0 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0

N Counter for 1540

C1 C2 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19
1 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0

N Counter for 1550

C1 C2 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19
1 0 1 1 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0

N Counter for 1450

C1 C2 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19
1 0 1 0 1 0 1 0 1 1 0 1 0 0 0 0 0 0 0 0 0

N Counter for 1460

C1 C2 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19
1 0 0 0 0 1 0 1 1 0 1 1 0 1 0 0 0 0 0 0 0

N Counter for 1470

C1 C2 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19
1 0 0 1 1 1 1 1 0 1 1 0 1 0 0 0 0 0 0 0 0

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N Counter for 1480

C1 C2 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19
1 0 0 0 1 0 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0

N Counter for 1490

C1 C2 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19
1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0

Functional Latch:
The functional latch value is derived based on VCO characteristics, power
down operation and fast-lock modes. The enabled bits are shown below,

C1 C2 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18

0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0

4.2 Loop Filter Design:

The resistance and capacitance values for the loop filter is calculated by using
PLL Loop Filter Design Tool provided by National Semiconductors

The parameters for designing the loop filters is follows,

KVCO − (MHz/Volt):- Voltage Controlled Oscillator (VCO) Tuning Voltage

constant. It is frequency Vs voltage tuning ratio.
Kf − (mA/2prad):-Phase detector/charge pump constant. It is ratio of the
current output to the input phase differential.
RFOPT − (MHz):-Radio Frequency output of the VCO at which the loop filter
is optimized.
FREF − (kHz):-Frequency of the phase detector inputs. It is usually equivalent
to the RF channel spacing.
N:-Main divider ratio. Equal to RFOPT/FREF

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Given parameters:
Kvco = 51 MHz/volt
Kf = 1mA/2Π rad
Kp = 45o
Loop bandwidth = 6 KHz
Charge pump current = 1mA

Calculated values:
C1 = 20nf
C2 = 156nf
C3 = 2nf
R1 = 2.4KΩ
R2 = 716Ω

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6.Test Procedure and Results:

6.1Test setup
The test setup for the output measurement is

Power
supply LCD
+5V Gnd (20×2Line)

Frequency Spectrum
Microcontroller synthesizer Analyzer
(89LS52)

Key Pad
(4×4 Matrix)

Fig 6.1 Test setup

6.2 Test procedure:

 Set power supply +5V and supply current of 70mA
 Connect the output port of the frequency synthesizer to the spectrum
analyzer.
 Vary the frequency selection bits by 4×4 matrix keypad and record the
corresponding frequency in the spectrum analyzer.
 For Phase noise measurement, set span 200 KHz, RBW 1Hz and VBW
10Hz in the spectrum analyzer. Capture the output signal and set 1 KHz,
10 KHz and 100 KHz marker offset in the spectrum analyzer with
respect to the signal peak. Record the marker offset level which is
corresponding to phase noise.
 For harmonics measurement, set wide span in the spectrum analyzer to
capture all the harmonics of the signal. Measure all the harmonics level.

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6.3 Measured frequency and output level:

OUTPUT
KEY POSITION OUTPUT LEVEL
FREQUENCY

1450 1.45 GHz

1460 1.46 GHz

1470 1.47 GHz
1480 1.48 GHz
1490 1.49 GHz

1500 1.50 GHz

1510 1.51 GHz

1520 1.52 GHz

1530 1.53 GHz

1540 1.54 GHz

1550 1.55 GHz

The measured plot at the centre frequency of 1500 MHz is

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Fig 6.2 Frequency plot

6.4 Measurement of Phase noise:

Center Frequency = 145 MHz
Span = 100 KHz
The phase noise
@ 1 KHz = -73.72 dBc
@ 10 KHz = -85.63 dBc
@ 100 KHz = -107.66 dBc

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The corresponding measured plot is

Fig 6.3 Phase noise plot at 10 KHz offset

6.5 Measurement of Harmonics

Start frequency = 1 MHz
Stop frequency = 1 GHz
RBW = 300 KHz
VBW = 300K Hz
The harmonics at,
2nd Harmonics @ 145 MHz = -7.68dBc

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3rd Harmonics @ 290 MHz = -19dBc

4th Harmonics @ 435 MHz = -36dBc
5th Harmonics @ 580 MHz = -48dBc
6th Harmonics @ 725 MHz = -41dBc

Fig 6.5 Harmonics measurement plot

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7. PCB layout

Fig 7.1 PCB layout

fig7.2- PCB with fabricated components

8. Conclusion:
LMX2326 combined with VCO CMV-14B15 produces low phase noise of 100
dBc at 100 KHz offset.

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Photos:

(1500 refers to 1.5 GHz, Frequency can be varied from 1450 (1.45GHz) to 1550
(1.55GHz))

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The Spectrun Analyzer Shows That Carrier is Now locked to 1.5GHz.

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Spectrum Analyzer show that The Message signal of 20 MHz Bandwidth is modulated
with Carrier Frequency of 1.5 GHz

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