8085 Instruction Set Appendix F deseribes each instruction fully in terms of its operation and the operand, including details such, ‘as number of bytes, machine cycles, T'states, Hex code, and affected flags. The instructions appear in al phabetical order and are illustrated with examples.138 {APPENDIX F ‘The following abbreviations are used in the deseription of the instruction set. SO8OA/8085 Register Memory Location R= Register cy = Cary ACI: Add Immediate to Accumulator with Carry Opcode —Operand Bytes. M-Cyeles ‘States. Hex Code ACL -Bbitdata 2 2 7 cE Description The §-bit data (operand) and the Carry flag are added to the contents of the accumulator, and the result is stored in the accumulator Flags All flags are modified to reflect the result of the addition, Example Assuming the accumulator contains 26H and the previous operation has set the Cary flag, add byte 57H to the accumulator Instruction: ACIS7H Hex Code: CE 57 Addition (A) 26H =0010 0110 (Datay: STH=O101 0111 cyt 4 7eH=T111 1110 Flags; S=0 Z=0 AC=0 Pet cY Comments: 1. After adi 2. This instruct used (0 account fora carry generated by 8-bit numbers. on the previous Carry flag is cleared. is commonly used in 16-bit addition, This instruction should not be005 INSTRUCTION SEP 739 ADC: Add Register to Accumulator with Carry Opeode —Operand Bytes. M-Cycles—"FStates Hex Codes ADC Reg, 1 ' 4 Re Mem. I 2 1 Hex 88 89 BA 8B 8c 8D SE. 8P pzZremoae Description The contents of the operand (register or memory) and the Carry flag are ‘added to the contents of the accumulator and the result is placed in the accumulator. The contents of the operand are not altered; however, the previous Carry flag is reset. Flags All flags are modified to rfleet the result of the addition, Example Assume register pair BC contains 2498H and register pair DE contairs S4A1H. Add these 16-bit numbers and save the result in BC registers ‘The steps in adding 16-bit numbers are as follows: 1, Aad the contents of registers C and E by placing the contents of one register in the ae- ‘cumulator, This addition generates a Carry. Use instruction ADD (explained on the ext page) and save the low-order 8-bits in register C. 98H = 1001 1000 AIH = 1010 0001 1 39H= 1 OOTT 1001 — Store inregister C cy cy 2. Ada the contents of registers B and D by placing the contents of one register inthe ae ‘cummulator. Use instruction ADC. ‘The result will be as follows. 2H=0010 0100 SIH=0101 0100 L 1. (Cary from the previous addition PH=OT TT 1001 Store in register B Comments; This instruction is generally used in 16-bit addition, For example, 1 add the ‘contents of BC registers to the contents of DE registers this instruction is used to account for the earry generated by low-oner bytes.740 -PENDIX F ADD: Add Register to Accumulator Opcode —Operand Bytes. M-Cycles— States. Hex Codes ADD Reg. 1 1 4 Reg. Hex Mem. 1 2 1 >Ecmmooe Description ‘The contents of the operand (register or memory) are added to the contents Of the accumulator and the result is stored in the accumulator. If the operand is a memory Jocation, that is indicated by the 16-bit address in the HL register, Flags All flags ate modified to reflect the result of the addition Example Register B has 51H and the accumulator has 47H. Add the contents of regis ter B to the contents of the accumulator, Instruction: ADDB Hex Code: 80 Register contents Register contents before instru Addition alter instruction SZ_AC PCY A [7X] F oid A [98 T0,0.-0_9] F B [sil x] c ooo B L c Example Memory location 2050H has data byte A2H and the accumulator 1s 76H. ‘Add the contents of the memory location o the contents of the accumulator Instruction; ADD M_— Hex Code: 86 Before this instruction is executed, registers HL. should be loaded with data 2059H.2086 INSTRUCTION SEP 741 Register contents before instruction fei x) F a Tx[Tx]c pt-x[x]e 2050 [Ad] # [20 [50] L Addition: Register contents after instruction SZ AC P CY (a) A (0001 iF (2050H)ssem B 16 x Ic D| is x _|E H| 18 50. Dy Opeode —Operand Bytes ‘TStates Hex Codes ADI &bit 2 2 7 co data Description The 8-bit data (operand) are added to the contents of the accumulator, and the result is placed in the accumulator, Flags All lags are modified to reflect the result of the addition, Example The accumulator contains 4AH, Add the data byte 59H (o the contents of the accumulator. Instruction; ADIS9H Hex Codes 6.59 Addition: (A): 4AH=0100 1010742 APPENDIX F ANA: Logical AND with Accumulator Opcode —Operand Byles M-Cycles. “States Hex Codes ANA Reg, I 1 4 Reg. Hex Mem. 1 2 7 40 Al ro a a AS 6 Ar >Ecmmoaw, Description The contents of the accumulator are logically ANDed with the contents of the operand (register or memory), and the result is placed in the accumulaor. Ifthe ‘operand is a memory location, its address is specified by the contents of HL registers. Flags, 7, P ate modified to reflect the result of the operation, CY is reset In 8085, AC is set, and in 80B0A AC is the result of ORing bits D, of the operands, Example The contents of the accumulator and the register D are 54H and 821, respec- tively. Logically AND the contents of register D with the contents of the accumulator Show the flags andthe contents of each register after ANDing. Instruction: ANAD Hex Code: A2 Register contents Logica Reiser contents before instruction ‘AND after instruction sz ac pcy ASH X F sit-0101 0100 al —w@ bor AND Bm XE OH 0,010), _S010s1.0,,_(p[meezaci enema) 000 0000 Flags: S=0,Z= 1, P=1 AC=1,CY=0 (for 8080A, AC = 0) ANI: AND Immediate with Accumulator Opeode —Operand Bytes. M-Cycles_—TStates Hex Code ANI Bhi 2 2 7 6 data‘9086 INSTRUCTION SET 43 Description ‘The contents of the accumulator are logically ANDed with the 8-bit data (operand) and the results are placed in the accumulator, Flags. S, Z, P are modified to reflect the results of the operation, CY is reset. In 8085, AC is set. Example AND data byte 97H with the contents of the accumulator, which contairs ASH. Instruction: ANI97H Hex Code: E697 Logical AND: (A): 3H ‘AND (Das): 971 Lt SZ AC PCY ~ 00 OOT1 Al B 1010, 0)F CALL: Unconditional Subroutine Call Opcode —Operand Bytes M-Cycles ‘States Hex Code CALL 16-bit 3 5 8 cD address Description ‘The program sequence is transferred to the address specified by the operand, Before the transfer, the address of the next instruction to CALL (the contents of the program counter) is pushed on the stack. ‘The sequence of events is described in the example below. Flags No flags are affected. Example Write CALL instruction at memory location 2010H to call a subroutine 1 ccaled at 2050H. Explain the sequence of events when the stack pointer is at location 2009H, Memory Hex Address Code Mnemonics 2010 = CD_—CALL2050H 2011 50 2012 20 Note: See the difference between writing a 16-bit address as mnemonics and code. In the code, the low-order byte (50) is entered first, then the high-order byte (20) is entered However, in mnemonics the address is shown in the proper sequence. If an assembler is, used to obtain the codes, it will automatically reverse the sequence of the mnemonics.144 APPENDIE F Execution of CALL: ‘The address in the program counter (2013H) is placed on the stack as follows, Stack pointer is decremented to 2098H 2097 [13 MSB is stored 209820, ‘Stack pointer is again decremented SP» 209 LSB is stored Call address (20504) is temporarily stored in internal WZ registers and placed on the bus for the fetch eyele Comments: ‘The CALL instruction should be accompanied by one of the retumn (RET of conditional return) instructions in the subroutine. Conditional Call to Subroutine Operand—16-Bit Address op Flag Hex Code Deseription Status Code M-Cyeles TStates CC Call on Cary cy=1 oc 2/9 (it condition is not teue) ENC Call withNoCany CY=0 D4 5/18 (if condition is true) CP Call on positive S=0 PA Note: If condition is not true it continues, CM Call on minus S=1 FC the sequence, and thus requires CPE Gallon Parity Even = P=1 BC. fewer T-states, CPO Callon Party Odd P=0 BA condition is tue it calls the CZ Call on Zero Za; CC subroutine, thus requites more NZ Call on No Zero Z=0 0 C4 states, Flags No flags ar affected, CMA: Complement Accumulator Opcode Operand —_Bytes._--M-Cycles-—T-States Hex Code CMA None 1 1 4 oF Description The contents of the accumulator are complemented, Flags No flags are affected :xample Complement the accumulator, which has data byte 89H. Instruction: CMA Hex Code: 2F Before instrtion After instrvtion alo CoToO]-s afi tio1iy 16H‘9086 INSTRUCTION SET CMC: Complement Carry Opcode —Operand Bytes. M-Cycles.-TStates Hex Code CMC None 1 1 4 oF Description ‘The Carry flag is complemented Flags The Carry flag is modified, no other flags are affected. CMP: Compare with Accumulator Opcode —Operand Bytes. MeCycles. States Hex Codes cMP Reg, 1 1 4 Reg, Hex Mem. 1 2 7 BS Bo BA BB BC BD BE BF >Ecmmvae Description ‘The contents of the operand (register or memory) are compared with the contents of the accumulator. Both contents are preserved and the comparison is shown by setting the Mags as follows: DIA) < (Reg/Mem: Carry flag is set and Zero flag is reset, 1D f(A) = (Reg/Mem): Zero flag. is set and Carry flag is reset. 11 IFA) > (Reg/Mem): Carry and Zero flags are reset. ‘The comparison of wo bytes is performed by subtracting the contents of the operand {rom the contents of the accumulator; however, neither contents are modified. Flags S, P, AC are also modified in addition to Z and CY to reflect the results of the op eration Example Register B contains data byte 62H and the accumulator contains data bye 57H. Compare the contents of register B with those of the accumulator, Instruction; CMP-B Hex Code: BB. Before instruction ‘After instruction A{s7[xx] F a (old B [o2[xx]c B [62 [xx Flags: $= 1, Z=0, AC P .cY=1 748746 PEND F Results after executing the instruction: No contents are changed. 1 Carry flag is set because (A) < (B). OS, Z,P.AC flags will also be modified as listed above. CPI: Compare Immediate with Accumulator Opeode —Operand Bytes M-Cycles cP bit 2 A 7 FE Description ‘The second byte (8-bit data) is compared with the contents of the accu lator. The values being compared remain unchanged and the results of the comparison are indicated by setting the lags as Follows. 11 IF(A) < Data Carry fag is set and Zero flag is reset F(A) = Data: Zero flag is set and Carry flag is reset MCA) > Data; Carry and Zero flags are reset. ‘The comparison of two bytes is performed by subtracting the data byte from the contents ‘of the accumulator; however, neither contents are modified, Flags, P, AC are also modified in addition to Z and CY to reflect the result of the operation, Example Assume the accumulator contains data byte ‘cumulator contents 2H. Compare 98H with the ac- Instruction: CPI98H Hex Code: FE 98 Results after executing the instruction 'D The accumulator contents remain unchanged. Zand CY flags are reset because (A) > Data, © Other fags: $ = 0, AC =0, P=. Example Compare data byte C2H with the contents of the accumulator in the above ex: mple, Instruction: CPLC2H Hex Code: FE C2 Results after executing the instruction © The accumulator contents remain unchanged 1 Zero flag is set because (A) = Data 1 Other lags: $= 0, AC = CY‘8086 INSTRUCTION SET 141 DAA: Decimal-Adjust Accumulator Opcode —Operand Bytes M-CyelesT'States_—_Hex Code DAA None 1 1 4 2 Description The contents of the accumulator are changed from a binary valle t0 (wo 4-bit binary-coded decimal (BCD) digits. Tis isthe only instruction that uses the auxil- {ary flag (internally) to perform the binary-to-BCD conversion; the conversion procedure is deseribed below. Flags $,Z, AC, P, CY flags ate altered to reflect the results of the operation. Instruction DAA converts the binary contents of the accumulator as follows 1. If the value of the low-order four bits (Dy-Dp) in the accumulator is greater than 9 or if AC flag is sot, the instruction adds 6 (06) 0 the low-order Four bits 2, IF the value of the high-order four bits (D,—D,) in the accumulator is greater than 9 ot if the Carry flag is set, the instruction adds 6 (60) to the high-order four bits Example Add decimal I2ycp to the aceun ator, which contains 39ycp- The binary sum is 4BH, The value of the low-order four bits is larger than 9. Add 06 10 the low-order Four bits Example Add decimal 68ycy to the accumulator, which contains 85yep. (A= B5pep=1000 0101 + 68ep=0 110 1000 T3ueo=1 110 11 OT ‘The binaty sum is EDH. ‘The values of both, low-order and high-order, four bits. are higher than 9, Add 6 to both = B= 1110 1101 46= 0110 0110 it O)3-Gorer ori148 APPENDIX F ‘The accumulator contains 53 and the Cary flag is set to indicate thatthe sum is larger than eight bits (153). The program should keep track of the Carry; otherwise it may be al {ered by the subsequent instructions DAD: Add Register Pair to H and L Registers Opcode —Operand Bytes M-Cycles.—TStates Hex Codes, DAD Reg. pair 3 10 | Reg. Pair Hex B09 D9 H (29 a) Description The 16-bit contents of the specified register pair are added to the contents ofthe HL register and the sum is saved in the HL register The contents ofthe source reg: ister pair are not altered. lags IF the result is larger than 16 bits the CY flag is set. No other flags are affected, Example Assun register pair HL contains 0242H, Multiply the contents by 2. Instruction: DAD H Hex Code: 29 Before instruction DAD operation After instruction ona u[o2[ a2]. 40242 0484 [ores] i Example Assume register pair HL is cleared, Transfer the points to memory location 2099H to the HL register pai inter (register) that Instruction: DAD SP Hex Code; 39 Before instruction DAD operation After instruction [00 [00] L. ‘0000 H{20[ 99] sp [2059 +2099) sp[_2099 2099 Note: After the execution of the instruction, the contents of the stack pointer register are not altered805 INSTRUCTION SET m9 DCR: Decrement Source by 1 Opceode —Operand Bytes. MeCycles.—T-States Hex Codes pcr Reg, 1 1 4 Reg, Hex. Mem. 1 3 10 05 oD 15 ID 25 2D 35 3D >Ermmuns, Description ‘The contents of the designated register/memory is decremented by 1 and the results are stored in the same place. If the operand is a memory location, it is speci~ fied by the contents of the HL register pair. CY is not modifi. Flags, Z, P, AC are modified to reflect the result of the operat Example Decrement register B, which is cleared, and specify its contents after the ‘decrement Instruction: DCR B Hex Code: 05 Before instruction Decrement operation A xx] F @)=0000 0000 B [oo [xx] C 01-0000 0001 ‘Sublraetion is performed in 2's complement (®)= 0000 0000 2's complement of = = isis sit rit titi After the execution of the DCR instruction register B will contain FFH; however, this sirvetion does not modify the CY fag. Example Decrement the AON, ents of memory location 2085, which presently holds[RPPENDIK F Assume the HL register contains 2085H. Instruction: DCRM Hex Code: 35 Before insirvtion Memory u 2D] Lone 2085 | a0} 2086 ‘After instruction nu [ooT ss] L 2084 2085 [OF 2086 DCX: Decrement Register Pair by 1 Opeode —Operand Bytes M-Cycles_—‘TStates ‘Hex Codes DCX — Reg. pair 1 6 Reg, Pair Hex ee DOB H (2B SPB Description ‘The contents of the specified register pair are decremented by 1, This in- struction views the contents of the two registers as a 16-bit number, Flags No flags are affected Example Register pair DE contains 2000H. Specify the contents of the entice register if itis decremented by I Instruction: = DCXD Hex Code: 1B. After subtracting from the DE register pir the answer is > OFT] & Example Write instructions to set the Zero flag when a register pair (such as BC) is sod as a down-counter: ‘To decrement the register pair, instruction DCX is necessary; instruction DCR is used for one register. However, instruction DCX does not set the Zera flag when the reg> ister pair goes to 0 and it continues counting indefinitely, The Zero flag can be set by us ing the following instructions.2006 INSTRUCTION SET 751 or BC pai DCX B _—__;Decrement register pair BC MOV A.C :Load accumulator with the contents of register C ORAB Set Zero flag if B and C are both 0 INZ Zero fag is not set, go back and decrement the contents of BC ‘pair DI: Disable Interrupts Opcode —Operand Bytes. M-Cyeles_—TStates Hex Code pI None 1 1 4 BB Description The Interrupt Enable flip-flop is reset and all the interrupts except the ‘TRAP (8085) are disabled. Flags No flags are affected, Comments: This instruction is commonly used when the execution of a code sequence ‘cannot be interrupted. For example, in critical time delays, this instruction is used atthe beginning of the code and the interrupts are enabled at the end of the cade, The 8085 ‘TRAP cannot be disabled. El: Enable Interrupts Opcode Operand Bytes. MeCycles_-‘TStates. Hex Code EL None 1 1 4 FB Deseription ‘The Interrupt Enable flip-flop is set and all interrupts are enabled. Flags No flags are affected, ‘Comments: After a system reset or the acknowledgment of an interrupt, the Interrupt Enable flip-flop is reset, thus disabling the interrupls. This instruction is necessary (0 reenable the interrupts (except TRAP). HLT: Halt and Enter Wait State Opcode —Operand Bytes. M-Cyele—TFStates Hex Code HLT None 1 2ormore 5 or more 16 Description ‘The MPU finishes executing the current instruction and halts any furth execution. The MPU enters the Halt Acknowledge machine cycle and Wait states ar i serted in every clock period. The address nnd the data bus are placed in the high impec‘182 APPENDIX F ance state. The contents of the registers are unalfected during the HLT state. An interrupt for reset is necessary o exit from the Halt state lags No flags are affected. IN: Input Data to Accumulator from a Port with 8-bit Address Opcode Operand Byles M-Cyeles States Hex Code IN 8itport address. 2 3 10 DB Description The contents of the input port designated in the operand are read and loaded into the accumulator: Flags No flags are affected Comments: The operand is an 8-bit address; therefore, port addresses ean range from OOH to FFH. While executing the instruction, a port address is duplicated on low-order (A,~Ao) and high-order (A,;-Aq) address buses. Any one of the sets of address lines can bbe decoded to enable the input port. INR: Increment Contents of Register/Memory by 1 Opcode —Operand Bytes. M-Cyeles_—"TStates. Hex Codes INR Reg, 1 1 4 Reg, Hex Mem. I 3 10 o oc le Ic x 2c x 3c >Ecmmone jon The contents of the designated register/memory are incremented by | and the results are stored in the same place. IF the operand is a memory Ic- cation, itis specified by the contents of HL register pair. Flags. S, Z, P, AC are modified to refleet the result of the operation. CY is not modified Example Register D contains FF, Specify the cont ‘ment. is of the register after the inere-‘8065 INSTRUCTION ser 183 Instruction: INRD Hex Code: 4 I 0 L 1 000 i LiL Cary Wo 0000 cY After the execution ofthe INR instruction, register D will contain 00H; however, no Carty flag is set. Example Increment the contents of memory location 2075H, which presently holds EH, Assume the HL register contains 2075H. Instruction: INRM Hex Code; 34 Before instruction Memory 4 OLS) 2074 2075] 2076 Ate instrueti 4 OL) L 2074 2075 | 2076 INK: Increment Register Pair by 1 Opeodle —Operand Bytes M-Cyeles Hex Codes INX Reg. pair 1 6 Reg. Pair Hex iy a Dea 13 ft soos Description The contents of the specified register pair are incremented by 1, The in siruetion views the contents of the two registers as a 16-bit number Flags No flags are affected Example Register pair HL. contains 9FFFH. Specify the contents of the if its incremented by 1 ire repister184 [APPENDIX F Instruction: INXH Hex Code: 23 After adding 1 to the contents of the HL pair the answer is H [aot oo} oL IMP: Jump Unconditionally Opcode —Operand Bytes M-Cycles_ States Hex Code IMP, I6-bit 5) 3 10 a Description The program sequence is transferred to the memory location specified by the 16-bit address. This is a 3-byte instruction; the second byte specifies the low-order byte and the third byte specifies the high-order byte Example Write the instruction at loc ‘memory location 2050H. jon 2000H to transfer the program sequence to Instruction: Memory Address Code Mnemonics 2000 C3 IMP 20508 2001 50 2002 20 ‘Comments: The 16-bit address ofthe operand is entered in memory in reverse order, the low-order byte first, followed by the high-order byte. Jump Conditionally Operand: 16-bit addess op Flag Hex Code Description Status Code M-Cycles/"T-States JC ump on Carry cy DA 2M if condition INC JumponNoCany CY D2 is not rue) a Jump on positive s 2 3M/IOT Gif condition JM Jump on minus s FA is ue) JPE ——Jumpon Parity Even P EA JPO Jump on Parity Odd P F2 Sump on Zero Zz cA INZ Jump on No Zero z a Flags No flags ae affected8086 INSTRUCTION SET 188 Comments: The 8085 requires only seven TEstates when condition is not true, For ex- ample, instruction JZ. 2050H will transfer the program sequence to location 2050 when the Zero flag is set (Z = 1) and the execution requires ten T:states. When the Zero flag is reset (Z. = 0), the execution sequence will not be changed and this requires seven states, LDA: Load Accumulator Direct Se hoes ee ical gitreas | acne LDA 16-bit a 4 1B 3A address Description The contents of a memory location, specified by a 16-bit address in tke ‘operand, are copied to the accumulator. The contents ofthe source are not altered, Ths is a S-byte instruction; the second byte specifies the low-order address and the third byte specifies the high-order address Flags No flags are affected Example Assume memory location 2050H contains byte F8H. Load the accumulator ‘with the contents of location 20504, Instruction; LDA 2050H_— Hex Code: 3A.5020 (note the reverse onder) a (EDX) F200 OB) Opeode —_Operand Byles M-Cyeles. States Hex Code LDAX = B/Dreg. pair 2 7 Reg. Hex BC 0A DE IA LDAX: Load Accumulator Indirect Description The contents of the designated register pair point (a, memory location ‘This instruction copies the contents of that memory location into the accumulator, The contents of either the register pair or the memory location are not altered Flags No flags are affected Example Assume the contents of register B = 20H, C = SOH, and memory location 2050H = 9FH. ‘Transfer the contents of the memory location 20S0H to the accumt lator186 {APPENDIX F Instruction: LDAX B Hex Code: 0A Register contents Memory Register contents before instruction contents after instuction Agel RXE ox _F. A [SFT XxX] F B [20 ww] Cc aso’ [or] BY Laomlesol ¢ LHLD: Load H and L Registers Direct Opeode —Operand Bytes. M-Cycles—‘PStates Hex Code LHLD 16-bit 3 5 16 2a address Description The instruction copies the contents of the memory location pointed out by the 16-bit address in register L and copies the contents of the next memory location in register H. The contents of source memory locations are not altered. Flags. No flags are affected. Example Assume memory location 2050H contains 90H and 20SIH consains O1H, ‘Transfer memory contents to registers HL. Instruction: LHLD 2050H Hex Code: 2A 5020 Memory contens Register contents before isrction ‘afer instruction 2050" [90 20s [ar 4 DOr) 4b LXI: Load Register Pair Immediate Opeode —Operand Bytes. M-Cycles. States Hex Code LXI Reg. pair, 3 3 10 Reg. 16-bit Pair Hex data B al D Ul H 2 SP 31 Description ‘The instruetion loads 16-bit data in the register pair designated in the ‘operand. This is @3-byte instruction; the second byte specifies the low-order byte and the third byte specifies the high-order byte. Flags No flags are affected8086 INSTRUCTION SET 187 Example Load the 16-bit data 20S0H in register pair BC. Instruction: LX1B,2050H Hex Cade: 01 50 20 ‘This instruction loads SOH in register C and 20H in register B, ‘Comments: Note the reverse order in entering the code of 16-bit data. This is the only in- struction that can directly load a 16-bit address in the stack pointer register MOV: Move—Copy from Source to Destination Opcode —Operand Bytes. M-Cycles—‘TStates. “Hex Code MOV Rds 1 1 4 See table below MoV MRs zi 7 MOV RUM Description This instruction copies the contents of the source register into the destina tion register; the contents of the source register are not altered. If one of the operands is a memory location, itis specified by the contents of HI. registers. Flags No flags are affected, Hex Code Source Location BocD EHLMA Destination Location pzremoos Example Assume register B contains 72H and register C contains 9FH. Transfer the contents of register C to register B. Instruction: MOV B,C Hex Cole: 41 Note the frst operand B specifies the destination and the second operand C specifies the Register contents Register contents before instruction after instruction ese a (rl sF] c158 [APPENDIC F Example Assume the contents of registers HI are 20H and SOH, respectively, Memory location 2050H contains 9FH. Transfer the contents of the memory location to register B. Instruction: MOV BM — Hex Code: 46 Register contents Memory Register contents before instaction contents afer instructor 2 [xxpx] c = B [9F [xx] c DB Pxxpoc] 20s (3 D [xxfxx} & a Pops] it” x Lots] o MVI: Move Immediate 8-Bit Opeode Operand Bytes. M-Cycles“‘TStates Hex Cade MYL Reg.,Datan 2 2 7 Reg. Hex Mem, Data 2 3 10 06 OE, 16 IE 26 2B 36 3B. zmoae >EC Description The 8-bit data are stored in the destination register or memery. If the ‘operand is a memory location, itis specified by the contents of HL registers Flags No flags are affected, Example Load 92H in register B. Instruction: MVIB,92H Hex Code: 06 92 This instruction loads 92H in register B. Example Assume registers Hand L contain 20H and SOH, respectively. Load 3AH in ‘memory location 2050H, Instruction: MVIM,3AH Hex Code: 36 Contents in after instruction HW L 2050 [34] H L0s INSTRUCTION SET 789 NOP: No Operation Opcode Operand Bytes. M-Cycles—FStates Hex Code NoP None 1 1 4 00 Description No operation is performed. ‘The instruction is fetched and decoded; how- ‘ever, no operation is executed. Flags No flags are affected, ‘Comments: The instruction is used to fill in time delays or to delete and inses i while troubleshooting. ORA: Logically OR with Accumulator Opcode Operand Bytes M-Cycles‘T-States Hex Code ORA Reg, 1 1 4 Mem, 1 B) 7 Hex BO BI Bo B3 Ba BS Bo By > reed oe Description The contents of the accumulator are logically ORed with the contents of the operand (register or memory), and the results are placed in the accumulator. Ifthe ‘operand is a memory location, its address is specified by the contents of HL registers. Flags Z, S, P are modified to reflect the results of the operation. AC and CY are reset Example Assume the accumulator has data byte 03H and register C holds byte 81H. Combine the bits of register C with the accumulator bits, Instruction: ORAC Hex Code: BI Register contents Register contents before instruct Logical OR after instruction 8Z AC PCY A [03 [XX] PF Sins F BL xx] 81 jc BL c760 [APPENDIX F Comments: The instruction is commonly used to 1 reset the CY flag by ORing the contents of the accumulator with itself 1 sot the Zero flag when 0 is loaded into the accumulator by ORing the contents of the accumulator with itself. combine bits from different registers, ORI: Logically OR Immediate Opcode —Opernand Bytes. M-Cyeles_ States Hex Code ORI bit 2 2 i F6 data Description The contents of the accumulator are logically ORed withthe bit data in the operand and the results are placed in the accumulator, Flags , Z, P are modified to reflect the results of the operation. CY and AC are rest. OUT: Output Data from Accumulator to a Port with 8-Bit Address Opcode Operand Bytes M-Cycles. ‘States. Hex Code OUT Bbitpon = 2 5 10 D3 address Deseri ‘The contents of the accumulator are copied into the output port specified by the operand, Flags No flags ae affected. ‘Comments: The operand is an 8-bit address; therefore, port addresses can range from OOH. to FFH, While executing the instruction, a port address is placed on the low-order address bus (Ay—Ap) as well asthe high-order address bus (A5~As). Any of the sets of address Tines can be decoded to enable the output por. PCHL: Load Program Counter with HL Contents Opcode —Operand Bytes. M-Cycles“T-States Hex Code PCHL None 1 1 6 F9 Description ‘The contents of registers H and L are copied into the program counter, The ‘contents of H are placed as a high-order byte and of Las a low-order byte. Flags No flags are affected8085 INSTRUCTION SEP 761 Comments: This instruction is equivalent to a I-byte unconditional Jump instruction. A program sequence can be changed to any location by simply loading the H and L.regis- ters with the appropriate address and by using this instruction. POP: Pop off Stack to Register Pair Opeode —Operand Byles M-Cycles—FStates “Hex Code POP — Reg. pair 2 10 Reg, Hex BCL Dot HEL Psw FL Deseription ‘The contents of the memory location pointed out by the stack pointer reg- ister are copied to the low-order register (such as C, E, L, and flags) of the operand, ‘The stack pointer is incremented by 1 and the contents ofthat memory location are copied (> the high-order register (B, D, H, A) of the operand. The stack pointer register is again in ‘eremented by 1 Flags No flags are modified. Example Assume the slack pointer register contains 2090H, data byte FS is stored in ‘memory location 2090H, and data byte 01H is stored in location 20911. Transfer the con- tents of the stack to register pair H and L, Instruction: POP H Hex Code: BL Register contents Stack Register contents before instruction ‘contents after instrueti H xx Dx] 2090 [FS H (ores J sp|__2090 2091 [OL sp [2092 2002 [_ ] Comments: Operand PSW (Program Status Word) represents the contents of the acct ‘mutator and the flag register; the accumulator is the high-order register and the flags are the low-order register, [Note that the contents of the source, stack locations, are not altered after the PO? instruction762 2PPENDIX F PUSH: Push Register Pair onto Stack Opcodle —Operand Bytes. M-Cycles_— ‘States. Hex Code PUSH = Reg. pair 3 2 Reg. Hex a DDS i bs Psw FS Description ‘The contents of the register pair designated in the operand are copied into the stack in the following sequence. The stack pointer register is decremented and the contents of the high-order register (B, D, H, A) are copied into that location. The stack pointer register is decremented again and the contents of the low-order registe-(C, B, Ly flags) are copied to that location. Flags No flags are modified. Example Assume the stack pointer register contains 2099H, register B contains 32H ‘and register C contains 57H. Save the contents of the BC register pair on the sack, Instruction: PUSH B Hex Code: C5 Register contents ‘Stack contents, Register contents before instruction after instruction after instruction BL 32] s7]c 2097 | 57 B32 57 Je 2008 [32 sP[_2099) pants sp[_207_] nts: Operand PSW (Program Status Word) represents the contents ofthe aecu- mulator and the flag register; the accumulator isthe high-order register and the flags are the low-order register Note that the contents of the source registers are not altered after the PUSH in- struction RAL: Rotate Accumulator Left through Carry Opeode —Operand Bytes M-Cycles.-‘PStates Hex Code RAL None 1 1 4 7 (ion Each binary bit of the accumulator is rotated left by one position through the Carry flag. Bit D, is placed in the bitin the Carry flag and the Carry flag is placed in the least significant position Dy, Flags CY is modified according to bit Dy. S, Z, AC, P are not affectedaS INSTRUCTION Se 763 Example Rotate the contents of the accumulator through Carry, assuming the aecume- lator has A7H and the Cary flag is reset Instruction: RAL_—-Hex Code: 17 oy oo) Accumulator content Dy De Ds Dy Ds Dz Dy Dy before instruction (Jo Ti Topor iy it ‘Accumulator contents fo Tr To ToTiT iT iT 9) alter instruction Comment; This instruction effectively provides a 9-bit accumulator. The original contents of the accumulator can be restored by using instruction RAR (Rotate Accumulator Right tough Carty). However; the contents will be modified if the instruction RRC (Rota Accumulator Right) is used to restore the contents RAR: Rotate Accumulator Right through Carry Opcode —Operand —Bytes—-M-Cycles—TStates—_ Hex Code RAR None 1 1 4 IF Description Each binary bit ofthe accumulator is rotated right by one positon through the Carry flag, Bit Dy is placed in the Cary flag and the bit in the Carry flag is placed in the most significant position, Dy, Flags CY is modified according to bit Dp, S, Z, P, AC are not affected Example Rotate the contents of the accumulator assuming it contains A7H and the Cay flag is reset to 0. Instruction: RAR Hex Code: IF cy fo) Accumulator contents ie Dy Ds D.9D, D; Di Oy before instruction TJo [i To T cy a Accumulator contents (0-1 [OT 7 OL oa] a) after instruction164 APPENDIX F RLC: Rotate Accumulator Left Opcode Operand —_Bytes_-M-Cyeles—TStates Hex Code RLC None 1 1 4 o7 Description Each binary bit ofthe accumulator is rotated left by one position. Bit Dy is placed in the position of Dy as well as in the Carry fla. Flags CY is modified according to bit D,. S, Z, P, AC are not affected Example Rotate the contents ofthe accumulator left, assuming it contains ATH and the Carry flag is reset to 0, Instruction: LC Hex Code: 07 cy fo} ‘Accumulator contents Dy_Dg_Dy_Dy Dy Dy Dy Dy before instruction Tr Io Ti Tofol itil i cy Accumulator contents ft TeTotit at it) after instruction ‘Comments: The contents of bit D, are placed in bit Dp, and the Carry flag is modified ac- cordingly, However, the contents of the Carry are not placed in bit Dy as in instruction RAL. RRC: Rotate Accumulator Right Opeode Oper Bytes M-Cycles "T-States Hex Code RRC None 1 ' 4 oF Deseription Bach binary bit of the accumulator is rotated right by one position, Bit Dy is placed in the position of D, as well as in the Carry flag, Flags CY is modified according to bit Dy, S, Z, P, AC are not affected. Example Rotate the contents of the accumulator right, iit contains ATH and the Carry flag is reset to 0,‘9086 INSTRUCTION SET 165 Instruction: RRC Hex Code: OF cy (0) Accumulator contents, D; De Ds Dy Ds Ds Dy Dy before instruction to [i Toft of iy ii cy oO Accumulator contents Uy Toi Tot of ii) after instruction ‘Comments: ‘The contents of bit Dp are placed in bit D,, and the Carry flag is modified accordingly. However, the contents of the Carry are not placed in bit D,, as in the in- siruetion RAR RET: Return from Subroutine Unconditionally Opcode —Operand Bytes M-Cycles_— States Hex Code RET. None 1 3 10 o Description The program sequence is transferred from the subroutine 10 the calling program, The two bytes from the top ofthe stack are copied into the program counter and the program execution begins at the new address, The instruction is equivalent to POP Program Counter. Flags No flags are affected Example Assume the stack pointer is pointing to location 2095H. Explain the effect of the RET instruction ifthe contents of the stack locations are as Follows: 2095 [50 2006 [ad After instruction RET, the program execution is transferred to location 2050H and the stack pointer is shifted to location 2097H, Comments: This truction is used in conjunction with CALL or conditional call in-166 op Code RC RNC RP RM. RPE RPO RZ RNZ {APPENDIX F Return Conditionally Flag Hex Deseription Status Code M.Cycles/'T-States, Return on Carry bs Return with No Carry DO 1/6 (if condition is not true) Return on positive FO 3/12 (if condition is tue) Return on minus F8 Note: Ifcondition is not true, it eentinues Retumn on Parity Even 18 the sequence and thus recuites Return on Parity Odd BO. fower Tstates Return on Zero, cs If condition is tue, it returns to the Return on No Zero co calling program and thus requires more Tales. Flags No flags are affected, RIM: Read Interrupt Mask Opcode Operand Bytes. M-Cycles—"T-States Hex Code RIM None I 1 4 2 Description This is a multipurpose instruction used to read the status of interrupts 7.5, 665, 5.5 and to read serial data input bit. The instruction loads eight bits in the accumula tor with the following interpretations Dy Ds Dy Ds Dr Dh Dy Le [is [is [ue [7s|s]ss Serial input Interrupt data bit masked if bit Interrupts Interrupt Enable pending if « flip-flop is set bi it bit= 1 Flags No flags are affected, nple After the execution of instruction RIM, the accumulator contained 49H.9055 INSTRUCTION SET 161 W dH = 9 1901001 S175 is peming Ls ss mstea Interrupt Enable RST 75 and 65 flip-flop is set '— are enabled RST: Restart Bytes M.Cyeles ‘TStates I 3 R Restart Opeode/Operand Binary Code Hex Code Address (H) RSTO 11 000 111 cr ‘0000 RST I 11 001 tit cr 0008 RST2 11 010 111 DT 010 RST3 11 our iit DF 018 RST 4 11 100 111 E7 (0020 RSTS 11 tor ait EF 028 RST6 ie tio att FT 0030 RST7 re ouit att FF 0038 Description The RST instructions are equivalent to I-byte call instructions to one ofthe eight memory locations on page 0. The instructions are generally used in conjunction ‘With interrupls and inserted using external hardware. However, these can be used as sof ‘ware instructions in a program (o transfer program execution to one ofthe eight location Flags No flags are affected, Additional 8085 Interrupts The 8085 has four additional interrupts and these inte rupts generate RST instructions internally and 1s do not require any extemal hardware, “These instructions and their Restart addresses are as Follows: Restart Interrupts Address ‘TRAP 24H RSTSS ——2CH RST 65 34H RST 75 3CH768 APPENDIX F SBB: Subtract Source and Borrow from Accumulator Opcode —Operand Byles M-Cyeles—T-States Hex Code sBB Reg, 1 ' 4 Reg, Hex Mem. I 2 7 98 ” 9A 9B 9c 9D 9E oF >Ermmong, Dese ts of the operand (register or memory) and the Borrow flag are subtracted from the contents of the accumulator and the results are placed in the acct- ‘mutator: The contents of the operand are not altered; however, the previous Borrow flag is reset Flags All flags are altered (o reflect the result of the subtraction, Example Assume the accumulator contains 37H, register B contains 3FH, and the Borrow flag is already set by the previous operation, Subiract the contents of B with the borrow from the accumulator. Instruction: SBBB Hex Code: 98 ‘The subiraction is performed in 2's complement; however, the borrow needs tobe addled first to the subtrahend: @: 3F Borrow: +1 Subtrahend: ~ 4OH=0 100 0000 2s complement of 40} 0 0000 “w oui Orr t=FH Complement Carry: oli ‘The Borrow flag is set to indicate the result is in 2's complement. The previous Borrow flag is reset during the subtraction, SBI: Subtract Immediate with Borrow Opcode Operand Bytes M-Cycles—T-States Hex Code SBI Bit 2 2 7 DE data086 INSTRUCTION SET 169 Description The 8-bit data (operand) and the borrow are subtracted from the conten's ‘of the accumulator, and the results are placed in the aceumulator, Flags All flags are altered to refleot the result of the operation. Example Assume the accumulator contains 37H and the Borrow flag is set, Subtract 25H with borrow from the accumulator, Instruction; SBL2SH Hex Code: DE 25 (Data): 2541 + (Borrow): _1H Subirahend!: 26H 2's complement of 2641 (A) 37H 0 0 L sets un 1h or Lt 00 00 mrs nplement Camry’ Flags: ateale es 0 1 o 0 0 A 0 SHLD: Store H and li Registers Direct Opeode —Operand Bytes M-Cycles-—F-States Hex Code SHLD 16-bit 3 5 16 2 address Description The contents of register L are stored in the memory location specified by the 16-bit address in the operand, and the contents of H register are stored in the next memory location by inerementing the operand, The contents of registers HL are not tered. This isa 3-byte instruction; the second byte specifies the low-order address and the thin byte specifies the high-order address, Flags No flags are affected Example Assume the H and L registers contain O1H and FFH, respectively, Store the contents at memory locations 2050H and 2051 Instruction; SHLD 20S0H_ Hex Code: 22-50 20 Register contents Memory and register contents before instruction = flr nsrcton (ODTRE) 12050 [FF H [OLDE] L 2051 [4710 APPENDIX F SIM: Set Interrupt Mask Opcode —Operand Bytes M-Cycles_-‘TStates. Hex Code sim None 1 1 4 30 Deseription This is a multipurpose instruction and used to implement the $285 inte rupts (RST 7.5, 6.5, and 5.5) and serial data output. ‘The instruction interprets the accumulator contents as Follows: DDD; Dyes Di aD HED, SDE XXX MSE [ M75 [M65 [M53] flp-op if D, = 1 ir bits = 1 Serial data Enable Mask Set 1 = Enable Enable if 0= Disable D=I 1 SOD—Serial Outpot Data: Bit Dy of the accumulator is latched into the SCD output line and male available (0 a serial peripheral if bit Dy = 1 5 SDE—Serial Data Enable: If this bit= 1, it enables the serial output, To implement se- rial output, this bit needs to be enabled, © XXX—Don't Care 1 R7.S—Reset RST 7.5: If this bit ‘control to reset RST 7.5, O MSE—Mask Set Enable: If this bit is high, it enables the functions of bits Ds, Dy, Dp. ‘This is a master control over all the interrupt masking bits. If this bit is low bits Ds, Dj, and Dy do not have any effect on the masks. 0 M7S—D, =0, RST 7.5 is enabled RST 755 is masked or disabled |. RST 7.5 flip-flop is reset. This isan sitio 1D M6.5—D, = 0, RST 6:5 is enabled = 1, RST 655 is masked or disabled 1D MS5—Dy = 0, RST 5.5 is enabled |. RST 5.5 is masked or disabled Example Write instructions to enable interrupt RST 5.5 and mask other interrspts. Instruction: MVIA,OEH — :Bits Dy = 1 and Dy =0 SIM Bnable RST 5.5 Example ATTY receiver line is connected to the SOD pin of the 8085, Disab all {errupts and send! START bit (logic 0) to TTY without affeeting interrupt masks,8086 INSTRUCTION SET 77 Instructions: MVEAMOH —:D,=0, START bit at logic 0 1, Enables serial output bit Dy sD; =0, Does not affect masks SIM ‘Send START bit Comments: This instruction does not affect TRAP interrupt SPHL: Copy H and L Registers to the Stack Pointer Opcode —Operand Byles. M-Cyeles_—TStates Hex Code SPHL None 1 1 6 (8085) 9 5 (8080) Description ‘The instruction loads the contents of the H and L registers into the stack pointer register; the contents of the H register provide the high-order address, and the contents of the L register provide the low-order address. The contents ofthe Hand L re3~ isters are not altered Flags No flags are affected. STA: Store Accumulator Direct Opeode —Operand Byles M-Cycles—“T-States— Hex Code STA 16-bit 3 4 B 32 Description The contents of the accumulator are copied to a memory location specified by the operand. This is a 3-byte instruction; the second byte specifies the low-order at ‘dress and the thitd byte specifies the high-order address Flags No flags are affected. Example Assume the accumulator contains 9FH. Load the accumulator contents into ‘memory location 2050H. Instruction: STA 2050H Hex Code: 325020 Register contents Memory contents before instuction after instruction A [oF [xx] F 2050 [9F112 [APPENDIX F STAX: Store Accumulator Indirect Opcode Operand Byles M-Cyeles—TStates Hex Code STAX B/D reg. 1 2 7 Reg, Hex pair B D Description The contents ofthe accumulator ate copied into the memory location spec: ified by the contents of the operand (register pair). The contents of the accumulator are not altered, Flags No flags are affected, Example Assume the contents ofthe accumulator are F9H and the contents of registers B and C are 20H and S011, respectively. Store the accumulator contents in memory loca tion 2050H, Instruction; STAX B Hex Code: 02 Register contents Register and memory contents before instruction after instruction A [po [xx] F 2050 A Xx] F B [20 [50 | c B [20 [50] c ‘Comments: This instruction performs the same function as MOV A.M except this in- struction uses the contents of BC or DE as memory pointers, STC: Set Carry Opcode —Operand Bytes. M-Cycles.—TStates Hex Code sTC None 1 1 4 37 Description The Carry flag is set to 1 Flags No other lags are affected113 8088 INSTRUGTION SET SUB: Subtract Register or Memory from Accumulator Opeode —Operand Bytes. M-Cycles.TFStates. Hex Code SUB Reg, 1 1 4 Reg. Hex Mem. 1 2 1 90 91 oy 93 94 95 96 7 >Ermmcos Description The contents of the register or the memory location specified by the ‘operand are subiracted from the contents ofthe accumulator, andthe results are placed in the accumulator The contents of the source are not altered. Flags All lags are affected to reflect the result of the subtraction. Example Assume the contents of the accumulator are 37H and the contents of register Care 40H. Subtract the contents of register C from the accumulator, Instruction: SUBC Hex Code: 91 (©: 40H= 0100 0000 2s-complement (C= 1100 0000 (Ay STH FH Complement Carry Flags: S P=0, “The result, as @ negative number, will be in 2's complement and thus the Carry (Borrow) flag is se. SUI; Subtract Immediate from Accumulator Opcode Operand Bytes. M-Cycles,—T-States_— Hex Code sur 2 2 7 D6 Description ‘The §-bit data (the operand) are subtracted from the contents of the accu ‘mulator, and the results are placed in the accumulator114 ‘APPENDIX F Flags All flags are modified to reflect the resulls of the subtraction. Example Assume the accumulator contains 40H. Subtract 37H from the accamulator. Instruction: SUI37H Hex Code: D637 Subirahend: 37H 2's complement of 37H oor 1100 0100 wv 0000 Complement Carry: 0 0000 Flags: $= 0,Z=0, AC Ley (A): 40h 09H XCHG: Exchange H and L with D and E, Opcode Operand Bytes M-Cycles—"TStates. Hex Code XCHG None 1 I 4 EB Description The contents of register H are exchanged with the contents of register D, !and the contents of register L are exchanged with the contents of register E. Flags No flags are affected XRA: Exclusive OR with Accumulator Opcode —Operand Bytes M-Cycles— States. Hex Code XRA Reg 1 1 4 Re Mem. a 7 8 Hex AB Ao AA AB AC AD AE AF >zramcos of the operand (register or memory) are Exclusive ORed with laced in the accumulator, “he con- Description ‘The conten the contents of the accumulator, and the results are {ents of the operand are not altered,29085 INSTRUCTION SET 718 Flags Z, S, P are altered (o reflect the results of the operation. CY and AC are reset. Example Assume the contents of the accumulator are 77H and of register D are 56H. [Exclusive OR the contents ofthe register D with the accumulator. Instruction; XRAD Hex Cole: AA (A): 77H XRI: Exclusive OR Immediate with Accumulator Opcode —Operand Bytes M-Cycles—TStates. Hex Code XxRI 8.bit 2 2 7 EE data Description ‘The 8-bit data (operand) are Exclusive ORed with the contents of the ac- ‘cumulator, and the results are placed in the accumulator. Flags Z, S, P are altered to reflect the results ofthe operation. CY and AC are reset. Example Assume the contents of the accumulator are 8FH. Exclusive OR the contents of the accumulator with A2H. Instruction: XRIA2H Hex Code: BE A2 (Ay: 8FH=1000 1111 (Data): AH= 1010 0010 Exclusive OR: ooro trot Flags: S = 0, Z=0, P CY =0,AC=0 XTHL: Exchange H and L with Top of Stack Opcode —Operand Byles M-Cycles—TStates. Hex Code XTHL None, 1 5 16 BB716 ‘APPENDIX F Description ‘The contents of the L register are exchanged with the stack location pointed out by the contents of the stack pointer register. The contents ofthe H register are exchanged with the next stack location (SP + 1); however, the contents of the stack pointer register are not altered Flags No flags are affected, Example ‘The contents of various registers and stack locations are as shown Stacks n[a2[ 57] L 2095 [38 sp|_ 2095 2006 [67 strate the contents of these registers after instruction XTHL, Register contents after XTHL Stach uifo7 | 38] 2095 sp[_ 2095 2096 088 Instruction Summary: Hexademical Order Hex Mnemonic [ Hex Mnemonie | Hex Hex «NOP 1 uxt Da a oF LxIB. n stax | 2 a on ee | tee 3 OINSESE ee 4 owe > | 2m 34 INR M OIRO 15 Dak bes! 35 «CRM 0 DCR OB 6 ov > | 26 3500 MVM % MB 7 RAL 2 sy ste 7 REC 9 pap v-| 20 39 «DAD SP © DAD B IA wpaxD | 2a BA LDA oA tpaxe | ip cx Do 3B DCX SP 0B (Dx 1c we & | 2c 3c INR A oc nk c | wD opcr EB |p 3D CRA ® wc jis mw oP 3B MWA c IF RAR 3F ewe 20 _RIM 40 Movap