SNUVM Reference Manual
Release 2.0
February 2011
Table of Contents
1. What is SNUVM
2. How To Compile and Run SNUVM
3. Assembly Instructions and Directives
4. Memory Layout
5. Alignment
6. Sample Codes
1. What is SNUVM?
SNUVM, the SNU Virtual Machine, is a virtual machine that directly executes assembly code. The
instruction set architecture (ISA) of SNUVM is similar to the ARM ISA, but much simpler. SNUVM is
written in Java and requires the J2SE Java Runtime Environment (JRE).
2. How To Compile and Run SNUVM
Please, see the installation guide at http://snuvm.snu.ac.kr/.
3. Assembly Instructions and Directives
3.1. Instructions
Instructions Descriptions
<Rd>: R0 ~ R15
<Operand>: an 8-bit integer constant or a register
MOV <Rd>,<Operand>
The 8-bit integer constant is prefixed with ‘#’, for example,
#0x24
#-0x13
#127
Move the value of <Operand> to the destination register <Rd
For example,
MOV R0, #32
MOV R1, #-25
MOV R2, R3
<Rd>: R0 ~ R15
<Rn>: R0 ~ R15
<Operand>: an 8-bit integer constant or a register
Add the value of <Operand> to the value of register <Rn>, an
ADD <Rd>,<Rn>,<Operand> stores the result in the destination register <Rd>.
For example,
ADD R2, R3, #12
ADD R2, R2, #-1
ADD R0, R2, R1
<Rd>: R0 ~ R15
<Rn>: R0 ~ R15
<Operand>: an 8-bit integer constant or a register
Subtract the value of <Operand> from the value of register
SUB <Rd>,<Rn>,<Operand> <Rn>, and stores the result in the destination register <Rd>.
For example,
SUB R2, R3, #12
SUB R2, R2, #-1
SUB R0, R2, R1
<Rd>: R0 ~ R15
<Rn>: R0 ~ R15
<Rs>: R0 ~ R15
Multiply the contents of <Rm> and <Rs>, and stores the resu
in the destination register <Rd>
MUL <Rd>,<Rm>,<Rs> The least significant 32 bits of the result are written to the
destination register
For example,
MUL R0, R1, R2
MUL R0, R0, R3
MUL R4, R5, R5
<Rd>: R0 ~ R15
<Rn>: R0 ~ R15
LDR <Rd>, [<Rn>]
Make data located at the address contained in <Rn> to be
loaded into the destination register <Rd>
For example,
LDR R0, [R2]
LDR R1, [R3]
<Rd>: R0 ~ R15
<Rn>: R0 ~ R15
Loads a byte from memory and zero-extends it to form a 32-b
word, and then stores the result to the destination register
LDRB <Rd>, [<Rn>]
<Rd>.
For example,
LDRB R0, [R2]
LDRB R1, [R3]
<Rd>: R0 ~ R15
<Rn>: R0 ~ R15
Make data from the register <Rd> to be stored to the memory
STR <Rd>, [<Rn>] location with the address contained in <Rn>
For example,
STR R0, [R2]
STR R1, [R3]
<Rd>: R0 ~ R15
<Rn>: R0 ~ R15
Makes 8-bit data from the register <Rd> (Rd[7:0]) to be store
STRB <Rd>, [<Rn>] to the memory location with the address contained in <Rn>.
For example,
STRB R0, [R2]
STRB R1, [R3]
<Rn>: R0 ~ R15
<Operand>: an 8-bit integer constant or a register
Compare the value of <Operand> with the value of register
<Rn>, and (conceptually) store the result of the operation <R
- <Operand> in CPSR.
CMP <Rn>,<Operand>
Negative (N), Zero (Z), Carry-out (C), oVerflow (V)
For example,
CMP R0, #0
CMP R4, R0
<label> is a name.
Converted by the assembler to the target address of the branc
Label: some text followed by a colon, like "L1:"
B <label> A named location in the code
Cause a jump to the target address labeled with “<label>:”
For example,
B loop
B done
Place this instruction at the end of your program.
B halt
‘halt’ is a reserved name.
<cond>: the condition under which the instruction is executed
Causes a branch to the target address if the condition matche
the result of the previous CMP (the condition flags in CPSR)
For example,
CMP R1, R2 makes BLT L1 taken if R1 < R2
B<cond> <label>
For example,
CMP R1, R2
BEQ done
CMP R5, #0
BNE loop
Cause a jump to the target address
Store the return address in the link register, LR
BL <label>
For example,
BL printInt
<Rd>: R0 ~ R15
<Rn>: R0 ~ R15
<Operand>: an 8-bit integer constant or a register
AND <Rd>,<Rn>,<Operand> Logical bitwise AND of two 32-bit values
For example,
AND r0, r1, r1
AND r0, r1, #-128
<Rd>: R0 ~ R15
<Rn>: R0 ~ R15
<Operand>: an 8-bit integer constant or a register
ORR <Rd>,<Rn>,<Operand>
Logical bitwise OR of two 32-bit values
For example,
ORR r0, r1, r1
ORR r0, r1, #127
<Rd>: R0 ~ R15
<Rn>: R0 ~ R15
<Operand>: an 8-bit integer constant or a register
EOR <Rd>,<Rn>,<Operand> Logical exclusive OR of two 32-bit values
For example,
EOR R0, R0, R0
EOR R0, R1, #127
3.2. Pseudo Instructions
Pseudo Instructions Descriptions
<Rd>: R0 ~ R15
<label>: the name of a symbol
Load the value store at <label> to <Rd>
LDR <Rd>, <label>
For example,
LDR R0, addr_screen
LDR R4, fvar
<Rd>: R0 ~ R15
<label>: the name of a symbol
<const>: an integer constant
LDR <Rd>,
<label>+<const> Load the value stored at foo+<number> to <Rd>
For example,
LDR r0, foo + 4
<Rd>: R0 ~ R15
<label>: the name of a symbol
Load the address at <label> to <Rd>
LDR <Rd>, =<label>
For example,
LDR R0, =addr_screen
LDR R4, =fvar
<Rd>: R0 ~ R15
<const>: a 32-bit integer constant
Load <const> to <Rd>
LDR <Rd>, =<const>
For example,
LDR R0, =0x12345678
LDR R4, =1000
<Rd>: R0 ~ R15
<label> is the name of a symbol
Load the address at <label> to <Rd>
ADR <Rd>, <label>
For, example,
ADR R0, addr_screen
ADR R4, fvar
No operation
NOP
It assembles to MOV R0, R0
3.3. Assembler Directives
Directives Descriptions
Aligns the next piece of code or data to a boundary
.align n For example,
.align 2
.align 0
Store the listed value(s) as 8-bit bytes
.byte <byte1> {,<byte2>} For example,
.byte 0xff
.byte 0x11, 0x22, 0x33
Inserts a list of 16-bit values as data into the assembly
.hword <hword1> {,<hword>} For example,
.hword 0xffff
.hword 0x1111, 0x2222, 0x3333
Create a (4-byte) word in the location where “.word” is placed. I
<number> exists, the number is stored in the location when the
word is created
.word <number1>
{,<number2>}
For example,
.word 0xffffffff
.word 0x11111111, 0x22222222, 0x33333333
Create a (4-byte) word in the location where “.word” is placed. I
<label> exists, the address at <label> is stored in the location
when the word is created
.word <label>
For example,
.word fvar
Inserts the string as data into the assembly
.ascii "<string>"
For example,
.ascii "Hello, world!"
As for .ascii but follows the string with a zero byte
.asciz "<string>"
For example,
.asciz "Hello, world!"
3.4. Labels and Comments
<label> is the name of a symbol to store the address of the instruction. The
assembler allows programmers to associate arbitrary names (labels or symbols)
with memory locations. Usually, every constant and variable is given a name so
instructions can reference those locations by name. <label> can be any alphabetic
characters A to Z and a to z, the digits 0 to 9, as well as "_", "." and "$". Note,
however, that you cannot start a symbol with a digit. Label is case-sensitive.
SNUVM allows you to place comments in a source program. Comments have no
effect on the actual program. They help you to read, understand and document the
program. Whole line starting with a character '@' is ignored by assembler.
For example, (red color: labels, green color: comments)
adr r0, msg @ get the address of msg
ldr r1, addr_screen @ get the value of addr_screen
loop: ldrb r2, [r0]
cmp r2, #0
beq done
strb r2, [r1]
add r0, r0, #1
add r1, r1, #1
b loop
done:
b halt
addr_screen: .word 0xd0000
msg: .asciz "Hello, world!"
4. Memory Layout
Systems based on SNUVM typically divide memory into two parts(see Figure below). The
first part, near the bottom of the address space (starting at address 0x8000), is for the code
and data. 0xD0000 ~ 0xD063F area is reserved for Memory-Mapped I/O for the screen.
5. Alignment
SNUVM instruction and data alignment requirements
• Only aligned accesses are supported
• Instruction
◦ 32-bit word aligned on a 4-byte boundary
• Data
◦ 4-byte word aligned on a 4-byte boundary
◦ 2-byte halfword aligned on a 2-byte boundary
6. Sample code
Sample1: Hello, World!
adr r0, msg
ldr r1, addr_screen
loop: ldrb r2, [r0]
cmp r2, #0
beq done
strb r2, [r1]
add r0, r0, #1
add r1, r1, #1
b loop
done:
b halt
addr_screen: .word 0xd0000
msg: .asciz "Hello, world!"
Sample2: The Sum of 10 Integers
MOV R1, #0
MOV R2, #0
ADD R2, R2, #1
ADD R1, R1, R2
ADD R2, R2, #1
ADD R1, R1, R2
ADD R2, R2, #1
ADD R1, R1, R2
ADD R2, R2, #1
ADD R1, R1, R2
ADD R2, R2, #1
ADD R1, R1, R2
ADD R2, R2, #1
ADD R1, R1, R2
ADD R2, R2, #1
ADD R1, R1, R2
ADD R2, R2, #1
ADD R1, R1, R2
ADD R2, R2, #1
ADD R1, R1, R2
ADD R2, R2, #1
ADD R1, R1, R2
B halt
