Electronics Engineering

O. N. Pandey

Electronics Engineering
Second Edition

123
O. N. Pandey
JSS Academy of Technical Education
Noida, India

ISBN 978-3-030-78994-7 ISBN 978-3-030-78995-4 (eBook)

https://doi.org/10.1007/978-3-030-78995-4
Jointly published with ANE Books India
ISBN of the ANE Books India’s edition: 978-9-382-12780-2

1st edition: © Ane Books Pvt. Ltd. 2016

2nd edition: © The Editor(s) (if applicable) and The Author(s), under exclusive license to Springer Nature
Switzerland AG 2022
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The publishers, the authors, and the editors are safe to assume that the advice and information in this
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Dedicated to my Parents
Smt. Kalavati Devi
and
Shri. Deo Murti Pandey
Who have given so much to me
Preface to Second Edition

I am very thankful to the students and faculty members who have made it one of the
most popular books. There has been a need to add one more chapter on Personal
Simulation Program with Integrated Circuit Emphasis (PSPICE); therefore, one
chapter on PSPICE has been included in this edition. PSPICE is quite vast topic as
such it is treated in its basic and simplified manner. Needless to say that all the
errors found and reported have been corrected. Six more latest university question
papers have been added for the benefit of the students.
I appreciate and thank the students and faculty members for giving their
encouraging feedbacks. I am also thankful to Dr. T. N. Nagabhushan, Principal of
JSS Academy of Technical Education, Noida, for all the encouragements given
during the second edition period.

Noida, India Dr. O. N. Pandey

vii
Preface to First Edition

Development in Electronics Engineering are taking place today at an awesome

place. Therefore, it has become essential to understand the fundamentals of
Electronics. This book presents fundamentals of electronics.
The book has been written after going through a large number of references. The
objective has been to present the matter in simple, straight forward and easy form
without losing any important information and detail. Appendices have been added
to cover electronic symbols, abbreviations, diagrammatic symbols, various
parameter units, conversion factors, periodic table of elements, conduction prop-
erties round copper conductor data, standard resistors and capacitors, electronic
formulae, equivalent circuits and characteristics. Glossary of electronic terms has
been added for quick understanding of electronic terms. Two examination papers
with solutions have also been added.
I am very thankful to Dr. Narendra Kumar and Prof. Dinesh Chandra of JSS
Academy of Technical Education, Noida for encouragement leading to such tech-
nical contribution.
I appreciate the cooperation and help extended by my wife Mrs. Ranjana
Pandey, Son Nishith Pandey, relatives and friends. I also appreciate the efforts and
help extended by Mrs. Shilpi Gadi, Mrs. Amita Rana, Ms. Paro Bajpai, Mr. Rahul
Gupta and others.

Noida, India Dr. O. N. Pandey

ix
Contents

1 Basics of Electronics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Electronic Charge and Current . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 Electronic Circuit Components . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3.1 Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3.2 Inductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3.3 Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.4 Voltage and Current Relationships . . . . . . . . . . . . . . . . . . . . . . . 5
1.5 Work, Power and Energy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.6 Si Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.7 Voltage and Current Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.8 Semiconductor Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.8.1 Intrinsic Semiconductors . . . . . . . . . . . . . . . . . . . . . . . . 13
1.8.2 Extrinsic Semiconductors . . . . . . . . . . . . . . . . . . . . . . . 13
1.9 P–N Junction and Depletion Layer . . . . . . . . . . . . . . . . . . . . . . 15
1.9.1 P–N Junction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.9.2 Depletion Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.9.3 Forward Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.9.4 Reverse Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2 Semiconductor Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.1 Semiconductor Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.2 V–I Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.3 Ge, Si and GaAs Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 24
2.4 Ideal and Practical V–I Characteristics . . . . . . . . . . . . . . . . . . . . 24
2.5 Diode Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.5.1 Forward Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.5.2 Transition and Diffusion Capacitance . . . . . . . . . . . . . . 28
2.5.3 Diode Equivalent Circuit . . . . . . . . . . . . . . . . . . . . . . . 29

xi
xii Contents

2.6 Diode Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

2.6.1 Repetitive Peak Current (Ipeak) . . . . . . . . . . . . . . . . . . . 30
2.6.2 Average Current (Iav) . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.6.3 Peak Inverse Voltage (VR) . . . . . . . . . . . . . . . . . . . . . . 31
2.6.4 Steady-State Forward Current (IF) . . . . . . . . . . . . . . . . . 31
2.6.5 Peak Forward Surge Current (IFS) . . . . . . . . . . . . . . . . . 31
2.6.6 Static Maximum Voltage Drop (VFM) . . . . . . . . . . . . . . 31
2.6.7 Continuous Power Dissipation (P) . . . . . . . . . . . . . . . . . 31
2.6.8 Reverse Recovery Time (trr) . . . . . . . . . . . . . . . . . . . . . 31
2.7 P–N Junction (Diode) as Rectifiers . . . . . . . . . . . . . . . . . . . . . . 33
2.7.1 Half-Wave Rectifier . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.7.2 Full-Wave Rectifier . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2.8 Ripple Efficiency and Regulation . . . . . . . . . . . . . . . . . . . . . . . . 42
2.9 Efficiency of Full-Wave Rectifier . . . . . . . . . . . . . . . . . . . . . . . . 42
2.10 Filters for Rectifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.11 Clipping Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
2.12 Clamping Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
2.13 Voltage Multipliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
2.13.1 Voltage Doubler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
2.13.2 Half-Wave Voltage Doubler . . . . . . . . . . . . . . . . . . . . . 53
2.13.3 Full-Wave Voltage Doubler . . . . . . . . . . . . . . . . . . . . . 54
2.13.4 Voltage Trippler and Quadrupler . . . . . . . . . . . . . . . . . . 56
2.14 Zener Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
2.14.1 Zener Diode Functioning . . . . . . . . . . . . . . . . . . . . . . . 57
2.14.2 Zener Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
2.14.3 Zener “ON” and “OFF” States . . . . . . . . . . . . . . . . . . . 58
2.14.4 Zener Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
2.15 Temperature Coefficient . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
2.15.1 Zener Diode Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 62
2.16 Zener Diode Application as Shunt Regulator . . . . . . . . . . . . . . . 63
2.17 Diodes for Optoelectronics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.17.1 Light-Emitting Diodes (LEDs) . . . . . . . . . . . . . . . . . . . 64
2.17.2 Photodiode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.17.3 Optocoupler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.18 Other Types of Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
2.18.1 Schottky Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
2.18.2 Varactor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
2.18.3 Varistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
3 Bipolar Junction Transistor (BJT) . . . . . . . . . . . . . . . . . . . . . . . . . . 79
3.1 Basic Construction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
3.2 Transistor Action . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
3.2.1 Working of PNP Transistor . . . . . . . . . . . . . . . . . . . . . . 80
3.2.2 Working of NPN Transistor . . . . . . . . . . . . . . . . . . . . . 81
Contents xiii

3.3 Circuit Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

3.3.1 Common-Base (CB) Configuration . . . . . . . . . . . . . . . . 82
3.3.2 Common-Emitter (CE) Configuration . . . . . . . . . . . . . . 83
3.3.3 Common-Collector (CC) Configuration . . . . . . . . . . . . . 84
3.4 Input/Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
3.4.1 CB Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
3.4.2 CE Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
3.4.3 CC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
3.5 Mathematical Relationships . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
3.5.1 Relation Between b and a . . . . . . . . . . . . . . . . . . . . . . 89
3.5.2 Relation Between ICEO and ICBO . . . . . . . . . . . . . . . . . . 89
3.6 Biasing of Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
3.6.1 Fixed Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
3.6.2 Emitter Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
3.6.3 Voltage Divider Bias . . . . . . . . . . . . . . . . . . . . . . . . . . 95
3.6.4 DC Bias with Voltage Feedback or Collector Bias . . . . . 98
3.6.5 Comparison of Biasing Circuits . . . . . . . . . . . . . . . . . . . 99
3.7 Graphical Analysis of CE Amplifier . . . . . . . . . . . . . . . . . . . . . . 100
3.8 Parameter Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
3.8.1 H-Parameter Model of CE Amplifier Configuration . . . . 104
3.9 Hybrid Equivalent Circuit for Common Base (CB) . . . . . . . . . . . 109
3.9.1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
3.10 Hybrid Equivalent Circuit for Common Collector (CC) . . . . . . . . 110
3.11 Overall Current Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
3.12 Overall Voltage Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
4 Field Effect Transistor (FET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
4.2 Junction Field Effect Transistor (JFET) . . . . . . . . . . . . . . . . . . . 186
4.3 Working Principle of JFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
4.4 Concept of Pinch-Off and Maximum Drain
Saturation Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
4.5 Input and Transfer Characteristics . . . . . . . . . . . . . . . . . . . . . . . 190
4.6 Parameters of JFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
4.7 JFET Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
4.7.1 Fixed-Biasing of JFET . . . . . . . . . . . . . . . . . . . . . . . . . 193
4.7.2 Self-Biasing of JFET . . . . . . . . . . . . . . . . . . . . . . . . . . 193
4.7.3 Potential Divider Method of Biasing JFET . . . . . . . . . . 194
4.8 JFET Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
4.8.1 Common Gate JFET Configuration . . . . . . . . . . . . . . . . 196
4.8.2 Common Source JFET Configuration . . . . . . . . . . . . . . 199
4.8.3 Common Drain JFET Configuration . . . . . . . . . . . . . . . 203
4.9 Metal–Oxide Semiconductor Field Effect
Transistor (MOSFET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
xiv Contents

4.10 MOSFET Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

4.10.1 Depletion Mode Operation . . . . . . . . . . . . . . . . . . . . . . 208
4.10.2 Enhancement Mode Operation . . . . . . . . . . . . . . . . . . . 209
4.11 Characteristics of MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
5 Operational Amplifier (Op-Amp) . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
5.2 Op-Amp Integrated Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
5.3 Op-Amp Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
5.4 Concept of Ideal Op-Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
5.5 Inverting Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
5.6 Non-inverting Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
5.7 Unity Gain or Voltage Follower Amplifier . . . . . . . . . . . . . . . . . 238
5.8 Op-Amp as Adder or Summer . . . . . . . . . . . . . . . . . . . . . . . . . . 238
5.9 Op-Amp as Difference Amplifier . . . . . . . . . . . . . . . . . . . . . . . . 239
5.10 Subtractor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
5.11 Differentiator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
5.12 Integrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
5.13 Op-Amp Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
5.13.1 Input Offset Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
5.13.2 Input Offset Current . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
5.13.3 Bias Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
5.13.4 Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
5.13.5 Common-Mode Rejection Ratio (CMRR) . . . . . . . . . . . 245
6 Switching Theory and Logic Design (STLD) . . . . . . . . . . . . . . . . . . . 271
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
6.2 Number System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
6.2.1 Decimal System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
6.2.2 Binary System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
6.2.3 Octal System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
6.2.4 Hexadecimal System . . . . . . . . . . . . . . . . . . . . . . . . . . 273
6.3 Conversion of Bases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
6.3.1 Decimal to Binary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
6.3.2 Binary to Decimal . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
6.3.3 Fractional Decimal Number to Binary . . . . . . . . . . . . . . 275
6.3.4 Fractional Binary to Decimal . . . . . . . . . . . . . . . . . . . . 275
6.3.5 Octal to Decimal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
6.3.6 Decimal to Octal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
6.3.7 Binary to Octal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
6.3.8 Octal to Binary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
6.3.9 Hexadecimal to Decimal . . . . . . . . . . . . . . . . . . . . . . . . 277
6.3.10 Decimal to Hexadecimal . . . . . . . . . . . . . . . . . . . . . . . . 277
6.3.11 Hexadecimal to Binary . . . . . . . . . . . . . . . . . . . . . . . . . 277
Contents xv

6.3.12 Binary to Hexadecimal . . . . . . . . . . . . . . . . . . . . . . . . . 277

6.3.13 Hexadecimal to Octal . . . . . . . . . . . . . . . . . . . . . . . . . . 278
6.4 Binary Coded Decimal (BCD) Numbers . . . . . . . . . . . . . . . . . . 278
6.5 Binary Addition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
6.6 Binary Subtraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
6.7 Boolean Algebra . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
6.7.1 Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
6.8 Boolean Algebra Theorems Table . . . . . . . . . . . . . . . . . . . . . . . 280
6.9 Logic Gates And Universal Gates . . . . . . . . . . . . . . . . . . . . . . . 281
6.10 Canonical Forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
6.11 K-map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
6.12 Simplification of Boolean Expression Using K-map . . . . . . . . . . 284
6.13 Simplification in Sum of Product (Sop) Form . . . . . . . . . . . . . . . 285
7 Electronics Instruments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
7.1 Digital Voltmeters (DVMs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
7.1.1 Ramp-Type DVMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
7.1.2 Staircase-ramp DVMs . . . . . . . . . . . . . . . . . . . . . . . . . . 329
7.2 Digital Multimeters (DMMs) . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
7.3 Cathode Ray Oscilloscope (CRO) . . . . . . . . . . . . . . . . . . . . . . . 332
7.4 Measurements Using CRO . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
7.4.1 Measurement of Voltage . . . . . . . . . . . . . . . . . . . . . . . . 333
7.4.2 Measurement of Current . . . . . . . . . . . . . . . . . . . . . . . . 334
7.4.3 Measurement of Phase Difference . . . . . . . . . . . . . . . . . 334
7.4.4 Measurement of Frequency . . . . . . . . . . . . . . . . . . . . . . 335
8 PSPICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
8.1 SPICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
8.2 PSPICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
8.3 Circuit Design and Analysis Using PSPICE . . . . . . . . . . . . . . . . 338
8.4 Simulation and Analysis of Common Emitter Amplifier
Using PSPICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348

Appendix A: Symbols, Abbreviations and Diagrammatic Symbols . . . . . 353

Appendix B: Units and Conversion Factors . . . . . . . . . . . . . . . . . . . . . . . 359
Appendix C: Periodic Table of the Elements . . . . . . . . . . . . . . . . . . . . . . 361
Appendix D: Conduction Properties of Common Metals . . . . . . . . . . . . . 363
Appendix E: Ripple Factor and Voltage Calculation . . . . . . . . . . . . . . . . 367
Appendix F: Hybrid Parameters—Graphical Determinations
and Conversion Equations (Exact and Approximate) . . . . . 371
xvi Contents

Appendix G: Selected Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379

Appendix H: Hybrid-p Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
Appendix I: Binary Multiplication, Binary Division and Negative
Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387
Solved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391
Glossary of Electric Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463
About the Author

O. N. Pandey was a Professor and Head of the instrumentation and control

engineering department at the JSS Academy of Technical Education, Noida. He
retired in the year 2017. He obtained his B.Tech., M.E. and Ph.D. degrees from IIT
Kanpur and the University of Roorkee (presently known as IIT Roorkee. Dr.
Pandey received a UNIDO fellowship and specialization in the field of instru-
mentation, control, and industrial automation in the USA. He presented several
technical papers and also participated in various national and international con-
ferences. Dr. Pandey served as a senior technical officer in CMTI-Bangalore for 12
years. He has been responsible for the development of technologies related to the
automation of manufacturing industries.

xvii
Chapter 1
Basics of Electronics

1.1 Introduction

Electron mechanics is known as electronics. Electronics puts electrons to work

using the science and technology of the electron motion. The advancement of
electronics has been very fast. Electronics has given tremendous growth in com-
puter science, communication, control, instrumentation, information technology.
Although electronic devices such as computer, cellular phone or television are
well-known, but inside of these devices are a mystery. Electronics engineering is
the knowledge related with functioning of electronic devices.
Development of electronics started with vacuum diode in 1897 and vacuum
triode in 1906. Semiconductor electronics started with the invention of transistor in
1948 and this replaced tube-based electronics. The electronic components
developed are diode, transistor, field effect transistor (FET).
Integrated circuits (ICs) were developed in 1958. ICs are basically an entire
electronic circuit on a single semiconductor chip. A single chip has all active and
passive components and their interconnections integrated during manufacturing
process. ICs drastically reduced the size, weight and cost of the electronic devices.
The design and fabrication of high density ICs is known as microelectronics.
The small-scale integration (SSI) have components less than 100, medium-scale
integration (MSI) have 100 to 1000 components, large-scale integration have 1000
to 10,000 components and very large-scale integration (VLSI) have more than
10,000 components. New IC concepts resulted in new computer architecture which
is based on speed, power consumption and component density. Thus, digital
integrated circuits came into existence leading to transistor–transistor logic (TTL),
emitter-coupled logic ECL, etc. The latest electronic component fabrication uses
complementary metal–oxide semiconductor (CMOS) technology.
The memories based on electronics are random access memories (RAMs) which
are capable of both storing and retrieving data. RAMs store about 100 bits of
information. 1600-bit, 64,000-bit and 288,000-bit RAMs have been developed

© The Author(s), under exclusive license to Springer Nature Switzerland AG 2022 1

O. N. Pandey, Electronics Engineering,
https://doi.org/10.1007/978-3-030-78995-4_1
2 1 Basics of Electronics

using metal–oxide semiconductor (MOS) technology. More than a billion-bit RAM

chips are available now. Further, read-only memories (ROMs), programmable
ROMs (PROMs), erasable PROMs (EPROMs) are also available. Microprocessor
(MP) development led to the “computer on a chip.” Other developments due to
MOS technology are charge-coupled device (CCD) which are being used in camera
manufacturing, image processing and communication. Analog integrated circuits
developed are operational amplifier (op-amp), digital-to-analog (D/A),
analog-to-digital (A/D) converters, analog multiplexer and active filters.
Electronics engineering developments are taking place today at an awesome
pace; therefore, it has become essential to understand the fundamentals of
electronics.

1.2 Electronic Charge and Current

The smallest particle of any material is a molecule and subdivision of molecules are
atoms. An atom consists of electrons, protons and neutrons. Electrons have negative
charge, protons have positive charge and neutrons have no charge at all. An atom is
electrically neutral, as the number of its electrons is equal to number of protons.
Bonding together has some loosely bound electrons, i.e., free electrons, silver,
copper, aluminum and zinc materials have free electrons; therefore, it is easy to
make them move. Such materials are known as conductors. There are materials like
glass, mica and porcelain which have closely bound atoms and movement of
electrons from atoms is very difficult. Such materials are non-metallic and are
known as insulators.
An electric current is the movement of electrons along a definite path in a
conductor. It is defined as:
Current, iðtÞ ¼ ddqt
where i(t) = instantaneous current in amperes.
q = electric charge in coulombs.
t = time in seconds.

1.3 Electronic Circuit Components

Electronic circuit components are of two types: active and passive. Active
components are semiconductor devices such as diodes, transistors, SCRs and
FETs. e components are resistors, inductors and capacitors. The active components
shall be discussed in subsequent chapters, but passive components need to be
discussed here itself.
1.3 Electronic Circuit Components 3

1.3.1 Resistors

Resistance is a property of a conductor which opposes the flow of an electric

current, and it is denoted by R.

l
R¼q ohm or X
a

where l = length of the conductor in meter.

a = area of cross section in meter2
r = specific resistance or resistivity of the material in ohm-meter.
Conductance, G ¼ R1 mho or X.
Most common resistors are molded-carbon composition type. These are available in
wattage ratings 14 W; 12 W and 1 W with values from few ohms to 22 MΩ. It has 5–
20% tolerance. There are some resistors which are known as metal film resistors
which have accuracy of ±1%. These are also known as precision type. All these
resistors are of very small size wherein printing of the ratings not feasible. Hence,
color coding done is as per Fig. 1.1.
The color codes are given in three bands with fourth band for tolerance. The
color coding is given in Table 1.1.
The above color coding can be memorized as follows: all capital letters stand for
colors.

B B ROY went to Great Britain and brought a Very Good Wife.

Suppose first, second, third and fourth colors are yellow, violet, orange and
silver, respectively. What is the resistance value? The resistance value is given by:
Resistance value,

R ¼ 47  103 X  10%

or
R ¼ 4:7 kX  10%

Fig. 1.1 Color coding for resistor values

4 1 Basics of Electronics

Table 1.1 Color coding of resistors

S. No. Color Digit Multiplier Tolerance S. No. Color Digit Multiplier Tolerance
01 Black 0 100 – 8 Violet 7 107 –
1 Brown 1 101 – 9 Gray 8 108 –
2 Red 2 102 – 10 White 9 109 –
3 Orange 3 103 – 11 Cold – – ±5%
4 Yellow 4 104 – 12 Silver – – ±10%
5 Green 5 105 – 13 No-color – – 205%
6 Blue 6 106 –

The above were fixed resistors, but there are variable resistors in the form of
Rheostats and Potentiometers. The resistors discussed so far have positive tem-
perature coefficients, i.e., resistance value increases if the surrounding temperature
increases. But, there are resistors which have negative temperature coefficients, i.e.,
resistance value decreases if the surrounding temperature increases. Such type of
resistors are known as thermistors. These are made of semiconductor such as
germanium (Ge) or silicon (Si). Other resistor types are light-dependent resistor
(LDR) and voltage-dependent resistor (VDR). LDR resistance value depends on the
intensity of light falling on it; therefore, it is also known as photoresistive cell or
photoresistor. LDR is made of cadmium sulfide (CDS) or cadmium selenide
(CdSe). VDR is based on junction field effect transistor (JFET) which has three
terminals, namely drain (D), source (S) and gate (G). The resistance between drain
and source terminals is dependent on the gate voltage.

1.3.2 Inductors

Inductors store energy in the form of magnetic field. It has a winding of a con-
ducting wire over a core which can be made of iron or just air itself. The current
flowing through the coil establishes a magnetic field through the core. Inductor field
reacts so as to oppose any change in current. The unit of inheritance is henry (H).
There are various types of inductors based on usage such as filter chokes which
smoothens pulsating current produced by a rectifier. Audio-frequency chokes
provide high impedance audio frequencies, i.e., between 60 Hz to 5 KHz. Variable
inductors are used in turning circuits for radio frequencies.

1.3.3 Capacitors

A capacitor stores energy in the form of electric field. A capacitor consists of two
conducting plates separated by an insulating material called dielectric. Capacitors
1.3 Electronic Circuit Components 5

can be of fixed value or variable value. The unit of capacitance is Farad (F).
A capacitor opposes any change in the potential difference or voltage applied across
its terminals.
There are mica capacitors which can be used up to 500 V and are available in the
range from 5 to 10,000 pF. There are ceramic capacitors which can be used in the
range of 3–6000 V. The capacitance value ranges from 3 pF to 3 µF.
Such capacitors can be used in ac as well as dc circuits. Another type in paper
capacitor which can be used from 100 V to several thousand volts. The capacitance
values range from 0.0005 µF to several mF. Such capacitors can be used for both ac
and dc circuits. Electrolytic capacitors are also available which can be used from
1 V to 500 V or more. The values may range from 1 µF to several thousand µF.
These are marked with positive and negative terminals as such used mostly for
dc circuits. Variable capacitors are also available wherein dielectric is air-gap and
its variation leads to variation in the capacitance value.

1.4 Voltage and Current Relationships

The relationships between potential difference across passive elements and the
current through them are given here in Table 1.2
Resistor dissipates energy in the form of heat, inductor stores energy in the form
of magnetic field and capacitor stores energy in the form of electric field. The
voltage and current in the case of resistors are in phase, whereas in the case of
inductors, current lags voltage, and in the case of capacitors, current leads the
voltage.
Heat produced by resistors, H ¼ I 2 Rt Joules
where I = rms value of current in amperes (A)

Table 1.2 Relationships between voltages and currents

S. No. Passive Element Relationship Symbolic Circuits

1. Resistor (R) v = iR

di
2. Inductor v= L
dt

dv
3. Capacitor i= C
dt
6 1 Basics of Electronics

R = resistance in ohms (Ω)

t = time in seconds (s)
Energy stored in Inductor, E ¼ 12 LI 2 Joules
where L = inductance in Farads (F)
Energy stored in capacitor, E ¼ 12 CV 2 Joules
where V = voltage across the capacitor in volts (V).
C = capacitance in Farads (F). Conversion of Joule and Calorie:

1 calorie ¼ 4:18 J:

1.5 Work, Power and Energy

Workdone ¼ Force  distance

W = F  d J.
whereW = work done in Joules (J)
F = force applied in Newtons (N)
d = distance moved in meters (M)

Power ¼ Rate of work done in Joules/second or watts ðWÞ:

or
dW
P¼
dt
W ¼ VQ Joules

where
V = voltage in volts (V)
Q = electric charge in columbs (C)

Energy W VQ
Power ¼ ¼ ¼ watts
time t t

Current, I ¼ Qt Amperes:

2
) Power, P ¼ VI ¼ I 2 R ¼ VR watts:
Important conversions are:
1 hp (British) = 746 watts
1 hp (Metric) = 735.5 watts

Kinetic energy ¼ 12 mv2

1.5 Work, Power and Energy 7

where m = mass of the material

v ¼ velocity of the mass

Gravitational potential energy ¼ mgh

where m = mass of the material

g = gravitational acceleration, i.e., 9.81 m/s2
h = height by which mass is lifted.

Electric - energy ¼ power  time

or

V2
W ¼ VIt ¼ I 2 Rt ¼ t
R

Electrical energy conversions are:

Watts  hour
1 unit ¼ 1 kWh ¼
1000

1 kWh ¼ 3:6  106 J ¼ 3:6 MJ:

1.6 Si Units

The SI units are as per international system of units which are commonly used. The
basic SI units are given in Table 1.3.

Temperature in Kelvin ¼ 273 þ temperature C and the unit change in both
units are 1 K and 1 °C respectively.

Complete revolution ¼ 2p radians or 360°


∴ 2p radians ¼ 360 .
The various prefixes used in units are given in Table 1.4.
Some derived SI units are given in Table 1.5.

Table 1.3 Basic SI units S. No Parameter SI unit Symbol

1. Length meter m
2. Mass kilogram kg
3. Time second s
4. Electric current ampere A
5. Absolute temperature kelvin K
6. Luminous intensity Candela Cd
7. Amount of substance mole mol.
8 1 Basics of Electronics

Table 1.4 Prefixes used in units

S. No Prefix Multiplication factor Symbol
1. pico 10−12 p
2. nano 10−9 n
3. micro 10−6 m
4. milli 10−3 m
5. kilo 103 k
6. mega 106 M
7. giga 109 G
8. tera 1012 T

Table 1.5 Derived SI units

S. No Parameter S.I. Unit Symbol
1. Area square meter m2
2. Volume cubic meter m3
3. Linear velocity meter per second m/s
4. Angular velocity radian per second rad/s
5. Linear acceleration meter/second square m/s2
6. Angular acceleration radian/second square rad/s2
7. Force kilogram meter per second kg m/s2
square or Newton or N
8. Weight = mass  gravitational kilogram force or 9.81 kgf or
acceleration g = 9.81 m/s2 Newtons 9.81 N

1.7 Voltage and Current Sources

Voltage sources are power supplies such as batteries, alternators and dynamos.
Metadyne generators, photoelectric cells, collector circuits of transistors are cur-
rent sources. All these are known as independent voltage and current sources,
respectively. The ideal voltage and current sources are shown in Fig. 1.2. Ideal

Fig. 1.2 Ideal voltage and

current source
1.7 Voltage and Current Sources 9

Fig. 1.3 Realistic voltage

and current source

Fig. 1.4 Conversion between

voltage and current source

voltage source has zero internal resistance in series, whereas ideal current source
has infinite resistance in parallel with the current source.
The realistic voltage source has an internal resistance in series, and realistic
current source has a resistance in parallel as shown in Fig. 1.3.
Conversion of voltage source to current source is shown in Fig. 1.4. It can be
observed that:
When voltage source is converted into current source, then current source values
are:
VS
IS ¼ and RP ¼ Rn
Rs

when current source is converted into voltage source, then voltage source values are:

Vs ¼ IS Rp and RS ¼ RP

when voltage or current source values are dependent on voltage or current values
of a branch, then the voltage or current source are known as dependent voltage and
current source as shown in Fig. 1.5.

Fig. 1.5 Dependent voltage

and current source
10 1 Basics of Electronics

1.8 Semiconductor Materials

A material is made up of one or more elements and an element is a substance

composed entirely of atoms. The atoms of different elements differ in their struc-
tures; therefore, different elements have different characteristics.
An atom is comprised of a relatively massive core or nucleus carrying a positive
charge, around which electrons move in orbits at distances which are great com-
pared with the size of the nucleus. The electron mass is 9.11  1031 kg and
electron charge is −1.602  10–19 Coulomb = −e. The nucleus of every atom
except that of hydrogen consists of protons and neutrons. Each proton carries a
positive charge, e equal in magnitude to that of an electron and its mass is
1.673  10−27 kg i.e., 1836 times that of electron. A neutron has no charge and
its mass is almost same as that of a proton.
Hydrogen atom has the simplest structure as shown in Fig. 1.6. It consists of
only a nucleus of one proton and one electron which revolves in an orbit, of 10−10
m diameter around proton. Atomic number of hydrogen is 1. Fig. 1.7 shows atomic
structure of silicon (Si). Silicon’s atomic number is 14. The electrons are arranged
in orbits or shells. First orbit can have maximum of two electrons. The second orbit
can have maximum of eight electrons. The third orbit can have maximum of
eighteen electrons. The fourth orbit can have maximum thirty-two electrons. The
uppermost orbit in an atom cannot have more than eight electrons.
The number of electrons present in the uppermost orbit is known as valence
electrons. Silicon has four valence electrons. Fig. 1.8 shows a germanium
(Ge) atom structure which has four valence electrons.
Atoms that have four valence electrons are known as tetravalent, and those with
three are known as trivalent. Atoms with five valence electrons are known as
pentavalent. The term valance indicates that the ionization potential required to
remove any one of these electrons from atomic structure is significantly lower than
that required for any other electron in the structure.
Energy Levels
Within the atomic structure of each and every isolated atom, there are specific
energy levels associated with each shell and orbiting electron as shown in Fig. 1.9.
The farther an electron is from the nucleus, the higher is the energy state, and any
electron that has left its parent atom has a higher energy state than any electron in
the atomic structure. Fig. 1.9a shows that in an isolated atom discrete energy levels

Fig. 1.6 Hydrogen atom

1.8 Semiconductor Materials 11

Fig. 1.7 Silicon atom

Fig. 1.8 Germanium atom

can exist. Fig. 1.9b shows a conductor wherein energy levels overlap, hence,
electrons are free to move. Fig. 1.9c shows an insulator wherein the electrons
require very high energy to bring them to conduction level. Fig. 1.9d shows
insulators wherein a minimum energy level is associated with electrons in the
conduction band and a maximum energy level of electrons bound to the valence
shell of the atom. Between the two is an energy that the electron in valence band
must overcome to become free carrier. This energy gap is different for Ge, Si and
GaAs. Ge has the smallest gap and GaAs the largest gap. In short, an electron in the
valence band of silicon must absorb more energy than one in the valence band of
germanium to become a free carrier. Similarly, an electron in the valence band of
12 1 Basics of Electronics

Fig. 1.9 Energy levels

gallium arsenide must gain more energy than one in silicon or germanium to enter
the conduction band.
Thus, we can see that semiconductors are a special class of elements having a
conductivity between that of a good conductor and that of an insulator.
A semiconductor is an element with a valence of four, i.e., an isolated atom of the
material has four electrons in its outer or valance orbit. The number of electrons in
the valence orbit is the key to electrical conductivity. Conductors have one valence
electron and insulators have eight valence electrons. The valance electrons get
themselves detached from the nucleus on the application of small electric field.
These free electrons constituting the flow of current are called conduction electrons.
1.8 Semiconductor Materials 13

There are two types of semiconductors. One is pure type, known as intrinsic type
and other is impure type, known as extrinsic type. The conductivity of intrinsic
semiconductor is poor at room temperature. Therefore, it is not used in electronic
devices. Intrinsic semiconductors properties can be varied by adding impurities, and
their conduction properly can be varied by varying temperature.

1.8.1 Intrinsic Semiconductors

In intrinsic semiconductors even at room temperature, some of the valance

electrons may acquire enough energy to cross over to conduction band from
valence band, thereby becoming free electrons. As the electrons leave the valance
band, it creates a vacant space in it. This is known as “hole.” Thermal energy
produces free electrons and holes in pairs. In Fig. 1.10, a dc voltage is applied
which will force the free electrons to move left and the holes to flow right. When
the free electrons arrive at left end of the semiconductor crystal, they enter the
external wire and flow to the positive battery terminal. On the other hand, the free
electrons at the negative battery terminal will flow to the right end of the crystal. At
this point, they enter the crystal and recombine with holes that arrive at the right end
of the crystal. In this way, a steady flow of free electrons and holes occur inside the
semiconductor. The current in a semiconductor is the combined effect of the flow of
free electrons in one direction and the flow of holes in the other direction. Free
electrons and holes are called carriers as they carry a charge from one place to
another.

1.8.2 Extrinsic Semiconductors

Extrinsic semiconductors are created by a process of adding impurities deliber-

ately to an intrinsic semiconductor. The process is known as doping. The added
impurity is known as doping agent. When doped with a trivalent impurity, the
impurity accepts one electron to achieve stable state. This type of doping agent is

Fig. 1.10 Intrinsic

semiconductors
14 1 Basics of Electronics

known as an acceptor. When doped with a pentavalent impurity, the impurity

donates one electron to the conduction band. This type of doping agent is known as
donor.
There are three semiconductors most frequently used in the construction of
electronic devices namely Si (silicon), Ge (germanium) and GaAs (gallium
arsenide) Si and Ge are single crystals, whereas GaAs is a compound crystal.
Initially, Ge was easily available and refinement, i.e., process of purity was easy.
Therefore, Ge was used for first few decades. However, it was found that Ge was
very sensitive to changes in temperature. In 1954, the trial of Se was done which
was less sensitive to temperature and available in abundance. Therefore, Si became
most popular choice. When speed of operation and communication on computers
became the basic requirement, GaAs became very handy in 1970s. Thus, GaAs is
used as the basic material for new high-speed and very large-scale integrated cir-
cuits (VLSI).

1.8.2.1 N-type Semiconductor

A pentavalent (phosphorous) impurity addition to an intrinsic semiconductor (sil-

icon) gives N-type semiconductor. Phosphorus has five valance electrons and sil-
icon has four valance therefore; in this case, one free electron is available as shown
in Fig. 1.11.
Thus, every phosphorus atom contributes one free electron without creating a
hole. Consequently, number of free electrons becomes far greater than the number
of holes. Such extrinsic semiconductor is known as N-type semiconductor.

1.8.2.2 P-type of Semiconductor

A trivalent (boron, aluminum, etc.) impurity addition to an intrinsic semiconductor

(silicon), gives P-type semiconductor.

Fig. 1.11 N-type

semiconductor, i.e., one free
electron without a hole
1.8 Semiconductor Materials 15

Fig. 1.12 P-type

semiconductor, i.e., one hole
is available per atom of boron

Boron has three valance electrons and silicon has four valance electrons;
therefore, the deficiency of an electron around the boron atom gives rise to a hole,
see Fig. 1.12. Thus, every boron atom contributes one hole. Hence, number of holes
become far greater than the number of electrons. This results in P-type
semiconductor.

1.9 P–N Junction and Depletion Layer

1.9.1 P–N Junction

P–N junction is formed by a special fabrication technology. To make a P–N junction,

the N-type and P-type semiconductor crystals are cut into thin slices called wafers.
If a wafer of P-type semiconductor is joined to a wafer of N-type semiconductor
in such a manner that the crystal structure remains continuous at the boundary, then
a new structure called P–N junction is formed.

1.9.2 Depletion Layer

In a P–N junction, the P-region has holes and negatively charged impurity ions. N-
region has free electrons and positively charged impurity ions. Electrons and holes
are mobile charges whereas the ions are immobile. When a P–N junction is formed,
the holes in the P-region diffuse into N-region and the electrons in the N-region
diffuse into P-region. This process is called diffusion which happens for a short time
as soon as the P–N junction is formed. After a few combinations of holes and
electrons, a restraining force is developed which is known as potential barrier.
This potential barrier prevents further diffusion of holes and electrons. The barrier
force development can be easily explained. That is, each recombination of hole and
16 1 Basics of Electronics

Fig. 1.13 Formation of P–N junction and depletion layer

electron eliminates hole and electron. During this process the negative acceptor ions
in the P-region and positive donor ions in the N-region are left uncompensated. The
additional holes trying to diffuse into N-region and additional electrons trying to
diffuse into P-region are repelled by these negative and positive charges respec-
tively. The region containing this uncompensated acceptor and donor ions is called
depletion layer, see Fig. 1.13.

1.9.3 Forward Biasing

When an external voltage is applied to the P–N junction in such a direction that it
cancels the potential barrier which permits current flow, it is called forward
biasing.
Figure 1.14 shows forward biasing connections. Positive terminal of battery is
connected to P-type and negative terminal to N-type. The applied forward potential
establishes an electric field which acts against the field due to depletion (potential)
barrier. Thus, the depletion (potential) barrier is reduced and allows the flow of

Fig. 1.14 Forward biasing

reduces, depletion (potential
barrier)
1.9 P–N Junction and Depletion Layer 17

Fig. 1.15 Reverse bias

increases depletion barrier
(potential barrier)

charged carriers across the barrier. In effect, a small forward voltage is sufficient to
make the depletion barrier insignificant. Once the depletion barrier is made
insignificant by the forward voltage, junction resistance becomes too small and a
high current flows in the circuit.

1.9.4 Reverse Biasing

When the external voltage applied to the P–N junction is in such a direction that
depletion (potential) barrier is increased, it is called reverse biasing.
Figure 1.15 shows reverse biasing connection. Negative terminal of battery is
connected to P-type and positive terminal to N-type. The reverse biasing establishes
an electric field which acts in the same direction as the field due to depletion
(potential) barrier. Thus, depletion (potential) barrier is increased and prevents the
flow of charge carriers across the junction. In effect, a high resistance path is
established for the circuit; hence, the current flow is insignificant.
Summary
1. Semiconductor Devices: Semiconductor devices are diode, transistor and
integrated circuits (ICs), ICs are known as microelectronics. ICs can be
small-scale integration (SI), medium-scale integration (MSI), large-scale
integration (LSI) and very large-scale integration (VLSI). There are digital as
well as analog ICs. Digital logic can be based on transistor–transistor logic
(TTL), emitter-coupled logic (ECL), etc. Latest electronic components use
complementary metal–oxide semiconductor (CMOS) technology. The
semiconductor memories are random access memory (RAM), read-only
memory (ROM), programmable ROM (PROM) and erasable PROM
(EPROM). Microprocessor (MP) has given bite to “computer on chip.”
Operational amplifier (op-amp) is an analog IC. Other electronic devices are
digital to analog (D/A) converter, analog-to-digital (A/D) converter, analog
multiplexers and active filters.
18 1 Basics of Electronics

2. Electronic Circuit Components: There are two types of electronic circuit

components. One type of components are active components such as diodes,
transistors, silicon controlled rectifiers (SCRs), field effect transistors (FETs),
etc. Other type of components are passive components such as resistors
inductors and capacitors.
3. SI Units: SI units are as per international system of units. The basic SI units
are meter, kilogram, second, ampere, kelvin, candela and mole. Temperature
in Kelvin = 273 + temperature in °C.
4. Voltage and Current Sources: Voltage source has very small internal
resistance and ideal voltage source has zero internal resistance. Current
source has very large resistance across it, and ideal current has infinite
resistance across it. Voltage and current sources can be converted from one
to other or vice-versa for circuit analysis purposes.
5. Semiconductor Materials: Number of electrons in uppermost orbit of an
atom of a material is known as valence. Conductors have one valance
electron, insulators have eight valence electrons and semiconductors have
four valence electrons. Each silicon atom in a crystal has its four valence
electrons plus four more electrons that are shared by the neighboring atoms.
6. Intrinsic Semiconductors: It is a pure semiconductor. When an external
voltage is applied to the intrinsic semiconductor, the free electrons flow
toward the positive battery terminal and the holes flow toward the negative
battery terminal.
7. Extrinsic Semiconductors: When an intrinsic semiconductor is doped with
pentavalent donor atoms, it has more free electrons than holes. When an
intrinsic semiconductor is doped with trivalent acceptor atoms, it has more
holes than free electrons.
8. N-type and P-type semiconductors: In an N-type semiconductor, the free
electrons are the majority carriers, while the holes are the minority carriers.
In a P-type semiconductor, the holes are the majority carriers, while the free
electrons are the minority carriers.
9. Forward and Reverse Biasing: When a battery is connected across the P–N
junction, then this process is known as biasing of the P–N junction. In
forward biasing of a P–N junction, positive terminal of the battery is con-
nected to the P-side and the negative terminal to the N-side. In reverse
biasing, the positive terminal of battery is connected to N-side and negative
side is connected to P-side of the P–N junction.
10. Important Formulae:
i .v ¼ i R
ii .v ¼ L ddti
iii. i ¼ C ddti
iv. Heat produced
by resistor = I 2 Rt Joules.
1.9 P–N Junction and Depletion Layer 19

v. Energy stored
in an inductor = R1 LI 2 Joules.
vi. Energy stored
in a capacitor = 12 CV2 Joules .
vii. 1 calorle ¼ 4:18 Joules:
2
viii. Power ¼ VI ¼ l2 R ¼ Vn watts:
ix. 1 hp (Brttish) ¼ 746 watts:
x. 1hpð Metric Þ ¼ 735:5 watts
xi. 1 unit energy ¼ 1 kWh ¼ 3:6 MJ :
Exercises
1. What do you understand by electronics? Explain its utility in our daily life.
2. Explain latest trends in electronics.
3. What do you understand by electric current?
4. What are active components? Name three active components.
5. What is a resistor? What is the relationship of resistance value with length and
of cross section of a conductor?
6. Explain color coding of a resistor with an example.
7. Explain inductors and capacitors. What are their relationships with current
through and voltage across there?
8. Explain electrical power, energy and their relationships with current and
voltages.
9. What is SI unit? Explain basic and derived SI units.
10. Write short note on voltage and current sources.
11. Explain an atom with a diagram.
12. What do you understand by valence of a material? Give valences of conductor,
insulator and semiconductor.
13. What is an intrinsic semiconductor?
14. Explain extrinsic semiconductor.
15. What are N-type and P-type semiconductors?
16. Explain a P–N junction and depletion layer.
17. What do you understand by forward and reverse biasings?
Chapter 2
Semiconductor Diodes

2.1 Semiconductor Diode

A P–N junction is known as semiconducto diode. A semiconductor diode is

represented by the schematic symbol shown in Fig. 2.1. The arrow indicates the
direction of forward bias current flow. It has two terminals.
If the dc power supply pushes current in the direction of arrow, it is foward
biased; if the current is trying to flow opposite to arrow direction, it is reverse
biased. Figure 2.2 shows forward and reverse-biased circuits.
The general characteristics of a semiconductor diode can be demonstrated
through the use of solid-state physics. Shockley’s equation represents these char-
acteristics. For the forward and reverse bias regions, the equation is:


IF ¼ IS eVF =gVT  1

where
VF = applied forward bias voltage across the diode.
IF = forward bias current through the diode.
IS = reverse bias saturation current.

g = a factor representing operating conditions, for germanium diode.

g = 1 and for silicon diode g = 2.

VT = thermal voltage determined by VT ¼ kTq .
where
k = Boltzmann’s constant = 1.38  10–23 J/Kelvin.
T = absolute temperature in kelvins = 273 + temperature in °C.
q = magnitude of electronic charge = 1.6  10–19 C.

© The Author(s), under exclusive license to Springer Nature Switzerland AG 2022 21

O. N. Pandey, Electronics Engineering,
https://doi.org/10.1007/978-3-030-78995-4_2
22 2 Semiconductor Diodes

( a ) P-N Junction ( b ) Schematic symbol of a semiconductor diode

Fig. 2.1 P–N junction and schematic symbol of a diode

(a) Forward biased diode ( b ) Reverse biased diode

Fig. 2.2 Forward and reverse-biased diodes

At room temperature (T = 300 K), VT = 26 mV.

Thus, at room temperature, IF = IS (e40VF η − 1).

2.2 V–I Characteristics

From Eq. (2.1), for forward bias VF will be positive and current equation is given
by:

IF ¼ IS eVF =g VT  IS

The first term in the equation is very high as compared to IS; hence, the forward
current is

IF ffi IS eVF =gVT

The forward bias current for theoretical case is shown in Fig. 2.3 by dotted lines
for a silicon diode.
2.2 V–I Characteristics 23

Fig. 2.3 V–I characteristics of ideal and practical diode

For a voltage VF = 0, the equation for current is

 
IF ¼ IS e0  1 ¼ 0:

For a negative VF (reverse bias), the equation for current is

IF ¼ Is eVF =gVT  Is

The first term will be too small as compared to IS+; hence, current becomes

IF ffi IS

The theoretical characteristics are again shown in Fig. 2.3 by dotted line for
VD = 0 and reverse bias. However, commercially available diode forward-bias
diode characteristics differ from the theoretical due to internal body resistance and
external contact resistance of diode, etc. Thus, commercial forward bias diode
characteristics are shown by continuous line in Fig. 2.3. The theoretical and
commercial diode current in the reverse bias case is too small, i.e., 10 pA to 1 µA;
therefore, characteristics for negative VD (reverse bias) are almost same.
Example 2.1 The reverse saturation current at room temperature is 0.4 µA when a
reverse bias is applied to a Ge diode. What is value of current flowing in the diode,
if 0.15 V forward bias is applied at room temperature?
24 2 Semiconductor Diodes

Solution:
Given:

IS ¼ 0:4 lA

Forward bias voltage,

VF ¼ 0:15 V

∴ The current flowing through the diode under forward bias at room temperature
is:


IF ¼ IS e40VF =g  1

h ¼ 1 for germanium diode

 
) IF ¼ 0:4  106 e40015  1

or

IF ¼ 160:87 lA:

2.3 Ge, Si and GaAs Characteristics

The V–I characteristics considered so far have been for silicon diodes. The V–I
characteristics for the three materials are shown in Fig. 2.4. The center of the knee
of the curve, i.e., barrier potential, is about 0.3 V for Ge, 0.7 V for Si and 1.2 V for
GaAs. It can be seen that best characteristics are for GaAs and next good one is for
Si; the Ge is the last one, i.e., least desirable. It is important to note in the reverse
bias case, there is a voltage VZ at which reverse bias current suddenly jumps to very
high current. VZ is known as zero potential. The zero voltages for Ge, Si and GaAs
are −50 V, −100 V and −1 kV, respectively.

2.4 Ideal and Practical V–I Characteristics

An ideal diode characteristic should be such that it allows full current to flow in
forward bias condition and zero current in reverse bias condition. In other words, an
ideal diode will act as a closed switch in forward bias condition, whereas as an open
switch in reverse bias condition. Figure 2.5 shows an ideal semiconductor diode in
forward bias and reverse bias condition.
2.4 Ideal and Practical V–I Characteristics 25

Fig. 2.4 V–I characteristics of Ge, Si and GaAs

Fig. 2.5 An ideal semiconductor diode

The ideal semiconductor V–I characteristics are shown in Fig. 2.6. The
semiconductor diode has zero resistance in forward bias and infinite resistance in
reverse bias condition. The actual V–I characteristics will be as explained earlier
for theoretical or commercial cases.

2.5 Diode Resistance

It is clear by now that a forward-biased diode conducts easily, whereas reverse-

biased diode conduction is negligible. In other words, forward resistance of a diode
is very small as compared to its reverse resistance.
26 2 Semiconductor Diodes

Fig. 2.6 An ideal and actual V–I characteristic of a semiconductor diode

2.5.1 Forward Resistance

Forward-biased diode resistance changes with the changing current; thus, it can be
dc forward resistance or ac forward resistance.

2.5.1.1 DC Forward Resistance or Static Resistance (RF)

In the case of application where direct current flows, the forward diode resistance
can be explained by Fig. 2.7. Suppose voltage applied is OA and dc current OB is
flowing through the diode, then

Fig. 2.7 DC forward bias

resistance
2.5 Diode Resistance 27

DC forward resistance

OA
RF ¼
OB

2.5.1.2 AC Forward Resistance (rF) or Dynamic Resistance

AC forward resistance is the resistance offered by the diode due to the changing
current. Consider Fig. 2.7.
AC forward resistance,

Change in voltage across the diode

rF ¼
Corresponding change in current

or

OD  OC CD DVF
rF ¼ ¼ ¼
OF  OE EF DIF

AC forward resistance is significant as diodes are generally used with ac volt-

ages. AC forward resistance of diode is very small in the range of 1–25 Ω.
The diode current equation is given by:


IF ¼ IS eVF =gVT  1

By differentiating, we get

dIF VF
¼ IS   eVF =gVT
dVF gVT

or

dVF gVT gVT

¼ V =gV ¼
dIF IS e F T IF þ IS

gVT
) rF ¼
IF þ IS

or
diode resistance,

gVT
rF ¼ as IS  IF
IF
28 2 Semiconductor Diodes

Thus, for forward bias, rF is inversely proportional to IF. At room temperature,

i.e., 27° (300 K), we have:

1  26 mV
rF ¼ taking g ¼ 1 ðgermanium and VT ¼ 26 mVÞ
IF  mA

Example 2.2 Determine the dynamic resistance of a P–N junction diode at for-
ward current of 2 mA. Assume that kTe ¼ 2:5 mV.

Solution:
Given: Forward current,

IF ¼ 2 mA

Voltage equivalent of temperature,

kT
VT ¼ ¼ 2:5 mV
e

We know that:
Dynamic resistance

gVT
rF ¼
IF

1  2:5 mV
rF ¼ taking g ¼ 1
2 mA

or

rF ¼ 1:25 X:

2.5.1.3 Reverse Resistance (RR)

The resistance of diode due to reverse bias is known as reverse resistance. The
reverse resistance is too high, nearly infinite.
Reverse resistance RR ’ 40; 000 RF for germanium.

2.5.2 Transition and Diffusion Capacitance

An electronic circuit is sensitive to frequency. At high frequencies for the diode,

stray capacitive effects are considerable. Forward bias condition has the effect of
2.5 Diode Resistance 29

Fig. 2.8 Effect of capacitance

on the semiconductor diode

diffusion leading to diffusion capacitance (CT). In reverse bias condition, there is

depletion region or transition capacitance (CT). The capacitive effects are repre-
sented by capacitors in parallel with the ideal diode, as shown in Fig. 2.8. These are
applicable normally in power areas.
The diffusion capacitance is given by the formula:

IF
CD ¼
gVT

where
η = constant (η = 1 for Ge and η = 2 for Si).
VT = volt equivalent of temperature.
T = mean lifetime of current.
IF = forward current.
The depletion or transition capacitance is given by formula:

CT ¼ pKffiffiVffi where V = applied bias voltage.

The capacitance VS applied bias voltage plot is given below:

2.5.3 Diode Equivalent Circuit

The diode linear characteristic of forward bias gives:

30 2 Semiconductor Diodes

VF ¼ VT þ IF rF

The actual and linear characteristics along with equivalent circuit are as fol-
lows:

2.6 Diode Ratings

Data sheets of diode specify several useful parameters, and some of these are
explained here.

2.6.1 Repetitive Peak Current (Ipeak)

It is the maximum instantaneous value of repetitive forward bias current.

2.6.2 Average Current (Iav)

It is an average forward bias current value and is defined by Iav ¼ 0:318 Ipeak :
2.6 Diode Ratings 31

2.6.3 Peak Inverse Voltage (VR)

It is the absolute peak voltage which must be applied in reverse bias across the
diode.

2.6.4 Steady-State Forward Current (IF)

It is the maximum current which can be passed continuously through the diode.

2.6.5 Peak Forward Surge Current (IFS)

It is a current which may flow briefly when a circuit in switch is first switched on.
IFS is very much higher than IF.

2.6.6 Static Maximum Voltage Drop (VFM)

It is a maximum forward voltage drop for a forward current at the device

temperature.

2.6.7 Continuous Power Dissipation (P)

It is the maximum power which can be dissipated continuously in free air.

2.6.8 Reverse Recovery Time (trr)

It is the maximum time for the device to switch from ON to OFF.

32 2 Semiconductor Diodes

Example 2.3 What is the current in the circuit shown below:

Solution: For silicon diode, VF = 0.7 V.

Using KVL in the circuit, we get:

5 ¼ VF þ I  10

or

5  0:7 4:3
I¼ ¼ ¼ 0:43 A
10 10

Thus, current in the circuit, I = 0.43 A.

Example 2.4 Find the voltage VA and the current in the circuit shown in figure
given below:

Solution: For silicon diode,

VF ¼ 0:7 V

Voltage,

VA ¼ 15  ð0:7  2Þ ¼ 13:6 V

and current,

13:6
I¼ ¼ 1:942  103 A or 1:942 mA
7  103
2.7 P–N Junction (Diode) as Rectifiers 33

Fig. 2.9 Block diagram of a dc supply

2.7 P–N Junction (Diode) as Rectifiers

The electrical power supply to Indian homes and industries is in the form of ac
voltage. It is 220 V rms at 50 Hz for domestic usage. The electronic equipment is
operated by dc supply. It can be dry cells or battery eliminator. A battery elim-
inator gets ac voltage as input and converts it into dc supply. Battery eliminator is
also known as dc power supply. The individual units in a dc power supply are input
step-down transformer, rectifier, filter and regulator. Figure 2.9 shows the block
diagram of a dc power supply.

2.7.1 Half-Wave Rectifier

A half-wave rectifier is shown in Fig. 2.10. The ac supply is input to a step-down

transformer. The secondary has a diode which is connected across the load as
shown. Suppose secondary voltage is given as:

Vo ¼ Vm sin xt

Then, half-wave rectifier waveforms will be shown in Fig. 2.11.

The ac voltage across the secondary winding of the transformer changes polarity
after every half-cycle. During positive half-cycle, the diode is forward biased, and
hence, current flows through the load. In other words, during positive half-cycle
voltage across the load is also positive half-cycle. During negative half-cycle, the
diode is subjected to reverse bias, and hence, negligible current flows through the

Fig. 2.10 Half-wave rectifier

34 2 Semiconductor Diodes

Fig. 2.11 Half-wave rectifier waveforms

load; i.e., there is no voltage across the load. Thus, output across the load is
pulsating dc.
The current through the load is given by:

iL ¼ Im sin xt for 0  xt  p
¼ 0 for p  xt  2p
2.7 P–N Junction (Diode) as Rectifiers 35

Peak value of current,

VL
Im ¼
RL

The average value of load current,

Area of wave for a cycle area

Iav ¼ Idc ¼ ¼
Duration of a cycle base

We know that:

Z2p
Area ¼ iL dðxtÞ
0
Zp Z2p
¼ Im sin xtdðxtÞ þ 0dðxtÞ
0 p
¼ Im ½ cos xtp0 þ 0
¼ Im ½ cos p  ð cos 0Þ
¼ Im ½1 þ 1 ¼ 2Im

area 2Im
) Idc ¼ ¼
base 2p

or

Im
Idc ¼ :
p

The voltage across the load RL is given by:

Im
Vdc ¼ Idc  RL ¼ RL
p

So far, it was considered that diode forward resistance is zero, but if actual
Fresistance rF is considered, then we get:

Vm
Im ¼
ðRL þ rF Þ
36 2 Semiconductor Diodes

Vm
) Vdc ¼  RL
pðRL þ rF Þ
Vm
¼

p 1 þ RrFL

or

Vm
Vdc ¼ for rF  RL :
p

Rectifier efficiency,

dc power output
g¼
ac power input

qdc ðIm =pÞ2 RL Im

¼ ¼ as Irms ¼
qac ðIm =2Þ ðrF þ RL Þ
2 2

0:406RL
) g¼
rF þ R L
0:406
¼

1 þ RrFL

or

g ¼ 0:406 for rF  RL :

Thus, in half-wave rectification, a maximum of 0.6% of ac power is converted

into dc power.
Peak Inverse Voltage (PIV) Diode.
The diode is subjected to voltage Vm in the reverse bias situation; therefore, peak
inverse voltage (PIV) in this case is Vm.
Thus, the diode must be able to withstand maximum voltage Vm in the negative
half-cycle.
Example 2.5 A half-wave rectifier employs a diode having a forward resistance of
10 Ω. If the input voltage to the rectifier circuit is 12 V(rms), find the dc output
voltage at a load 100 mA and PIV.
Solution:
Given: Forward resistance,
2.7 P–N Junction (Diode) as Rectifiers 37

rF ¼ 10 W

Load Current,

IL ¼ 100 mA

rms value of supply voltage,

Vrms ¼ 12 V

Maximum supply voltage,

pffiffiffi
VSM ¼ 2 Vrms
pffiffiffi
¼ 2  12 ¼ 16:97

dc output voltage for half-wave rectifier,

VSM
Vdc ¼  Idc rF
p

or

17
Vdc ¼  0:1  10 ¼ 4:4 V:
p
PIV ¼ VSM ¼ 17 V:

Example 2.6 A half-wave rectifier uses a diode with an equivalent forward

resistance of 0.3 Ω. If the input ac voltage is 10 V(rms) and the load is a resistance
of 2.0 Ω, calculate Idc and Irms in the load.
Solution:
Given: Supply voltage, Vrms = 10 V, forward resistance,

rF ¼ 0:3 X and load resistance RL ¼ 20 X

The peak value of supply voltage,

pffiffiffi
Vm ¼ 10 2 V

The peak value of current,

pffiffiffi
Vm 10 2
Im ¼ ¼ ¼ 6:15 A
RL þ rF 2 þ 0:3

dc output current,
38 2 Semiconductor Diodes

Im 6:15
Idc ¼ ¼ ¼ 1:958 A:
p p

rms value of output current,

Im 6:15
Irms ¼ ¼ ¼ 3:075 A:
2 2

2.7.2 Full-Wave Rectifier

Half-wave rectifier utilizes only one half-cycle of the input wave. Full-wave rec-
tifier utilizes both the half-cycles. A unidirectional local current is achieved by
inverting alternate half-cycles. Full-wave rectifier can be divided into two cate-
gories. One is known as center tap rectifier which uses two diodes. The other is
known as bridge rectifier which uses four diodes.

2.7.2.1 Center Tap Rectifier

In this case, the secondary winding is center tapped and load along with two diodes
is connected as shown in Fig. 2.12a. The secondary winding is divided into two

Fig. 2.12 a Center-tapped full-wave rectifier and b center-tapped full-wave rectifier waveform
2.7 P–N Junction (Diode) as Rectifiers 39

equal parts, and a tapping is done and used in circuit as shown. The waveform of dc
voltage across the load will be shown in Fig. 2.12b. Diode DI conducts during
positive half-cycle, whereas diode D2 conducts during negative half-cycle.
Thus, load current through load is always in one direction only. Hence, it is
full-wave rectified dc output.
Peak Inverse Voltage (PIV) of Diode
The voltage Vm is the maximum voltage across half of the secondary winding.
When diode D1 is conducting, resistance of diode is almost zero. Hence, full peak
voltage Vm appears across the load resistor RL. Thus, reverse voltage which appears
the diode D2 summation of voltage across D2 and that load RL. Hence, Vm voltage
appears across diode D2; i.e., 2 Vm voltage appears across the non-conducting
diodes, D1 or D2.
∴ Peak inverse voltage of diode

PIV¼ 2 Vm

Center tapping is difficult, dc power output is small as secondary winding is

divided, and diodes should have high PIV.

2.7.2.2 Bridge Rectifier

It uses four diodes instead of two as shown in Fig. 2.13. But, it does not need a
center-tapped transformer.
A simplified circuit diagram of the bridge rectifier is shown in Fig. 2.14a.
Diodes D2 and D4 conduct during positive half-cycle of the supply, whereas diodes
D1 and D3 are non-conducting as shown in Fig. 2.14b. Hence, current flows
through the load resistor RL and diodes D2 and D4. Diodes D1 and D3 conduct
during negative half-cycle of the supply, whereas diodes D2 and D4 are
non-conducting as shown in Fig. 2.14c. Thus, current flows in the same direction
through the load resistor RL and diodes D1 and D3. Hence, an alternating bidirec-
tional voltage waveform is converted into unidirectional voltage waveform across
the load resistor.

Fig. 2.13 Bridge rectifier

40 2 Semiconductor Diodes

Fig. 2.14 Simplified circuit and conduction of bridge rectifier

The waveform of the supply voltage is shown in Fig. 2.15a. The current
waveform through the load resistor RL during positive half-cycle of the supply is
shown in Fig. 2.15b. Similarly, the current waveform through the load resistor
during negative half-cycle of the supply is shown in Fig. 2.15c. The net current
wave during full cycle of the supply through the load resistor RL is shown in
Fig. 2.15d. Thus, voltage waveform during full cycle of supply across the load is as
shown in Fig. 2.15de, i.e., fully rectified waveform of the supply.
The peak inverse voltage (PIV) across each non-conducting diodes in a bridge
rectifier is just the peak value of the voltage supply, i.e., Vm. Thus, the diodes used
for bridge rectifier are cheaper as compared to the ones used for center-tapped
rectifiers.
It is important to note that the need for center tapping of supply transformer
secondary is eliminated in bridge rectifier. The output is twice that of the
center-tapped circuit for the same secondary voltage. For the same dc output
voltage, PIV of bridge rectifier circuit is half that of center-tapped circuit. It requires
four diodes, each half-cycle of ac input two diodes that conduct are in series,
therefore, voltage drop in the internal resistance of the rectifying unit will be twice
as great as in the centre-tapped circuit. This is undesirable when the secondary
voltage is small.
2.7 P–N Junction (Diode) as Rectifiers 41

Fig. 2.15 Bridge rectifier waveforms

42 2 Semiconductor Diodes

2.8 Ripple Efficiency and Regulation

A measure of purity of the dc output of a rectifier is ripple factor which is defined as

follows:
Ripple factor,

rms value of the components of wave

r¼
average or dc value

Rectification efficiency is defined as:

dc power delivered to load

g¼
ac input power from transformer secondary

or

Pdc
g¼
Pac

It may be noted that Pac is the power which would be indicated by a wattmeter
connected in the rectifying circuit with its voltage terminates placed across the
secondary winding and Pdc is the dc output power.
The degree of constancy is measured by load voltage regulation defined as:

No - load average voltage  Full - load average voltage

Load Regulation ¼
Full - load average voltage

2.9 Efficiency of Full-Wave Rectifier

Take V = Vm sin xt as the ac voltage given for rectification. RL and rF are load
resistance and diode resistance, respectively.
Then,

Pdc ¼ ðIdc Þ2 RL

for

2Im Vm
Idc ¼ and Im ¼
p rF þ RL

i.e.,
2.9 Efficiency of Full-Wave Rectifier 43

 2
2Im
Pdc ¼ RL
p

and

Pac ¼ ðIrs Þ2 ðrF þ RL Þ

or
 2
Im Im
Pac ¼ pffiffiffi ðrF þ RL Þ as Irms ¼ pffiffiffi
2 2

Thus,

Pdc ð2Im =pÞ2 RL 0:812RL

g¼ ¼  pffiffiffi2 ¼
Pac Im = 2  ðrF þ rL Þ rF þ R L

or

0:812
g¼

1 þ RrFL

i.e., the efficiency will be maximum if rF  RL .

Hence, maximum efficiency of a full-wave rectifier is 81.2% which is double of
half-wave rectifier.

2.10 Filters for Rectifiers

Rectifier output should be similar to a battery output. The rectifier output is pul-
sating dc which can be smoothened out using filter circuits. Figure 2.16 shows
schematic of a rectifier with a shunt capacitor filter. Input and output waveforms of
the filter are also shown.
There are several types of filters which are in use, but shunt capacitor serving as
a filter is most common. As shown in Fig. 2.16a, it is basically just a large value
capacitor which is connected across the full-wave rectifier and the load RL. The
pulsating input voltage is applied across the capacitor, and filter output is
smoothened. The capacitor changes the conditions under which the diodes conduct
as shown in Fig. 2.17. When the rectifier output is increasing, the capacitor charges
to peak value voltage Vm. Soon after, the rectifier voltage output tries to fall. As
soon as the source voltage becomes slightly less than Vm, the capacitor will try to
send current back through the diode. This reverse biases the diode; i.e., it becomes
44 2 Semiconductor Diodes

Fig. 2.16 Full-wave rectifier with a shunt capacitance filter

Fig. 2.17 Waveform output of shunt capacitor filter

open circuited. Thus, power source gets separated from the load. The capacitor
starts to discharge through the load which prevents the load voltage from falling to
zero. This continues to discharge until the source voltage becomes more than the
capacitor voltage. This cycle keeps on repeating. The rectifier supplies the charging
current through the capacitor branch as well as the load RL. Thus, current is
maintained through the load all the time at almost a constant value.
2.10 Filters for Rectifiers 45

Example 2.7 Sketch the output voltage v for the circuit given in the following
figure. Assume diodes D1 and D2 to be ideal diodes.

Solution: During positive half-cycles of input voltage, diode D1 is forward

biased and D2 is reverse biased. In this case, current flows through only one diode
D1. Thus, output vo is zero. During negative half-cycles of input voltage, diode D1
is reverse biased and diode D2 is forward biased; i.e., current flows through only
one diode D2. The voltage vo is given by:
Output voltage,

vi  5 kX
vo ¼
ð5 kX þ 5 kXÞ

or
vi
vo ¼ ¼ 5V
2

Thus, the output waveform sketch is as follows:

46 2 Semiconductor Diodes

Example 2.8 Sketch the output voltage waveform for the circuit given below.
Assume the diode is ideal.

Solution:
(a) For positive half-cycle: The input waveform circuit behavior and output
waveform are as follows:

The peak value of output

ð101120Þ 6:67
Vop ¼ 20  ¼ 20 
10 þ ð101120Þ 10 þ 6:67

or

Vop ¼ 8:0 volts:

(b) For negative half-cycle: The waveforms and circuit are as follows:
2.10 Filters for Rectifiers 47

Example 2.9 In the given circuit, calculate and sketch the waveform of current,
over one period of the input voltage. Assume the diodes to be ideal.

Solution:
Both D1 and D2 diodes conduct 0  xt  p2, where x ¼ 1 rad./sec .
If the voltage at node is V, then by applying KCL, we get

VA  cos t VA  sin t VA
þ þ ¼0
1 1 1

or

3VA ¼ cos t þ sin t

or

cos t þ sin t
VA ¼
3

or
48 2 Semiconductor Diodes

VA cos t þ sin t
i¼ ¼ . . .ðiÞ
1 3
p
During 2  xt  p, only diode D2 conducts as sin t is in positive half-cycle.
Thus,

sin t
i¼ . . .ðiiÞ
2

During p  xt  3p
2, none of the diodes conduct.

) i¼0

During 3p
2  xt  2p, D1 conducts and D2 does not conduct.

cos t
) i¼ :
2

The output waveform is given below:

cos t þ sin t cos 0 þ sin 0 1

i¼ ¼ ¼ for xt ¼ 0
3 pffiffi
3pffiffi 3
p p
pffiffiffi
cos 4 þ sin 4 2
þ 2 2
2 2 p
¼ ¼ 2 ¼ ¼ 0:5 for xt ¼
3 3 23 4

sin t sin p2 1 p
i¼ ¼ ¼ ¼ 0:5 for xt ¼ etc:
2 2 2 2
2.10 Filters for Rectifiers 49

Example 2.10 What is the ripple factor having rms value of 2 V on average of
50 V?
Solution: rms value of ac,

Vrms ¼ 2

Average value of voltage output,

Vac ¼ 50 V

Vrms 2
) Ripple factor ¼ ¼ ¼ 0:04
Vdc 50

Example 2.11 In a power supply, the dc output voltage drops from 44 V with
no-load to 42 V at full load. Calculate the percentage of voltage regulation.
Solution:
Given: No-load voltage,

VNL ¼ 44 V

Full-load voltage, VFL ¼ 42 V

VNL  VFL 44  42
) % Voltage regulation ¼  100 ¼  100
VFL 42
2
¼  100
42
¼ 4.76 %:

2.11 Clipping Circuits

Diode clipping circuits or clippers separate an input signal at a particular dc level

and pass the output without distortion, desired upper or lower portion of the original
waveform. Clippers are used to eliminate amplitude noise or to fabricate new
waveforms from an existing signal. There are two types of clippers—series and
parallel.
A simple series clipper is a half-wave rectifier as shown in Fig. 2.18a, wherein
input and output waveforms are also shown. It can be seen that the series config-
uration has the diode in series with load. The orientation of diode decides whether
positive or negative region of the applied voltage is “clipped off.” The addition of a
dc supply to the network has pronounced effect on the clipper output, i.e., can aid or
work against the source voltage. The dc supply gives biasing effect. Biased series
50 2 Semiconductor Diodes

Fig. 2.18 a Positive simple series clipper and input/output waveforms and b positive biased series
clipper and input/output waveforms

clippers with input and output waveforms are shown in Fig. 2.18b. A negative
simple series clipper with input/output waveforms is shown in Fig. 2.19a. Negative
biased series clippers with input/output waveforms are shown in Fig. 2.19b.
A parallel clipper has the diode in a branch parallel to the load. A positive simple
parallel clipper with input/output waveforms is shown in Fig. 2.20a. Positive biased
parallel clipper with input/output waveforms is shown in Fig. 2.20b.
A negative simple parallel clipper with input/output waveforms is shown in
Fig. 2.21a. Negative biased parallel clippers with input/output waveforms are
shown in Fig. 2.21b.
2.12 Clamping Circuits 51

Fig. 2.19 a A negative biased series clipper with input/output waveforms and b negative biased
series clippers with input/output waveforms

2.12 Clamping Circuits

A clamping circuit or clamper is a network made of a diode, a resistor and a

capacitor which shifts a waveform to a different dc level without changing the
appearance of the applied signal. Clamping circuits have a capacitor connected
directly from input to output with a resistive element in parallel with output signal.
Although diode is also in parallel with the output signal, it may or may not have a
series dc supply as an added element. A simple negative clamping circuit with
input/output waveforms is shown in Fig. 2.22a. Negative biased clamping circuits
with input/output waveforms are shown in Fig. 2.22b.
A simple positive clamping circuit with input/output waveforms is shown in
Fig. 2.23a. Positive biased clamping circuits with input/output waveforms are
shown in Fig. 2.23b.
52 2 Semiconductor Diodes

Fig. 2.20 a A positive simple parallel clipper with input/output waveform and b positive biased
parallel clippers with input/output waveforms

2.13 Voltage Multipliers

A voltage multiplier helps in giving dc output having multiple of peak of ac input.

A voltage multiplier circuit is a combination of two or more peak rectifiers. Voltage
multipliers can raise voltage level to hundreds or thousands of volts. Voltage
multipliers are classified as:
(i) Voltage doubler
(a) Half-wave voltage doubler
(b) Full-wave voltage doubler
(ii) Voltage trippler
(iii) Voltage quadrupler.
2.13 Voltage Multipliers 53

Fig. 2.21 a Negative simple parallel clippers with input/output waveforms and b negative biased
parallel clippers with input/output waveforms

2.13.1 Voltage Doubler

The circuit gives dc output voltage which is double of the peak of ac input voltage.
It can be half-wave voltage doubler or full-wave voltage doubler.

2.13.2 Half-Wave Voltage Doubler

A half-wave voltage doubler circuit is shown in Fig. 2.24. The elements D1, C1 and
D2, C2 are used in the rectifier.
When during positive half-cycle D1 conducts and D2 is not conducting, capacitor
C1 changes up to dc peak value (Vm). But, during negative half-cycle D2 conducts
and D1 is not conducting, hence, capacitor C2 charges. During negative half-cycle,
54 2 Semiconductor Diodes

Fig. 2.22 a A simple negative clamping circuit with input/output waveforms and b negative
biased clamping circuits with input/output waveforms

the voltage across C1 is in series with the input voltage, and hence, the total voltage
across capacitor C2 is 2Vm. Thus, capacitor C2 charges to the voltage 2Vm.
In the next positive half-cycle, D2 is not conducting, and hence, capacitor C2 will
discharge through the load. Both the diodes D1 and D2 should have a peak inverse
voltage (PIV) of 2Vm each.

2.13.3 Full-Wave Voltage Doubler

A full-wave voltage doubler circuit is shown in Fig. 2.25. During positive

half-cycle, diode D1 conducts and charges capacitor C1 to a peak voltage Vm. Diode
D2 does not conduct during this period. Diode D2 conducts during negative
2.13 Voltage Multipliers 55

Fig. 2.23 a A simple positive clamping circuit with input/output waveforms and b positive biased
clamping circuits with input/output waveforms

Fig. 2.24 A half-wave voltage doubler

half-cycle, and capacitor C2 charges to peak voltage Vm. Diode D1 does not conduct
during this period. Thus, peak voltage 2Vm is supplied to load RL. The peak inverse
voltage (PIV) of each diode in this case is equal to 2Vm. It may be noted that
center-tapped transformer is not needed in this circuit.
56 2 Semiconductor Diodes

Fig. 2.25 A full-wave

voltage doubler circuit

Fig. 2.26 A voltage trippler

and quadrupler circuit

2.13.4 Voltage Trippler and Quadrupler

A voltage trippler and quadrupler circuit are shown in Fig. 2.26. It can be seen
that conduction of D1 charges C1 during positive half-cycle Vm peak value.
Conduction of D2 charges C2 to peak value 2Vm produced by sum of source and
capacitor C1 voltage. During the second positive half-cycle, D3 will conduct and
peak voltages C1 and source V1 will charge C3 to 2Vm peak voltage. During second
negative half-cycle, diodes D2 and D4 will conduct leading to C3 charging C4 to the
same peak value 2Vm.
Thus, it can be seen that voltage across C1, C1; C3, C2; and C4 are 2Vm, 3Vm and
4Vm, respectively; i.e., voltage multiplied is 2, 3 and 4. Each diode PIV will be 2Vm.

2.14 Zener Diodes

Zener diodes operate in the breakdown region without damage, and these are
available from about 2 V to 200 V.
2.14 Zener Diodes 57

Fig. 2.27 Zener breakdown

characteristics

There is a point where the application of too negative a voltage will result in a
sharp change in the characteristics of a diode as shown in Fig. 2.27. The current
increases rapidly in a direction opposite to that of positive voltage region. The
reverse bias potential which gives this dynamic change in characteristics is known
as the zener potential (VZ).
The breakdown or zener voltage depends upon the amount of doping. Heavy
doping gives thin depletion layer, and breakdown of the junction will occur at a
lower reverse voltage. Light doping gives higher breakdown voltage.
If the voltage of the zener bias region increases, the reverse saturation current Is
will also increase. This aids the ionization process to the point where a high
avalanche current is established which establishes avalanche breakdown region.
Avalanche effect occurs due to accumulative action.
The external applied voltage accelerates the minority carriers in the depletion
region. They achieve sufficient kinetic energy to ionize atoms by collision. This
creates new electrons which are again accelerated to high-enough velocities to
ionize more atoms. This way, an avalanche of free electrons is obtained.
Thus, reverse current increases sharply. The avalanche region depends on the
doping as already discussed.

2.14.1 Zener Diode Functioning

It is a silicon junction diode which is operated under reverse bias and arranged to
breakdown when a specific reverse bias voltage is applied. Zener diode is a crystal
diode which is properly doped to have a sharp breakdown voltage. Figure 2.28
shows the symbol of a zener diode. It is like an ordinary diode except that the bar
is turned into Z-shape.
58 2 Semiconductor Diodes

Fig. 2.28 Zener diode

symbol
Anode Cathode

Fig. 2.29 Equivalent circuit

of a zener diode

2.14.2 Zener Resistance

The current through a zener diode produces a small voltage drop in addition to the
breakdown voltage. In breakdown region, variation of current through zener does
not give appreciable change in the voltage drop. Hence, it is generally ignored.
Zener diode equivalent circuit is shown in Fig. 2.29. It is equivalent to a
battery of voltage VZ in series with a resistance rZ. Resistance rZ is called dynamic
resistance or zener resistance of a zener diode. Zener resistance is zero for an ideal
diode. The value of dynamic resistance is:

DVZ
rZ ¼ :
DlZ

The zener resistance value lies in the range of few ohms to several hundred
ohms.

2.14.3 Zener “ON” and “OFF” States

In case reverse bias voltage across a zener diode is equal to or more than breakdown
voltage VZ, the current increases sharply. The curve will be almost vertical in this
region. This implies that the voltage across zener diode is constant at VZ even if the
current through it changes. Thus, breakdown region of an ideal zener diode will be
represented by a battery of voltage VZ; see Fig. 2.30. Zener diode is said to be in
“ON” condition in such situation.

Fig. 2.30 Zener is in “ON” state

2.14 Zener Diodes 59

Fig. 2.31 Zener is in “OFF” state

In case the reverse bias voltage across the zener diode is less than VZ but greater
than zero volt, the zener diode will be in “OFF” state. This case is represented by an
open circuit as shown in Fig. 2.31.
Example 2.13 A zener diode has a breakdown voltage of 10 V in the given circuit.
What are the minimum and maximum zener currents?

Solution: Minimum zener current ISMIN ¼ ð3010Þ V as voltage across the zener
820 X
shall be 10 V to breakdown voltage.

20
) IsMIN ¼ ¼ 24:4 mA:
820

Maximum zener current,

ð50  10Þ V
ISMax ¼
820 X

or

40
IsMAX ¼ ¼ 48:8 mA:
820 X
60 2 Semiconductor Diodes

2.14.4 Zener Regulator

Zener diode maintains a constant output voltage even though the current through it
as voltage regulator, see Fig. 2.32.
The current through resister Rs is

VS  VZ
IS ¼
RS

The practical zener diode will have some resistance rZ; therefore, VL is:

VL ¼ VZ þ IZ rZ

Normally, rz can be neglected; hence, VL is:

VL ¼ VZ

The load current,

VL
IL ¼
RL

Using KCL, we get:

IS ¼ IZ þ IL

or

IZ ¼ IS  IL :

Fig. 2.32 Zener regulator

2.14 Zener Diodes 61

This means that the zener current no longer equals the series current as it does in
an unloaded zener regulator. Due to load resistor, the zener current equals the
series current minus the load current.

2.15 Temperature Coefficient

Rise in the ambient temperature leads to slight changes in the zener voltage. The
effect of temperature is represented by temperature coefficient, which is the per-
centage change per degree change. Thus, calculation of zener voltage change at the
highest ambient temperature is essential. The temperature coefficient is negative for
zener diodes having the breakdown voltages less than 5 V. The temperature
coefficient is positive for zener diodes having the breakdown voltages more than
6 V. The temperature coefficient changes from negative to positive between 5 and
6 V. This implies that there is an operating point at which the temperature coeffi-
cient is zero. In case the zener voltage is to be kept constant over a large tem-
perature range in some applications, temperature coefficient is very important.
Example 2.14 A zener diode has zener voltage of 12 V and temperature coeffi-
cient a = 0.06%/°C. Calculate the change in zener voltage when ambient temper-
ature of 25 °C changes to 110 °C.
Solution: Change in zener voltage,
a
DV ¼ V   DT
100

or

0:06
DV ¼ 12   ð110  25Þ
100

or

DV ¼ 0:61 V:

Example 2.15 A zener diode has zener voltage of 3.3 V and temperature coeffi-
cient of a = – 0.062%/°C. Calculate the zener voltage when ambient temperature of
25 °C changes to 110 °C.
Solution: Change in zener voltage,
a
DV ¼ V   DT
100
62 2 Semiconductor Diodes

or
 
0:062
DV ¼ 3:3   ð110  25Þ
100

or

DV ¼ 0:17 V

Zener voltage,

V ¼ V þ DV

or

V ¼ 3:3  0:17 ¼ 3:13 V:

2.15.1 Zener Diode Ratings

The specification data of diodes are provided by the manufacturer in two forms.
They give a brief description limited to one page. They may also give the char-
acteristics using graphs, art work, tables, etc. The specifications or ratings of diode
must include the parameters given below. Ratings of BAY 73 diode are written in
the boards as an example of ambient temperature of 25 °C.
(i) Forward voltage VF at a specified current and temperature (0.60 − 0.68 V
for IF = 1.0 mA at 25 °C)
(ii) Maximum forward current IF at a specified temperature (500 mA at 25 °C)
(iii) Reverse saturation current IR at a specified voltage and temperature (0.5 nA,
VR = 100 V, TA = 25 °C)
(iv) Reverse voltage rating or peak inverse voltage (125 V at IR = 100 µA)
(v) Maximum power dissipation level at a particular temperature (500 mW at
25 °C)
(vi) Capacitance levels (8 pF at VR = 0, f = 1.0 MHz)
(vii) Reverse recovery time trr (3 µs at IF = 10 mA, VR = 35 V, RL = 1.0 to 100
kΩ)
(viii) Minimum reverse bias voltage (125 °C)
(ix) Operating temperature range (25 °C to 125 °C)
(x) Temperature coefficients
(xi) Dimensional specifications (diagram with dimensions).
2.16 Zener Diode Application as Shunt Regulator 63

2.16 Zener Diode Application as Shunt Regulator

It can be used as a voltage regulator to obtain a constant voltage from a source

voltage which may have large range of variation. The circuit diagram is shown in
Fig. 2.33. The zener diode is reverse connected as a shunt across the load RL. RS.
Series resistance absorbs the output voltage fluctuation such that desired constant
output voltage is maintained across the load RL. The zener will maintain a constant
voltage equal to its breakdown voltage Vz across load RL as long as input voltage Vi
does not fall below VZ+. The operating principle is as follows:
(i) If the voltage across RL is less than the zener breakdown voltage VZ+, then
the zener diode does not conduct; i.e., resistors Rs and RL become a potential
divider across Vi.
(ii) When the Vi voltage goes above Vz, the zener operates in the breakdown
region. Resistor Rs limits the zener current from exceeding its rated maxi-
mum current.
(iii) Once zener diode conducts, the voltage across it remains almost constant
although current Iz may vary appreciably.
(iv) In case, the load current IL increases, the current Iz reduces to maintain
current IS constant and voltage across load RL remains constant. Thus, the
current voltage VO remains constant.
(v) However, if the load current IL reduces, the current IZ increases to maintain
current. Thus, the output voltage VO remains constant.
(vi) If the input voltage Vi increases, the zener diode passes larger current so that
extra voltage is dropped across resistor RS. In case, the input voltage Vi
reduces, the zener diode current also reduces and the voltage drop across RS
is reduced. Thus, the output voltage VO remains constant. Fluctuations of Vi
have very little on VO as voltage drop across RS is of self-adjusting nature.

Fig. 2.33 Zener diode shunt voltage regulator

64 2 Semiconductor Diodes

2.17 Diodes for Optoelectronics

Optics and electronics combine to make optoelectronics. Some of the electronic

components of optoelectronics are light-emitting diodes (LEDs), photodiodes,
optocouplers, etc.

2.17.1 Light-Emitting Diodes (LEDs)

When a P–N junction diode is forward biased, the potential barrier is lowered, and
the electron and hole recombinations take place around the junction.
Recombinations of electrons and holes radiate energy. In ordinary diodes, this
energy is in the form of heat. However, semiconductor materials gallium arsenide
phosphide (GaAsP) and gallium phosphite (GaP) can cause radiation of red, green
or orange lights. A schematic diagram of LED and a seven-segment display using
LEDs are shown in Fig. 2.34.

2.17.2 Photodiode

A photodiode is based on principle of reverse current, and it is optimized for its

sensitivity to light. A window lets light pass through the package to junction. The
incoming light produces free electrons and holes. Figure 2.35 shows a circuit
containing photodiode. The arrows indicate the incoming light. The reverse current
is in tens of microamperes.

2.17.3 Optocoupler

Optocoupler or optoisolator combines a LED and photodiode in a single package.

A circuit containing an optocoupler is shown in Fig. 2.36. LED is on input side and

Fig. 2.34 LED symbol and display

2.17 Diodes for Optoelectronics 65

Fig. 2.35 Circuit with photodiode

Fig. 2.36 Optocoupler circuit

photodiode on output side. In the input circuit, the source voltage and series resistor
set up a current through LED. LED-emitted light hits the photodiode which set up a
reverse current in the output circuit. The reverse current produces a voltage across
the output resistor. Finally, the output voltage equals the output supply voltage
minus the voltage across the resistor. The output voltage varies in step with the input
voltage. Thus, combination of LED and photodiode, i.e., optocoupler, transfers input
signal from first circuit to second circuit. The advantage is that input and output
signals are electrically isolated from each other. With an optocoupler, the only
contact between two circuits is a beam of light. This gives an insulation resistance
between the two circuits in thousands of mega ohms. Optocouplers are used in
high-voltage applications where potentials of two circuits may differ by several
thousand volts or low-voltage computer signals are isolated from ac voltage circuits.

2.18 Other Types of Diodes

Other important types of diodes are signal diodes, power diodes, Schottky diode,
varactor and varistor. The signal diodes are normally having large reverse
resistance/forward resistance ratio and a minimum junction capacitance. They
66 2 Semiconductor Diodes

handle small currents and/or voltages. Most types of signal diodes have a PIV rating
in the range 30–150 V. The maximum forward current range may be from 40 mA
to 250 mA.
Power diodes handle large currents and/or voltages and are mostly used in
rectifiers. PIV rating is between 50 and 1000 V, and the maximum forward current
can be 30 A or even more. Power diodes are normally silicon diodes which help in
reducing the voltage drop across the diode when a large forward current flows. The
forward resistance is about one or two ohms. The reverse resistance is very high so
that almost no current flows through the diode when reverse biased.

2.18.1 Schottky Diode

Schottky diodes are special purpose diodes which can easily rectify frequencies
above 300 MHz. It does not have depletion layer which eliminates the stored
charges at junction; i.e., switching “ON” and “OFF” is faster than ordinary diode.
Schottky diodes are used in computers, and in fact, it is a backbone of low-power
TTL groups of devices.

2.18.2 Varactor

Varactor or varicap or epicap or tuning diode finds large applications in television

receivers, FM receivers and other telecommunication receivers. It is used in
reverse-biased condition. The depletion layer gets wider with more reverse voltage.
The P and N regions work as two plates of a capacitor. Thus, when reverse bias
voltage increases, the capacitor value reduces in short, at higher frequencies, and
the varactor acts as a variable capacitor. Figure 2.37 shows varactor symbol,
equivalent circuit and plot of capacitance versus reverse bias voltage.

2.18.3 Varistor

Varistor is a diode like two back-to-back zener diodes with a high breakdown
voltage in both directions. Varistor works as a transient suppressor. It protects from
lightening and power-line faults which can pollute the line voltage by superim-
posing dips, spikes and transients on normal 220 V supply. Dips are severe voltage
drops of microsecond duration. Spikes are short overvoltages of 500 V to over
2000 V.
2.18 Other Types of Diodes 67

Fig. 2.37 Varactor

Example 2.16 For the circuit of the given figure, find:

(a) the output voltage
(b) the voltage drop across RS
(c) the current through zener.

Solution:
(a) In output voltage,

VL ¼ VZ ¼ 50 V:

(b) Voltage drop across

Rs ¼ 120  50 ¼ 70 V:

(c) The load current,

50 V
IL ¼ ¼ 5 mA
10  103 X
68 2 Semiconductor Diodes

Current through resistor RS,

70 V
Is ¼ ¼ 14 mA
5  103 X

∴ Current through zener diode,

IZ ¼ IS  IL ¼ 14  5 ¼ 9 mA:

Example 2.17 For the circuit shown below, find (a) the output voltage, (b) voltage
across RS and (c) the current through zener diode.

Solution:
(a) Output voltage,

Vo ¼ VZ ¼ 8 V:

(b) Voltage drop across

RS ¼ 12  Vo ¼ 12  8 ¼ 4 V:

(c) Current through zener diode,

IZ ¼ IS  IL

Load current,

Vo 8V
IL ¼ ¼ ¼ 0:8 mA
RL 10 kX

Current through series resistor RS,

2.18 Other Types of Diodes 69

12  8
IS ¼
RS
4V
¼ ¼ 0:8 mA:
5 kX

∴ Current through zener diode,

IZ ¼ IS  IL
¼ ð0:8  0:8ÞmA ¼ 0:

Example 2.18 For the circuit shown below, find the maximum and minimum
values of zener diode current.

Solution: Voltage across 10 kΩ resistor Vo- = VZ = 50 V.

Current through 10 kΩ resistor,

50
IL ¼
10  103
¼ 5 mA:

Maximum current through 5 kΩ resistor,

Maximum source voltage  Vo

ISmax ¼
5 kX
120  50
¼ ¼ 14 mA
5  103

∴ Maximum zener current,

IZmax ¼ ISmax  IL ¼ 14  5 ¼ 9 mA:

Minimum current through 5 kΩ resistor,

70 2 Semiconductor Diodes

Minimum source voltage  Vo

Ismin ¼
5 kX
80  50
¼ ¼ 6 mA:
5  103

∴ Minimum Zener current,

IZmin ¼ 6  5 ¼ 1 mA:

Example 2.19 Determine VL, IZ and PZ for the circuit shown below.

Solution: Suppose zener diode in the circuit is not conducting, then the circuit
has zener diode like open. The circuit looks as follows:

Load voltage,

16 V  1:2 kX
VL ¼
1 kX þ 1:2 kX

or

16  1:2
VL ¼ ¼ 8:73 V:
2:2

The load voltage VL is less than zener breakdown voltage VZ = 10 V; therefore,

zener diode does not conduct at all.
Thus,
2.18 Other Types of Diodes 71

Iz ¼ 0:

and

PZ ¼ IZ  VZ ¼ 0  8:73 ¼ 0 X:

Summary
1. Diode Symbol: The diode symbol looks like an arrow which points in the easy
direction of conventional current flow. The opposite way is the easy direction
for electron flow. The P-side is known as anode, and the N-side is known as
cathode.

2. Diode Characteristics: V–I characteristic is a plot of forward bias and reverse

bias currents versus external voltage applied across the diode. The characteristic
is nonlinear. Very high current flows in the forward-biased diode, and only a
small current flows in a reverse-biased diode.
3. Knee Voltage: The forward region has a segment known as knee voltage. This
voltage is approximately equal to the barrier potential of the diode.
A current-limiting resistor is always used to prevent the current from exceeding
the maximum rating.
4. Diode Current Equation: The diode current equation is given by:

VF 

IF ¼ IS e g VT  1

where
IF = forward diode current.
IS = reverse diode current at room temperature.
VF = external voltage applied to the diode.
h = a constant, 1 for Ge and 2 for Si, and the voltage equivalent of temperature
is given by:

kT
VT ¼
q

where
k = Boltzmann’s constant = 1.38  10−23 J/K.
q = electronic charge = 1.6  10−19 C.
T = diode junction temperature in (K).
72 2 Semiconductor Diodes

5. Ideal Diode: The ideal diode is visualized as a switch which automatically

closes when forward biased and opens when reverse biased.

VS  VF
R¼
IF

6. Forward Resistance:

g VT
rF ¼
IF

7. Diode Approximation:

VF ¼ VT þ IF rF

where VT = barrier potential, 0.7 V for Si, 0.3 V for Ge and 1.2 V for GaAs.
8. Current-Limiting Resistor:

VS  VF
R¼
IF

9. Forward Current Approximation:

VS  VB
IF ¼ :
R þ rF

10. Data Sheet: It specifies the characteristics of semiconductor devices. The data
sheet of a diode contains useful information such as breakdown voltage,
maximum forward current, forward voltage drop and maximum reverse current.
11. Input Transformer: A step-down transformer is used in rectifiers. It may be
center tapped in secondary winding.
12. RMS Voltage:

Vrms ¼ 0:707 Vm :

13. Half-Wave Rectifier: It has a diode in series with a load resistor. The load
voltage is a half-wave rectified sine wave with a peak value approximately
equal to the peak secondary voltage.

Vdc ¼ 0:318 Vm :
2.18 Other Types of Diodes 73

14. Full-Wave Rectifier: It has a center-tapped transformer with two diodes and a
load resistor. The load voltage is a full-wave rectified sine wave with a peak
value approximately equal to half of the peak secondary voltage.

Vdc ¼ 0:636 Vmc

15. Bridge Rectifier: It has four diodes. The load voltage is a full-wave rectified
sine wave with a peak value approximately equal to peak secondary voltage.

Vdc ¼ 0:636 Vm

fout ¼ 2fin

16. Capacitor-Input Filter: It is a capacitor across the load resistor which charges
to the peak voltage and supplies the current to the load when the diodes are not
conducting. A large capacitor gives small ripple, and the load voltage is almost
a pure dc voltage.
17. Diode Current for Full-Wave Rectifier:

IF ¼ 0:5 IL

18. Peak Inverse Voltage (PIV):

For a full-wave rectifier:

PIV ¼ peak secondary voltage of the transformer:

19. Ripple Factor (r):

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
 2
Irms
r¼ 1
Idc

20. Clipper: A circuit which shapes the waveform by removing or clipping a

portion of the applied input signal waveform without distorting the remaining
part.
21. Chamber: A circuit which shifts or clamps a signal to different dc levels.
22. Voltage Multiplier: A circuit which produces dc output whose value is mul-
tiple of peak ac input voltage.
23. Zener Diode: A special diode optimized for operation in the breakdown region.
It is used as voltage regulator.
74 2 Semiconductor Diodes

24. Loaded Zener Regulator: Zener diode is connected in parallel with a load
resistor. The current through the current-limiting resistor equals the sum of the
zener current and the load current.
25. Optoelectronic Diodes: Light-emitting diodes (LEDs) radiate light when in
breakdown condition. These are used as indicators. By combining seven LEDs
in a package, a seven-segment indicator/display is created.
Photodiode is another optoelectronic diode. It is optimized for its sensitivity to
light. Optocoupler is a combination of LED and photodiode in a light package
which serves as electrical isolator for sensitive circuits.
26. Schottky Diode: It is a special diode which is useful at high frequencies where
short switching times are needed. It is used generally for frequencies above
300 MHz.
27. Varactor: The reverse-biased P–N junction works like a plate of capacitor. The
capacitance so created is varied by controlling the reverse voltage.
28. Varistor: It is like two back-to-back zener diodes with a high breakdown
voltage in both directions. It is used as a spibe suppressor.
Exercises
2:1. Explain how a barrier potential is developed at the P–N junction.
2:2. Explain the action of P–N junction diode under forward bias and reverse
bias.
2:3. Draw and explain the V–I characteristics of a P–N junction diode.
2:4. Differentiate between transition capacitance and diffusion capacitance of a
P–N junction diode.
2:5. What is static resistance of diode? How will you find the dynamic resistance?
2:6. Explain the formation of potential barrier in P–N junction. Why is silicon
preferred to germanium in the manufacturing of semiconductor device?
2:7. For a semiconductor diode, define static and dynamic resistance.
2:8. Plot the hole current, the electron current and the total current as a function of
distance on both the sides of a P–N junction. Indicate the transition region.
2:9. When a reverse bias is applied to a germanium diode, the reverse saturation
current at room temperature is 0.3 µA. What is the value of current flowing in
the diode when 0.15 V forward bias is applied at room temperature? [Ans.
120.73 µA].
2:10. A semiconductor diode has a forward 72 bias of 200 mV and reverse satu-
ration current of 1 µA at room temperature. Find ac resistance of the diode
[Ans. 11.86 Ω].
2:11. The figure given below shows the circuit of series diode configuration. What
is the value of VF, VR and IF ? [Ans. 0.7 V, 7.3 V, 3.65 mA].
2.18 Other Types of Diodes 75

2:12. A series diode configuration circuit is given below. What is the value of VR
and IF ? [Ans. 11 V, 2.5 mA].

2:13. A series diode configuration circuit is given. What are the values of VR1, VR2
and Vo ? [Ans. 2.38 mA, 9.52 V, 4.76 V, –0.24 V].

2:14. A parallel diode configuration circuit is shown in the figure given below.
What are the values of Vo, I, IF1 and IF2 ? [Ans. 0.7 V, 33.1 mA, 16.5 mA,
16.5 mA].
 76 2 Semiconductor Diodes

2:15. What is a resistance for a semiconductor diode with a forward bias of 0.25 V ?
Reverse saturation current at room temperature is of 1.2 µA [Ans. 1.445 W].
2:16. Determine the current flowing in the circuit shown below.

2:17. Determine the current through 2 kΩ resistor in the circuit given below [Ans.
1.205 mA].
2.18 Other Types of Diodes 77

2:18. A half-wave rectifier uses a diode with an equivalent forward resistance of

0.3 Ω. If the input ac voltage is 10 V (rms) and the load is a resistance of
20 Ω, calculate Idc and Irms in the load [Ans. 1.958 A, 3.075 A].
2:19. A zener diode shunt regulator circuit is shown in the figure given below. Find
the zener current for the load resistances of 30 kΩ, 10 kΩ and 3 kΩ.

2:20. A 10 V regulated dc supply of 10 mA is required from a dc source of 12–

15 V by using a pair of zener diodes. Take IZ min = 0.2 mA; during the
circuit, find the value of RS and power rating of zener diodes [Ans.
Rs = 196 W, Power rating of zener = 255 mW].
Chapter 3
Bipolar Junction Transistor (BJT)

3.1 Basic Construction

Bipolar junction transistor (BJT) was invented by Shockley in 1951 to amplify

radio and TV signals. BJT replaced the vacuum tube which needed heater for its
internal filament requiring watt power. The word bipolar is an abbreviation for “two
polarities”. The word transistor is a combination of transfer and resistance as it
transfers the resistance from one end of the device to the other end. We know that
simple diodes are made up of two pieces of semiconductor either silicon or ger-
manium to form a simple P–N junction. If we join together two individual diodes
end to end giving two P–N junctions combined together in series, we now have a
three-layer, two-junction, three-terminal device forming the basic bipolar junction
transistor (BJT) as shown in Fig. 3.1. Thus, a construction of a transistor has three
doped regions giving three terminals.
Outer two terminals are known as emitter and collector, whereas the middle
terminal is known as base; there are two basic types of transistor construction, PNP
and NPN, which basically describes the physical arrangement of the P-type and N-
type semiconductor materials from which they are made. Transistor construction is
shown in Fig. 3.2. Transistors are current amplifying and regulating devices. The
principle of operation of the two transistor types PNP and NPN is exactly the same,
only difference being in the biasing (base current) and the polarity of power supply
for each type. Circuit symbols for both PNP and NPN transistors are shown in
Fig. 3.3. The arrow in the circuit symbol always shows the direction of conven-
tional current flow between the base terminal and its emitter terminal. The direction
of the arrow points from the positive P-type region to the negative N-type region,
exactly same as for the standard diode symbol. Current direction can also be
derived by treating terminals as positive–negative–positive (PNP) and negative–
positive–negative (NPN).

© The Author(s), under exclusive license to Springer Nature Switzerland AG 2022 79

O. N. Pandey, Electronics Engineering,
https://doi.org/10.1007/978-3-030-78995-4_3
80 3 Bipolar Junction Transistor (BJT)

Fig. 3.1 Two individual diodes joined together

Fig. 3.2 PNP and NPN transistors

Fig. 3.3 Symbolic form

3.2 Transistor Action

The emitter base junction is forward-biased, whereas collector base junction is

reverse-biased for active operating as shown in Fig. 3.4. The forward bias of the
emitter base causes the emitter current to flow. It can be observed that almost all
emitter current flows in the collector circuit. Thus, current in the collector circuit
depends on the emitter current; i.e. when the emitter current is zero, the collector
current is almost zero. Suppose the emitter current is 1 mA, then the collector
current is also near about 1 mA. This is the basic function of a transistor.

3.2.1 Working of PNP Transistor

Consider that a PNP transistor has a forward bias on emitter–base and reverse bias
on collector–base junction as shown in Fig. 3.5. Forward bias on emitter base
causes the holes in P-type emitter to flow towards the base. The holes cross into the
3.2 Transistor Action 81

Fig. 3.4 PNP and NPN transistors biased for active operation

Fig. 3.5 Biased PNP

transistor

N-type base which constitutes the emitter current IE. They have tendency to com-
bine with the electrons. The base is lightly doped and also very thin; hence, just few
holes (less than 5%) combine with electrons. Remaining (more than 95%) cross into
collector region to constitute collector current IC. Thus, almost all the emitter
current flows into the collector circuit. It should be noted that current flow within
PNP transistor is due to movement of holes, although current in external wires is by
electrons. It can be observed that the emitter current is the sum of collector and base
currents, i.e. IE ¼ IB þ IC .

3.2.2 Working of NPN Transistor

Consider that a NPN transistor has a forward bias on emitter–base and reverse bias
on collector–base junction as shown in Fig. 3.6. Due to forward bias, electrons in
N-type emitter flow towards the base. This constitutes the emitter current IE. These
electrons flow through the P-type base where they tend to combine with holes. The
base is lightly doped and also is very thin; hence, just a few electrons (less than 5%)
combine with the holes to constitute base current IB. Remaining electrons (more
82 3 Bipolar Junction Transistor (BJT)

Fig. 3.6 Biased NPN

transistor

than 95%) cross over into the collector region which constitutes collector current IC.
It is clear that: IE ¼ IB þ IC .

3.3 Circuit Configurations

There are three possible configurations to connect a transistor within an electronic

circuit. Each configuration responds differently as the characteristics vary with each
type of circuit arrangement with regard to the input signals. The configurations are
common base having voltage gain but no current gain; common emitter having both
voltage gain and current gain; and common collector having current gain but no
voltage gain.

3.3.1 Common-Base (CB) Configuration

Common-base or grounded base configuration is shown in Fig. 3.7. The base is

common to both the input signal and output signal. The input signal is applied
between base and emitter terminals. The output signal is taken from between the
base and the collector terminals. The base terminal is grounded or connected to a
fixed reference voltage point. The current flowing through the emitter is quite large
as base and emitter junction is forward-biased. The flow through collector is very
small as base and collector junction is reverse-biased. Thus, the collector current
output is less than the emitter current input resulting in current gain less than one;
i.e., it “attenuates” the input signal. Common-base configuration is non-inverting

Fig. 3.7 Common-base

amplifier circuit
3.3 Circuit Configurations 83

voltage amplifier circuit with input signal voltage and output voltage being on
phase. This configuration is not very common due to its usually high-voltage
characteristics. It has a high output to input resistance. The important aspect is that
load resistance (RL) to input resistance (Rin) gives gain value of “resistance gain”.
Thus, the voltage gain for common base can be written as:

IC  RL RL
AV ¼ ¼a ð3:1Þ
IE  RIN RIN

The common-base configuration is normally used in single state amplifier cir-

cuits such as microphoto amplifier or RF radio amplifiers as it has very good high
frequency response.

3.3.2 Common-Emitter (CE) Configuration

Common-emitter or grounded emitter configuration is shown in Fig. 3.8. The

input signal is applied between base and emitter, while output signal is picked up
between collector and emitter. This configuration is generally used for transistor-
based current amplifiers; it produces the highest voltage–current and power gain of
all of the three transistor configurations. The input impedance is low as the ter-
minals are forward-biased, and output impedance is high as the terminals are
reverse-biased.
From the circuit of Fig. 3.5, we know:

IE ¼ IC þ IB

where IE is current flowing out of amplifier, IC is current flowing into the collector
and IB is the current flowing into the base, and the current gains are given by:

IC
a¼ ð3:2Þ
IE

Fig. 3.8 Common-emitter

amplifier circuit
84 3 Bipolar Junction Transistor (BJT)

and

IC
b¼ ð3:3Þ
IB

or

b
a¼ ð3:4Þ
bþ1

and
a
b¼ ð3:5Þ
1a

In short, common-emitter configuration has greater input impedance, current and

power gain than that of the common-base configuration but its voltage gain is much
lower. It is an inverting amplifier circuit resulting in the output signal being 180°
out of phase with the voltage signal.

3.3.3 Common-Collector (CC) Configuration

Common-collector or grounded collector configuration is shown in Fig. 3.9. The

collector is common, the input signal is connected to the base, and the output is
taken from the emitter load. This configuration is known as a voltage follower or
emitter follower circuit. This configuration is very useful for impedance matching
applications because of its high input impedance in the range of hundreds of
thousands of ohms, and its output impedance is relatively low.
The current and gain relationships are as follows:

IE ¼ IC þ IB

Fig. 3.9 Common-collector

amplifier circuit
3.3 Circuit Configurations 85

and

IE IC þ IB
Ai ¼ ¼
IB IB

or

IC
Ai ¼ þ1
IB

or

Ai ¼ b þ 1 ð3:6Þ

The common-collector configuration is a non-inverting amplifier circuit, wherein

the input signal is in phase with the output signal. In this case, voltage gain is
always less than unity and provides good current amplification.

3.4 Input/Output Characteristics

Characteristic curves give complete behaviour of a transistor. These are relation-

ships of transistor current and voltages. The relationship of input current and input
voltage (for a value of output voltage) is known as input characteristics. The
relationship of output current and output voltage for a value of input current is
known as output characteristics.

3.4.1 CB Characteristics

The input characteristics for the common-base amplifier are shown in Fig. 3.10 for
a silicon transistor. It relates input current (IE) to an input voltage (VBE) for various
levels of output voltage.
The output characteristics for the common-base amplifier are shown in Fig. 3.11.
It relates output current (IC) to an output voltage (VCB) for various levels of input
current (IE).
The output characteristics have three basic regions known as active, cut-off and
saturation as shown in the figure. Active region is used for linear amplifiers. In this
case, base–emitter is forward-biased and collector–base is reverse-biased.
In the cut-off region, the emitter current (IE) is zero and the collector current is
not zero. It has a small value which is a leakage current Icbo. In this region,both the
functions are reverse biased, therefore, a small increase in Vcb results in a large
increase in the collector current.
86 3 Bipolar Junction Transistor (BJT)

Fig. 3.10 Input

characteristics of CB
transistor (silicon) amplifier

Fig. 3.11 Output

characteristics of CB
transistor amplifier

Current amplification factor, a ¼ DI

DIE ða ¼ 0:9 to 0:99Þ
C

Total collector current; IC ¼ aIE þ ICBO ð3:7Þ

where ICBO = collector to base current where emitter is open and very small in mA,
so may be ignored.

3.4.2 CE Characteristics

The input characteristics of the common-emitter amplifier are shown in Fig. 3.12
for a silicon transistor. It relates input current (IB) to an input voltage (VBE) for
various levels of output voltage. Input resistance,
3.4 Input/Output Characteristics 87

Fig. 3.12 Input

characteristics of CE
transistor (silicon) amplifier

DVEB
ri ¼ at constant VCB :
DIE

(very small few ohms) VCB and output resistance,

DVCB
ro ¼ at constant IE (very high in terms of kXÞ.
DIC

Fig. 3.13 Output characteristics of CE

88 3 Bipolar Junction Transistor (BJT)

The output characteristics for the common-emitter amplifier are shown in

Fig. 3.13. It relates output current (IC) to an output voltage (VCE) for various levels
of input current (IB), and saturation regions are marked.
In the active region of common-emitter amplifier, the base–emitter junction is
forward-biased and the collector–emitter junction is reverse-biased.
Current amplification factor,

DIC
b¼ ð20  500Þ
DIB

For dc values,

IC
bdc ¼ :
IB

Input resistance,

DVBE
ri ¼ at constant VCE (few hundred ohms)
DIB

Output resistance,

DVCE
ro ¼ at constant IB (in the order of 50 kXÞ
DIC

Collector current

IC ¼ bIB þ ICEO

where ICEO = collector to emitter current when base is open.

3.4.3 CC Characteristics

Common-collector configuration is used for impedance matching as it has a high

input impedance and low output impedance, i.e. opposite to that of the CB and CE
configurations. There is no need of CC characteristics from design point of view.
The output characteristics of CC (IEversus VCE) for a range of values IB are same as
for CE configuration with IE ’ IC (as a ’ 1) and VCE = negative of VCE (in CE
configuration). Input characteristics of CC configuration common-emitter base
characteristics are capable of giving the required information.
3.5 Mathematical Relationships 89

Fig. 3.14 Transistor current

relationships

3.5 Mathematical Relationships

3.5.1 Relation Between b and a

Transistor current relationships are shown in Fig. 3.14.

We know IE ¼ IB þ IC
or

DIE ¼ DIB þ DIC

but

DIC DIC
b¼ ¼
DIB DIE  DIC
DIC =DIE
¼
ðDIE =DIE Þ  ðDIC =DIE Þ

or
a DIC
b¼ a¼
1  a as DIE

i.e. if a ! 1; b ! 1. Thus, current gain in common emitter is very high.

3.5.2 Relation Between ICEO and ICBO

We know
IC ¼ aIE þ ICBO
¼ aðIB þ IC Þ þ ICBO
90 3 Bipolar Junction Transistor (BJT)

or

ð1  aÞIC ¼ aIB þ ICBO

or

a ICBO
IC ¼ IB þ ð3:8Þ
1a 1a

and

IC ¼ bIB þ ICEO ð3:9Þ

From (3.8) and (3.9), we get:

ICBO
ICEO ¼ ð3:10Þ
1a

3.6 Biasing of Transistors

Biasing of a transistor is application of dc voltages to establish a fixed level of

current and voltage. It is also known as operating point or quiescent (Q) point.
Consider use of a transistor as an amplifier. Normal requirement is that the output
should be a faithful amplification of input signal without any change in the shape.
Figure 3.15 shows conditions of proper biasing of the common-base amplifier in
the active region wherein IC ’ IE , i.e. IB ’ 0, i.e. as though base is open circuited.
The dc supplies are then incorporated with a polarity that will support the resulting
current direction.
Figure 3.16 shows conditions of proper biasing of a common-emitter amplifier
in the active region. The dc supplies are incorporated with polarities which will
support the established direction of IE as per arrow of the transistor and other
currents as per Kirchhoff’s current law, i.e.

Fig. 3.15 Biasing condition

of common-base PNP
transistor in active region
3.6 Biasing of Transistors 91

Fig. 3.16 Proper biasing

condition of a
common-emitter NPN
transistor

IC þ IB ¼ IE

The important relationship in each configuration is given by:

VBE ¼ 0:7 V
IE ¼ ðb þ 1ÞIB ’ IC ð3:11Þ
IC ¼ bIB

3.6.1 Fixed Bias

It is the simplest transistor dc bias configuration as shown in Fig. 3.17. The

capacitors in the circuit are treated as open for dc analysis, i.e.
XC ¼ 2p1f C ¼ 1 as f = 0 for dc analysis. The base−emitter loop gives:

Fig. 3.17 Fixed-bias circuit of a NPN transistor

92 3 Bipolar Junction Transistor (BJT)

VCC  IB RB  VBE ¼ 0

or
VCC  VBE
IB ¼ ð3:12Þ
RB

The collector–emitter loop gives:

IC ¼ bIB

It is also important to remember that the collector current is not dependent on the
load in the active region. By KVL in the collector–emitter loop, we get:

VCE þ IC RC  VCC ¼ 0

or

VCE ¼ VCC  IC RC :

Consider the circuit of Fig. 3.17. It gives the equation for load line:

VCE ¼ VCC  IC RC

or
VCC  VCE
IC ¼ ð3:13Þ
RC

The load line is superimposed on the output characteristics as shown in

Fig. 3.18.
We choose the curve for IB current (say 20 mA) and the intersection point with
load line as Q. Point Q is the operating point.

3.6.2 Emitter Bias

A dc bias circuit is shown in Fig. 3.19. It contains an emitter resistance to improve

the stability level over that of the fixed-bias configuration.
By applying KVL in base–emitter loop, we get:

VCC  IB RB  VBE  IE RE ¼ 0

We know that:

IE ¼ ðb þ 1ÞIB
3.6 Biasing of Transistors 93

Fig. 3.18 Fixed-bias load line

Fig. 3.19 Emitter bias circuit

with emitter resistor

By substituting value of IE in the loop equation, we get:

VCC  IB RB  VBE  ð~
b þ 1ÞIB RE ¼ 0

or
VCC  VBE
IB ¼ ð3:14Þ
RB þ ðb þ 1ÞRE

By applying KVL in collector–emitter loop, we get:

94 3 Bipolar Junction Transistor (BJT)

IE RE þ VCE þ IC RC  VCC ¼ 0

By taking IE ’ IC , we get:

VCE ¼ VCC  IC ðRC þ RE Þ ð3:15Þ

The voltage from emitter to ground is:

VE ¼ IE RE

and voltage from collector to ground is:

VC ¼ VCE  VE

or

VC ¼ VCC  IC RC ð3:16Þ

The voltage from base to ground is:

or

VB ¼ VBE þ VE ð3:17Þ

Saturation Level
The collector current at or the collector saturation level for an emitter- bias circuit
can be determined by applying short circuit between collector and emitter is
VCE = 0, we get:

VCC
IC sat ¼ ð3:18Þ
RC þ RE

Load line analysis of the improved bias stability will be same except that it will
follow the equation:

VCC  VCE
IC ¼ ð3:19Þ
RC þ RE
3.6 Biasing of Transistors 95

3.6.3 Voltage Divider Bias

The bias current ICQ and VCEQ are dependent on parameter b which is temperature
sensitive, particularly for silicon transistors. Voltage divider bias circuit as shown
in Fig. 3.20 is independent of b parameter as change in b is very small. The analysis
of the circuit can be exact or approximate.

3.6.3.1 Exact Analysis

The supply between base and ground, i.e. input side, can be represented as shown in
Fig. 3.21.
The venin equivalent values are:

Fig. 3.20 Voltage divider

bias circuit

Fig. 3.21 Input side of the

transistor
96 3 Bipolar Junction Transistor (BJT)

Fig. 3.22 Input portion

circuit using Thevenin
equivalent

RTH ¼ R1 k R2 ; ðVCC is taken as short circuitÞ

R2 VCC
VTH ¼ ð3:20Þ
R1 þ R2

The input portion of circuit can be redrawn along with the transistor as shown in
Fig. 3.22.
By applying KVL, we get:

VTH  IB RTH  VBE  IE RE ¼ 0

The above equation after substituting IE ¼ ðb þ 1Þ IB gives:

VTH  VBE
IB ¼ ð3:21Þ
RTH þ ðb þ 1ÞRE

It can be observed that RTH is large and effect of b is very much reduced.
By applying KVL from VCC to ground through collector and emitter circuit, we
get:

VCE ¼ VCC  IC ðRC þ RE Þ ð3:22Þ

3.6.3.2 Approximate Analysis

The input circuit along with base to emitter and ground can be represented as shown
in Fig. 3.23.
Now, if Ri  R2, then

IB ¼ 0; i.e:; I1 ’ I2 :
3.6 Biasing of Transistors 97

Fig. 3.23 Input circuit

through base–emitter and
ground

Hence,

R2  VCC
VB ¼ ð3:23Þ
R1 þ R2

Further,

Ri ¼ ðb þ 1ÞRE ’ bRE :

∴ The condition for R1 to be very large than R2 is taken as:

bRE  10R2

We can also conclude:

VE ¼ VB  VBE

VE
IE ¼
RE

ICQ ’ IE

VCE ¼ VCC  IC RC  IE RE

Taking IE ’ IC , we get:

VCEQ ¼ VCC  IC ðRC þ RE Þ ð3:24Þ

Transistor saturation equation is given by:

VCC
IC sat ¼ IC max ¼
RC þ RE
98 3 Bipolar Junction Transistor (BJT)

The load line equation is given by:

VCC


IC ¼
RC þ RE
VCE ¼0

and
VCE ¼ VCC jIC ¼0 mA

3.6.4 DC Bias with Voltage Feedback or Collector Bias

A feedback path from collector to base improves level of stability. Consider circuit
of Fig. 3.24 which is having a voltage feedback from collector.
It may be noted that it is dc analysis; hence, C1 and C2 look as though open
 
1
XC ¼ ¼ 1 for f ¼ 0 :
2pfC

By KVL around the loop from VCC to RC, RB, base, emitter, RE and ground, we
get:

VCC  IC0 RC  IB RB  VBE  IE RE ¼ 0

We know that:

Fig. 3.24 DC bias circuit

with voltage feedback
3.6 Biasing of Transistors 99

IC0 ¼ IC þ IB ; i.e: IC0 ¼ IC as IB is very small compared to IC

and also

IC0 ’ IC ¼ bIB and IE ’ IC :

Hence, the loop equation becomes:

VCC  bIB RC  IB RB  VBE  bIB RE ¼ 0

or

VCC  VBE
IB ¼ ð3:25Þ
R B þ bð I C þ R E Þ

bðVCC  VBE Þ
ICQ ¼ bIB ¼
RB þ bðIC þ RE Þ

or

VCC  VBE
ICQ ¼ for RB  bðIC þ RE Þ ð3:26Þ
IC þ R E

The collector–emitter loop through RC and RE gives:

IE RE þ VCE þ IC0 RC  VCC ¼ 0

Taking IC0 ’ IC and IE ’ IC , we get:

IC ðRC þ RE Þ þ VCE  VCC ¼ 0

or

VCE ¼ VCC  IC ðRC þ RE Þ ð3:27Þ

3.6.5 Comparison of Biasing Circuits

1. Fixed-Bias Circuit: The values of collector current IC and collector–emitter

voltage VCE are dependent upon the value of b which varies with temperature.
This implies that operating point Q will change with change in b due to tem-
perature variation. Thus, a stable Q-point cannot be achieved in a fixed-bias
circuit. Therefore, it is rarely used.
100 3 Bipolar Junction Transistor (BJT)

2. Collector to Base Bias: Collector to base biasing has greater stability than
fixed-bias circuit.
3. Voltage Divider Bias: The voltage divider or salt bias circuit gives stability in
operating point Q as it is almost independent of b value. Further, even same type
of transistor can have different values of b and this also does not affect the
stability of point Q.
4. Emitter Bias Circuit: Similar to voltage divider bias, this circuit also provides
almost same stability of operating point Q.

3.7 Graphical Analysis of CE Amplifier

This method requires output characteristics of the transistor which are supplied by
the manufacturer. Application of the ac voltage to the input gives variations in base
current. The corresponding collector current and collector voltage variation can be
seen on the characteristics. The graphical method does not involve any approxi-
mations; therefore, the results obtained are more accurate than the equivalent circuit
method. The maximum ac voltage which can be properly handled by the amplifier
can also be visualized. Graphical method is the only suitable method for large
signal amplifiers, i.e. power amplifiers.
In order to understand this method, a common-emitter (CE) amplifier circuit of
Fig. 3.25 is considered.
The dc load line (circuit is shown in the figure) equation is given by (Fig. 3.26):

VCC  VCE VCC  VCE

IC ¼ ¼ ;
RC þ RE Rdc
Rdc ¼ 1 kX to 0:1 kX ¼ 1:1 kX

For, VCE = 0,

Fig. 3.25 A common-emitter amplifier circuit

3.7 Graphical Analysis of CE Amplifier 101

Fig. 3.26 CE amplifier

circuit in dc condition

VCC 9V
IC ¼ ¼ ¼ 8:2 mA
Rdc 1:1 kX

For, IC = 0, we get:

VCC  VCE
0¼ or VCE ¼ VCC ¼ 9 V
Rdc
 
The dc load line has a slope of  R1dc and is drawn using points (9 V, 0) and (0,
8.2 mA) on the transfer output characteristics in Fig. 3.27. The operating (quies-
cent) point Q is intersection of dc load line and the output characteristics of
IB = 30 mA. The Q-point has the values IC = 4 mA and VCC = 4.5 V.
The circuit of Fig. 3.28 is applicable in the case of ac input signal Vi. In this
circuit, the load resistance in RC is in parallel with RL. The ac load resistance is
given by:

Rac ¼ 1 kX k 470 X ¼ 320 X

The ac load line has a slope of  R1ac and passes through point Q as drawn on the
pffiffiffi
output characteristics. The ac input signal is 5 mV, i.e. 5  2  2 ¼ 14:14 mV
peak to peak. Now, consider that the input characteristics of the transistor produce a
20 mA peak-to-peak variation in the base current corresponding to the given ac
voltage input. 20–40 mA variation in the base current gives upper and lower
operating points Q1 and Q2. This gives collector current variation from 2.9 to
5.1 mA. The collector to emitter (VCE) voltage variation is between 4.1 and 4.9 V.
The current gain and voltage gain are calculated as:
Current gain,
IC max  IC min
Ai ¼ ð3:28Þ
IB max  IB min
102 3 Bipolar Junction Transistor (BJT)

Fig. 3.27 Analysis by graphical method

Fig. 3.28 CE amplifier circuit in ac condition

or
ð5:1  2:9Þ mA
Ai ¼ ¼ 110
ð40  20Þ lA
3.7 Graphical Analysis of CE Amplifier 103

and voltage gain,

VCE max  VCE min

AV ¼
Vi max  Vi min
ð3:29Þ
ð4:9  4:1Þ V
¼
14:14 mV

or

AV ¼ 56:58:

The input voltage–current is in phase, whereas collector current and collector to

emitter voltage are out of phase by 180° as shown in Fig. 3.29.

Fig. 3.29 Phase relationships between input and output voltages

104 3 Bipolar Junction Transistor (BJT)

3.8 Parameter Model

h (hybrid)-parameters are mixture of constants having different units. A transistor

is a three-terminal device which can be represented as two-port network as shown
in Fig. 3.30. The left side terminals ð1  10 Þ are input, and the right side terminals
ð2  20 Þ are output. The two-part network voltage and current relationships in terms
of h-parameter are given by the following two equations:

v1 ¼ h11 i1 þ h12 v2 ð3:30Þ

i2 ¼ h21 i1 þ h22 v2 ð3:31Þ

where


v1


h11 ¼
¼ input impedance ¼ hi
i1 v2 ¼0


i2


h21 ¼
¼ forward current ratio ¼ hf
i1 v2 ¼0


v1


h12 ¼ ¼ reverse voltage ratio ¼ hr
v2
v2 ¼0


i2


h22 ¼ ¼ output admittance ¼ ho
v2
i1 ¼0

The h-parameter model of a transistor is shown in Fig. 3.31.

3.8.1 H-Parameter Model of CE Amplifier Configuration

An additional suffix is added to the symbols of the h-parameters to indicate that the
transistor is used in the CE mode. Hence, the terminal 1 is the base terminal, terminal
2 is the collector and terminals 10 and 20 combined are the emitter. Accordingly, v1

Fig. 3.30 Two-port network

3.8 Parameter Model 105

Fig. 3.31 h-parameter model of a transistor.

and i1 become vb and ib; v2 and i2 become vc and ic. Thus, h-parameter model of the
transistor in CE mode becomes as shown in Fig. 3.32.
Then, h-parameter-based circuit equation becomes:

vb ¼ hie ib þ hre vc ð3:32Þ

ic ¼ hfe ib þ hoe vc ð3:33Þ

Figure 3.33 shows the complete h-parameter equivalent circuit of a transistor

amplifier of CE configuration. It has small signal voltage source having low fre-
quency. If the signal is small, the active region is linear; if the signal has low
frequency, the capacitive effect is negligible. Thus, in such case the h-parameters
remain constant.

Fig. 3.32 h-parameter model of CE amplifier configuration

Fig. 3.33 Complete h-parameter model of CE configuration

106 3 Bipolar Junction Transistor (BJT)

3.8.1.1 Current Gain Ai

The current gain of the circuit is given by:

iL ic
Ai ¼ ¼  as iL ¼ ic
ib ib

The voltage across the load is: vc ¼ iL RL ¼ ic RL .

By substituting vc in Eq. (3.33), we get:

ic ¼ hfe ib  hoe ic RL

or

ic ð1 þ hoe RL Þ ¼ hfe ib

or

ic hfe
¼
ib 1 þ hoe RL

∴ Current gain,

hfe
Ai ¼ 
1 þ hoe RL ð3:34Þ

3.8.1.2 Input Resistance

vc
Ri ¼
The input resistance, ib
By substituting value of vc = –ic RL in Eq. (3.32), we get:

vb ¼ hie ib þ hre ðic RL Þ

or

vb ¼ hie ib  hre ic RL

or
 
vb ic
¼ hie  hre RL
ib ib
3.8 Parameter Model 107

 
vb ic
) Ri ¼ ¼ hie  hre RL
ib ib

or

Ri ¼ hie  hre  Ai  RL

Now, by substituting value of Ai from Eq. (3.34), we get:

 
hfe
Ri ¼ hie  hre    RL
1 þ hoe RL

or
hre  hfe
Ri ¼ hie  ð3:35Þ
hoe þ R1L

3.8.1.3 Voltage Gain Av

vc ic RL
Av ¼ ¼
The voltage gain is defined as: vi vi .
As

ic
Ai ¼  or ic ¼ Ai ib
ib
 
Ai ib RL ib
) Av ¼ ¼ Ai RL ð3:36Þ
vi vb

We know that:
vb
¼ Ri
ib

Ai RL
) Av ¼
Ri

By substituting,

hfe
Ai ¼ 
1 þ hoe RL

and
108 3 Bipolar Junction Transistor (BJT)

hre  hfe hre  hfe RL

Ri ¼ hie  ¼ hie 
hoe þ R1L 1 þ hoe RL

We get

hfe 1
Av ¼  
1 þ hoe RL hoe  1hþre hhfe RRL
oe L

hfe 1 þ hoe RL ð3:37Þ

¼ 
1 þ hoe RL hie þ hie hoe RL  hre hfe RL
hfe
¼
hie þ DhRL

where

Dh ¼ hie hoe  hre hfe

3.8.1.4 Output Resistance

The output resistance can be calculated by opening load RL and making the circuit
signal as zero. Thus, the circuit of Fig. 3.33 becomes as shown in Fig. 3.34.
vc
Ro ¼
Output resistance, ic
From equation, we get:

ic ¼ hfe ib þ hoe vc
vc
) Ro ¼ ð3:38Þ
hfe ib þ hoe vc

By writing KVL for input side of the circuit, we get:

Rs ib þ hre vc þ hie ib ¼ 0

Fig. 3.34 Circuit for calculation of Ro

3.8 Parameter Model 109

or

hre vc
ib ¼  ð3:39Þ
Rs þ hie

Now, by substituting ib value from Eq. (3.39) into Eq. (3.38), we get:
vc
Ro ¼  
hre vc
hfe Rs þ hie þ hoe vc

or

Rs þ hie
Ro ¼
hoe ðRs þ hie Þ  hfe hre

or

Rs þ hie
Ro ¼
Rs hoe þ ðhie hoe  hfe hre Þ

or
Rs þ hie
Ro ¼ for Dh ¼ hie hoe  hfe hre
Rs hoe þ Dh

or
hie
Ro ¼ ð3:40Þ
Dh

for input source resistance, Rs = 0.

3.9 Hybrid Equivalent Circuit for Common Base (CB)

3.9.1 Configuration

In the h-parameter, additional subscript shall be added in Fig. 3.35 and the circuit
becomes as shown in Fig. 3.34. The h-parameter equations shall be given by:

veb ¼ hib ie þ hob vcb ð3:41Þ

ic ¼ hfb ie þ vcb hob ð3:42Þ

110 3 Bipolar Junction Transistor (BJT)

Fig. 3.35 CB circuit with h-

parameters

The current gain, input resistance, voltage gain and output resistance of the CB
circuit can be derived similar to CE circuit, or it can be obtained from CE formula
by replacing e with b in place of additional subscript.

hfb
Ai ¼  ð3:43Þ
1 þ hob RL

hrb hfb
Ri ¼ hib  ð3:44Þ
hob þ R1L

hfb RL
Av ¼  ð3:45Þ
hib þ DhRL

and

Rs þ hib
Ro ¼ ð3:46Þ
Rs hob þ Dh

where

Dh ¼ hib hob  hrb hfb

3.10 Hybrid Equivalent Circuit for Common

Collector (CC)

The hybrid equivalent circuit is shown in Fig. 3.36. In this case, the additional
subscript shall be c.
In this case, additional subscript shall be changed to c for current gain, input
resistance, voltage gain and output resistance formulae

hfc
Ai ¼  ð3:47Þ
1 þ hoc RL
3.10 Hybrid Equivalent Circuit for Common Collector (CC) 111

Fig. 3.36 CC circuit with h-

parameters

hrc hfc
Ri ¼ hic  ð3:48Þ
hoc þ R1L

hfc RL
Av ¼  ð3:49Þ
hic þ DhRL

Rs þ hic
Ro ¼ ð3:50Þ
Rs hoc þ Dh

where

Dh ¼ hic hoc and hrc hfc

3.11 Overall Current Gain

In order to calculate current including source resistance, the source voltage is

considered as source current and the circuit is shown in Fig. 3.37.
The current gain with source resistance,

iL i2 i2 i1 i1 i2
Ais ¼ ¼ ¼  ¼ Ai  as ¼ Ai
is is i1 is is i1

From the circuit (3.37), we get:

Fig. 3.37 Input circuit with

current source and source
resistance
112 3 Bipolar Junction Transistor (BJT)

Fig. 3.38 Input circuit with

voltage source and source
resistance

1
i1 ¼ ðRs k Ri Þ  is 
Ri

or
is Rs  Ri
i1 ¼ 
Ri Rs þ Ri

or
i1 Rs
¼
is Rs þ Ri
Rs
) Ais ¼ Ai  ð3:51Þ
Rs þ Ri

3.12 Overall Voltage Gain

The input part will contain source resistance, and the circuit becomes as shown in
Fig. 3.38.
The voltage gain with source resistance,
or
vb vc
Avs ¼ Av  as ¼ Av
vs vb

From the circuit (3.38), we get:

vs vb Ri
vb ¼  Ri or ¼
Rs þ Ri vs R s þ R i
Ri
) Avs ¼ Av  ð3:52Þ
Ri þ Rs
3.12 Overall Voltage Gain 113

SOLVED EXAMPLES
Example 3.1 A transistor is connected in CB configuration. When the emitter
voltage is changed by 200 mV, the emitter current changes by 5 mA. During this
variation, the collector to base voltage is kept fixed. Calculate the dynamic input
resistance of transistor.
Solution The dynamic input resistance of transistor,


DvEB


ri ¼
DiE
VCB¼constant

or
200 mV
ri ¼
5 mA

or
ri ¼ 40 X:

Example 3.2 The figure given shows the collector–base bias circuit with b = 100.
Assuming VBE = 0, determine the following:
(i) The value of IB
(ii) The value of IC
(iii) The value of VCE
(iv) The stability factor

Solution
(i) The value of base current

VCC  VBE ð10  0Þ V

IB ¼ ¼
RB þ bRC ð100 þ 100  10Þ kX
114 3 Bipolar Junction Transistor (BJT)

or
IB ¼ 0:09  104 mA:

(ii) The value of collector current

IC ¼ bIB ¼ 100  9 mA

or
IC ¼ 0:9 mA:

(iii) The value of voltage from collector to emitter

VCE ¼ VCC  IC RC

¼ 10  0:9  103  10  103 V

or

VCE ¼ 1 V:

(iv) The stability factor

1þb
S¼  
1 þ b RC RþC RB

or

1 þ 100
S¼  
1 þ 100 10 þ10100

or

101 101
S¼ ¼
1 þ 0:09 1:09

or

S ¼ 92:6:
3.12 Overall Voltage Gain 115

Example 3.3 A transistor with b = 100 is used in CE configuration. The collector

circuit resistance is RC ¼ 1 kX and VCC = 20 V. Assuming VBE = 0, find the value
of collector to base resistance, such that quiescent collector–emitter voltage is 4 V.
Also, determine the stability factor in this case.
Solution Consider the figure shown:

IC0 ¼ IC þ IB

or

IC0 ’ IC as IB  IC

From the figure, we get:

VCC ¼ IC RC þ VCE

or

20 ¼ IC  1  103 þ 4 V

or

IC ¼ 16 mA

We know that: IC ¼ bIB

IC 16  103
) IB ¼ ¼ ¼ 160 mA
b 100
116 3 Bipolar Junction Transistor (BJT)

From figure, it is seen:

VCE ¼ IB RB þ VBE

or

VCE ¼ IB RB þ 0

or

VCE 4
RB ¼ ¼
IB 160  106

or

RB ¼ 25 kX:

The stability factor,

bþ1 100 þ 1 101

S¼ bRC
¼ ¼
1þ RB þ RC
1 þ 1001
25 þ 1 1 þ 100
26

or

101
S¼ ¼ 20:86:
4:84

Example 3.4 In common-emitter circuit as given below, an NPN transistor having

a value of b = 50 is used with VCC = 10 V and R ¼ 2 kX. If a 100 kX resistor is
connected between collector and base and VBE = 0, determine:
(i) The position of quiescent point and
(ii) Stability factor, S
Solution
(i) Consider the figure shown:

IC0 ¼ IC þ IB

or

IC0 ’ IC as IB  IC
3.12 Overall Voltage Gain 117

KVL from VCC, collector, RB, base, emitter and ground gives:

VCC ¼ IC0 RC þ IB RB þ VBE

or
IC
VCC ¼ IC  RC þ  RB þ 0 as IC0 ’ IC and IC ¼ bIB
b

or


RB
VCC ¼ IC R C þ
b

or
VCC 10 V
IC ¼ RB ¼

RC þ b 2 þ 100
50 kX

or

IC ¼ 2:5 mA

We know:
IC ¼ bIB

IC 2:5 mA
) IB ¼ ¼ ¼ 0:05 mA
b 50

We can see that:

VCE ¼ IB RB þ VBE
118 3 Bipolar Junction Transistor (BJT)

or

VCE ¼ 0:05  103  100  103 þ 0

or

VCE ¼ 5 V

∴ Point, Q ¼ ð5 V; 2:5 mAÞ:

The stability factor,

bþ1
S¼ bRC
1þ RB þ RC

or

50 þ 1 51  102
S¼ ¼
1 þ 100
5020
þ 20
102 þ 100

or

S ¼ 25:75:

Example 3.5 In a NPN transistor amplifier stage, a 9 V battery, supply is to be

used with collector to base biasing. Determine the values of RB and RC if ICBO is
negligible, b = 100, and if the quiescent point is specified by IC = 0.2 A and VCE =
5 V.
Solution Consider the circuit given in the figure.
3.12 Overall Voltage Gain 119

From the figure, we get:

VCC ¼ IC0 RC þ VCE

or

VCC ¼ ðIC þ IB ÞRC þ VCC

or

VCC ¼ IC RC þ VCE as IB  IC

) IC RC ¼ VCC  VCE ¼ 9  5 ¼ 4 V

as

VCC ¼ 9 V and VCE ¼ 5 V

4 4
) RC ¼ ¼ ¼ 20 X:
IC 0:2

It is known that:

IC ¼ bIB

or

IC 0:2
IB ¼ ¼ ¼ 2 mA
b 100

From the figure, we get:

0
VCE ¼ IB RB þ VBE

or
5 V ¼ 2 mA  RB taking VBE ¼ 0

or
5V
RB ¼ ¼ 2:5 kX:
2 mA

Example 3.6 In the given figure, a transistor with b = 45 is used with collector to
base resistor (R) biasing, with a quiescent value of 5 V for VCE. If VCC = 24 V,
RL = 10 kW and RE = 270 W, find the value of (i) R and (ii) stability factor.
120 3 Bipolar Junction Transistor (BJT)

Solution Consider circuit of the figure given here.

(i) By KVL in collector and emitter circuit, we get:

VCC ¼ IC0 RL þ VCE þ IE RE

or

VCC ¼ ðIC þ IB ÞRL þ VCE þ ðIB þ IC ÞRE

as

IC0 ¼ IC þ IB and IE ¼ IB þ IC

or

VCC ¼ ðbIB þ IB ÞRL þ VCE þ ðbIB þ IB ÞRE

or

VCC ¼ ðbIB þ IB ÞðRL þ RE Þ þ VCE

or

24 V ¼ ð45 þ 1Þ  IB  ð10 kX þ 0:2070 kXÞ þ 5 V

3.12 Overall Voltage Gain 121

or
19V
IB ¼
46  ð10 þ 0:27Þ  103 X

or
19
IB ¼ mA
46  10:27

or

IB ¼ 40 mA

We can see from the circuit of the figure that:

VCE ¼ VBE þ RIB

or
VCE  VBE 5  0:6
R¼ ¼ X
IB 40  106

where

VBE ¼ 0:6 is taken:

or

R ¼ 110 kX:

(ii) Stability factor

bþ1
S¼ bRE
1þ RE þ R
45 þ 1
¼
1þ 45270
270 þ 110103
46
¼  12150
1 þ 110:27010 3

46 46
¼ ¼
1 þ 0:11 1:11

or

S ¼ 41:44:
122 3 Bipolar Junction Transistor (BJT)

Example 3.7 In a CE germanium transistor amplifier, self-bias is used. The var-

ious parameters are: VCC = 16 V, RC ¼ 3 kX, RE ¼ 2 kX, R1 ¼ 56 kX, R2 ¼ 20 kX
and a ¼ 0:985. Determine the following:
(i) Operating point
(ii) The stability factor, S
Solution Consider the circuit of the figure being given here.

a 0:985
b¼ ¼ as a ¼ 0:985:
1  a 1  0:985

(i) Or b = 66 from the circuit

VCC  R2 16  20  103
VB ¼ ¼ ¼ 4:21 V:
R1 þ R2 ð56 þ 20Þ  103

VB  VBE
IC ¼
RE

or
ð4:21  0:3ÞV
IC ¼ as VBE ¼ 0 for germanium transistor
2  103 X

By application of KVL in the collector–emitter loop, we get:

3.12 Overall Voltage Gain 123

VCE ¼ VCC  IC ðRC þ RE Þ

¼ 16 V  2:0  103 ð3 þ 2Þ  103 ¼ 6 V

Thus, operating point, Q = (6 V, 2 mA).

(ii) Stability factor
 
1þb 1þ RTH
RE
S¼
1þbþ RTH
RE

where
R1  R2 56  103  20  103
RTH ¼ R1 k R2 ¼ ¼ ¼ 14:73 kX:
R1 þ R2 ð56 þ 20Þ  103

1 þ 66 1 þ 14:73
) S¼ 2
1 þ 66 þ 14:73
2

or
S ¼ 7:5:

Example 3.8 Calculate the collector current and collector to emitter voltage of the
circuit figure assuming the following circuit components and transistor specifications.

R1 ¼ 40 kX; R2 ¼ 4 kX; RC ¼ 10 kX; RE ¼ 1:5 kX

VBE ¼ 0:5 V; B ¼ 40; VCC ¼ 22 V:
124 3 Bipolar Junction Transistor (BJT)

Solution For given self-bias circuit, the value of collector current IC is given by

VB  VBE
IC ¼ ð3:1Þ
RE

But base voltage

R2
VB ¼ VCC 
R1 þ R2
4  103
VB ¼ 22 
ð40 þ 4Þ  103
22  4
¼ ¼2V
44

Using equation (i)

VB  VBE
IC ¼
RBE
2  0:5 1:5
¼ ¼ ¼ 1 mA
1:5  10 3 1:5  103
IC ¼ 1 mA:

Now, collector to emitter voltage

VCE ¼ VCC  IC ðRC þ RE Þ

¼ 22  1  103 ð10 þ 1:5Þ  103
VCE ¼ 22  11:5 ¼ 8:5V
IC ¼ 1 mA
VCE ¼ 8:5 V:

Example 3.9 In a single state CE amplifier, VCC = 20 V, b = 50, RE = 200 W, R1

= 60 kW and R2 = 30 kW. Determine the dc voltage across RE.
Solution The base voltage VB (the voltage at base w.r.t. ground) is
3.12 Overall Voltage Gain 125

VCC  R2
VB ¼ ½* VB is the voltage across R2 
R1 þ R2
30  103
¼ 20 
ð60 þ 30Þ  103
20  30
¼
90
20
VB ¼ ¼ 6:67 V:
3

The voltage across the emitter resistor RE is given by

VE ¼ VB  VBE

Taking

VBE ffi 0:6 V

VE ¼ 7:66  0:6
VE ¼ 7:07 V:

Example 3.10 A silicon transistor with VBE = 0.8, hFE = 100, VCE sat = 0.2 V is
used in the circuit shown in the given figure. Find the minimum value of RC for
which the transistor reaches its saturation.
126 3 Bipolar Junction Transistor (BJT)

Solution Base current IB is given by

5V 5
IB ¼ ¼
200 kX 200  103
5
IB ¼  105 ¼ 25 mA
2

Collector current

IC ¼ bIB ¼ 100  25  106

¼ 25  104 ¼ 2:5

From the figure,

VCC ¼ VCE þ IC RC
10 ¼ 0:2 þ 2:5  103  RCðminÞ
9:8 ¼ 2:5  103  RCðminÞ
9:8
RCðminÞ ¼ kX ¼ 3:92 kX:
2:5

Example 3.11 For the circuit shown in given figure, assume hFE = 100 and
VBE = 0.8 V.
(a) Find if the silicon transistor is in cut-off, saturation or active region.
(b) Find VC.
(c) Find the minimum value of the emitter resistance for which the transistor
operates in active region.
3.12 Overall Voltage Gain 127

Solution RC drawing the given circuit.

Applying KVL to the input loop

7  103 IB þ 0:8 þ 500ðIB þ Ic Þ ¼ 3

or

7500IB þ 500IC ¼ 2:2 ðiÞ

Applying KVL to the output loop

3  103 IC þ VCE þ 500ðIB þ IC Þ ¼ 10

Taking limiting value of VCE = 0.2 for saturation as in last question

3000IC þ 0:2 þ 500IB þ 500IC ¼ 10

or

500IB þ 3500IC ¼ 9:8 ðiiÞ

Solving (i) and (ii), we have

IC ¼ 2:78 mA; IB ¼ 0:1 mA

For saturation,
128 3 Bipolar Junction Transistor (BJT)

IC 2:78 mA
IBðminÞ ¼ ¼
hFE 100
IBðminÞ ¼ 0:0278 mA:

But, IB = 0.1 mA, which is greater than 0.0278 mA.

IB ¼ 0:1 mA [ IBðminÞ ¼ 0:0278 mA:

Therefore, the transistor is in saturation region.

(b) Since transistor is in saturation,

VC ¼ VBE ¼ 0:8 V

From circuit,

VCE ¼ VC  VE
¼ VC  500ðIC þ IB Þ

¼ 0:8  500 2:78  103 þ 0:1  103
VCE ¼ 0:8  500  2:88  103
¼ 0:64 V:

Again from circuit,

VCE ¼ VCC  IC ðRC þ RE Þ


0:64 ¼ 10  2:78  103 3  103 þ RE

Solving above equation, we get

RE ¼ 827 X:

Example 3.12 A CE amplifier employing an NPN transistor has load resistor RC

connected between collector and VCC supply of +16 V. For biasing, a resistor R1 is
connected between collector and base, resistor R2 ¼ 30 kX is connected between
base and ground and resistor RE ¼ 1 kX is connected between emitter and ground.
Draw the circuit diagram. Calculate the values of R1 and RC and the stability factor
S if VBE ¼ 0:2 V; IE ¼ 2 mA; a0 ¼ 0:985 and VCE ¼ 6 V.
Solution Given that emitter current IE = 2 mA.
3.12 Overall Voltage Gain 129

Collector current,

IC ¼ a0 IE
IC ¼ 0:985  2 ¼ 1:97 mA:

Also, base current,

IB ¼ IE  IC
¼ 2  1:97 ¼ 0:03 mA

We know that
a
b¼
1a

Therefore,
0:985
b¼ ¼ 65:6677
1  0:985

Collector resistance,

VCC  VCE  IE RE
RC ¼
IC
16  6  2 mA  1 kX
RC ¼ ¼ 4:06 kX:
1:97 mA
130 3 Bipolar Junction Transistor (BJT)

or voltage drop across resistor R2

VCC  R2 30  16 480
Vth ¼ ¼ ¼ ðiÞ
R1 þ R2 30 þ R1 30 þ R1

Again, we know that

R1  R2 30R1
Rth ¼ ¼
R1 þ R2 30 þ R1

and

Vth ¼ IB Rth þ VBE þ IE RE

or
480 30R1
¼ 0:03  þ 0:2 þ 2 mA  1 kX
30 þ R1 30 þ R1

or

480 ¼ 0:9R1 þ 2:2ð20 þ R1 Þ

Solving, we get R1 ¼ 133:55 kX:.

For voltage divider biasing, stability factor S is expressed as:
Stability factor,

1þb
S¼ bRE
1þ RTH þ RE

Substituting all the values, we get

1 þ 65:667
S¼ ¼ 18:65:
1 þ 65:667 133:55 
1
30
þ1
133:55 þ 30

Example 3.13 Assume that a silicon transistor with b0 = 50, VBE = 0.6 V and
VCC = 20 V and RC ¼ 4:7 kX is used in a self-bias circuit. It is designed to
establish a Q pt at VCE = 8 V and IC = 2 mA and stability factor S
5.0. Design
the circuit with all component values.
Solution Given that:
Collector current,
IC ¼ 2 mA
3.12 Overall Voltage Gain 131

and

b0 ¼ 50

Base current,
IC 2
IB ¼ ¼
b0 50
IB ¼ 0:04 mA

Emitter current is given as

IE ¼ IB þ IC ¼ 0:04 þ 2 ¼ 2:04 mA
VCE ¼ 8 V
VBE ¼ 0:6V; VCC ¼ 20 V

We know that for a self-biased circuit:

Emitter resistance
VCC  VCE
RE ¼  RC
IC

Substituting all the values, we get

20  8
RE ¼  4:7 ¼ 1:3 kX
2 mA

Also, stability factor for self-bias circuit is given as

1þ RTH
RE
S ¼ ðb þ 1Þ
1 þ b þ RRTHE

Substituting all the values, we get

1 þ R1:3
TH

S ¼ ð1 þ 50Þ
1 þ 50 þ R1:3
TH

Solving, we get

RTH ¼ 5:765 kX

Also,

VTH ¼ IB RTH þ VBE þ IE RE

132 3 Bipolar Junction Transistor (BJT)

or

VTH ¼ 0:04  5:765 þ 0:6 þ 2:04  1:3

¼ 3:486 V

Again,

VCC  R2 VCC  RTH

VTH ¼ ¼
R1 þ R2 R1

or

VCC
R1 ¼ RTH 
VTH

Substituting given values, we get

20
R1 ¼ 5:765  ¼ 331:3 kX:
3:4826

Now since

VCC  R2
VTH ¼
R1 þ R2

Therefore,

VTH  R1 3:4826  33:1

R2 ¼ ¼
VCC  VTH 20  3:4826
¼ 7:98 kX:

Example 3.14 The given figure shows a self-biased transistor amplifier using a Si
transistor with VCC = 20 V, hFE = 400 and VBE = 0.65 V. The transistor should be
biased at VCE = 10 V and IC = 0.6 mA. Find the value of RC ; RE , R1 and R2 such
that it meets the following specification over the temperature range 25–145 °C.

DIC

10 ; VBE at 25  C ¼ 650  50 mA,
DIC

ICO at 25  C ¼ 5 nA max; Ico at 145 ¼ 3:0 mA max

Assume that percentage change in IC due to VBE and ICO is same (5%).
Solution Change in IC due to VBE and ICO is 5%.
3.12 Overall Voltage Gain 133

Change in collector current

5
DIC ¼  0:6 ¼ 0:03 mA
100

Change in reverse saturation current

DICO ¼ 3  106  0:005  106 ¼ 2:995 mA

Stability factor,

DIC
S¼
DICO

or

0:03  103
S¼ ¼ 10
2:995  106

For a Si transistor, VBE decreases at the rate of –2.5 mV/°C.

Therefore,

2:5ð145  25Þ
DVBE ¼
300 mV

Now,
DIC
SV ¼
DVBE

or
134 3 Bipolar Junction Transistor (BJT)

0:03  103
SV ¼ ¼ 0:0001
300  103
b ¼ hFE ¼ 400

and
S b
SV ¼ 
RTH þ RE b þ 1

or

10 400
0:0001 ¼ 
RTH þ RE 401

or

RTH þ RE ¼ 99; 750:6

Again,

RE þ RTH
S¼
RE þ bRþTH1

or

RE þ RTH
10 ¼
RE þ bRþTH1

391
RE ¼ RTH
3609

Solving equations (i) and (ii), we get

RE ¼ 9:75 kX:

and

RTH ¼ 90 kX
DIC ¼ SICO þ SV DVBE ¼ 0:03  103 þ 0:03  103 ¼ 0:06 mA

For the given circuit, we have

3.12 Overall Voltage Gain 135

VCC ¼ IC RC þ VCE þ IE RE


0:66
20 ¼ 0:66RC þ 10 þ 0:66 þ  9:75
400

or

RC ¼ 5:377 kX:

Now,

VTH ¼ IB RTH þ VBE þ IE RE

Substituting all the values, we get


0:66 0:66
VTH ¼  90 þ 0:65 þ 0:66 þ  9:75 ¼ 7:25 V
400 400

Now since

VCC 20
R1 ¼ RTH ¼ 90  ¼ 248 kX:
VTH 7:25

Also,

VTH  R1
R2 ¼
VCC  VTH

Substituting values, we get

7:25  2:48
R2 ¼ ¼ 141 kX:
20  7:25

As R1, R2, RC and REare designed for variation up to 145 °C, the variation of
VBE at 25°C of 650±50 mV will be absorbed in the overall variation.
Example 3.15 Find IC and VCE for the following circuit. What will happen to VCE
if b increases due to temperature?
Solution Applying KVL to the base–emitter loop:
136 3 Bipolar Junction Transistor (BJT)

VCC ¼ ðIC þ IB ÞRC þ IB  RB þ VBE þ IE RE

VCC ¼ IC RC þ IB RB þ VBE þ IE RE

* ðIC  IB Þ

But IE ffi IC and neglecting VBE,

we have

VCC ¼ IC RC þ IB RB þ 0 þ IC RE
¼ IC ðRC þ RE Þ þ IB RB

But

IC ¼ bIB

Therefore,
VCC ¼ bIB ðRC þ RE Þ þ IB RB
¼ IB ½bðRC þ RE Þ þ RB 

VCE 18
IB ¼ ¼
RB þ bðRC þ RE Þ 510  103 þ 90ð2:2 þ 1:8Þ103
18  103
¼ ¼ 0:02  103
870

IB ¼ 20  106 A ¼ 20 mA
3.12 Overall Voltage Gain 137

) IC ¼ bIB ¼ 90  20  106

Hence,

IC ¼ 1800  106 ¼ 1:8  103 ¼ 1:8 mA

Now,

VCE ¼ IB RB þ VBE

Taking

VBE ffi 0
VCE ffi IB RB ¼ 20  106  510  103 ¼ 20  510  103 ¼ 102  102
VCE ¼ 10:2 V:

Example 3.16 A transistor has an emitter current of 10 mA and a collector current

of 9.95 mA. Calculate its base current.
Solution Given that

IE ¼ 10 mA

and

IC ¼ 9:95 mA

Emitter current is given by

IE ¼ IC þ IB
IB ¼ IE  IC ¼ 10  9:95 ¼ 0:05 mA:
IB ¼ 0:05 mA

Example 3.17 Draw N-P-N and P-N-P transistors. Label all the currents and show
the direction of flow. How are all the currents of a transistor related?
Solution N-P-N transistor symbol and common-emitter circuit.
138 3 Bipolar Junction Transistor (BJT)

P-N-P transistor and common-emitter circuit.

The currents of a transistor are related by the following relation:

IE ¼ IB þ IC

where
IE emitter current
IC collector current
IB base current

Example 3.18 Find the value of b, VCC and RB in the circuit shown below.
3.12 Overall Voltage Gain 139

Solution Given that:

IB ¼ 20 mA ¼ 0:02 mA
RC ¼ 2:7 kX
VCE ¼ 7:3 V; VE ¼ 2:1 V
RE ¼ 0:68 kX
VBE ¼ 0:7 V (assumed)

From the figure, we have

IE RE ¼ VE

or
VE
IE ¼
RE

Substituting values, we get

2:1
IE ¼ ¼ 3:09 mA
0:68

Also, since
IE ¼ IC þ IB
140 3 Bipolar Junction Transistor (BJT)

Therefore,

IC ¼ IE  IB ¼ 3:09  0:02

or

IC ¼ 3:07 mA

Further,

IC 3:07
IC ¼ bIB so that b ¼ ¼ ;
IB 0:02
b ¼ 154:

Applying KVL to the output side of the given circuit,

we get

VCC ¼ IC RC þ VCE þ VE

Substituting values, we get

VCC ¼ 3:07  2:7 þ 7:3 þ 2:1

¼ 1:77 V

Also applying KVL to the input side, we obtain

VCC ¼ IB RB þ VBE þ VE

or

VCC  VBE  VE
RB ¼
IB

Putting values, we get

17:7  0:7  2:1

RB ¼
0:02  103
RB ¼ 745 kX:

Example 3.19 Consider a dc bias circuit with voltage feedback as in the given
figure. Determine the quiescent levels of ICQ and VCEQ. The b of the transistor is
1590, and cut in voltage is 0.7 V.
3.12 Overall Voltage Gain 141

Solution

Now, applying KVL to the input side, we get

VCC ¼ ðIC þ IB ÞRC þ IB RB þ VBE þ IE RE

or

VCC ¼ ðIC þ IB ÞRC þ IB RB þ VBE þ ðIC þ IB ÞRE

VCC ¼ ðIC þ IB ÞðRC þ RB Þ þ IB RB þ VBE

But
IC
IB ¼
b

Therefore, we have


IC IC
VCC ¼ IC þ ðRC þ RB Þ þ  RC þ VBE
b b

or
 
IC IC
VCC ¼ ðRC þ RE Þ þ  RB þ VBE
b b
142 3 Bipolar Junction Transistor (BJT)

The dc equivalent circuit for the given circuit.

Or

  
1 RB
VCC  VBE ¼ IC 1þ ðRC þ RE Þ þ
b b

Then, we have

bðVCC  VBE Þ
ICQ ¼
ð1 þ bÞðRC þ RE Þ þ RB

Given
b ¼ 90 ; VCC ¼ 10 V; VBE ¼ 0:7 V
RC ¼ 4:7 K ¼ 4700 ohm; RB ¼ 250 K ¼ 25;000 ohm

Substituting all these values in Eq. (i), we get

90ð10  0:7Þ
ICQ ¼
ð1 þ 90Þð4700 þ 100Þ þ 25;000
90  9:3
ICQ ¼ ¼ 1:06 mA:
91  5900 þ 25;000

Further, applying KVL to the output side, we get

IC
VCEQ ¼ VCC  IC þ ðRC þ RE Þ
b
3.12 Overall Voltage Gain 143

Again, substituting given values, we obtain

VCEQ ¼ 3:68 V:

Example 3.21 For the emitter bias circuit shown in the given figure, determine
IB ; IC ; VCE ; VC ; VB and VC :
Solution Note that the dc equivalent circuit is obtained by making the capacitors
open circuited.
Applying KVL to the input side, we get

The dc equivalent circuit for the given circuit.

VCC ¼ IB RB þ VBE þ IE RE ðiÞ

IE ¼ IB þ IC and IC ¼ bIB

With above two substitutions, Eq. (i) becomes

VCC ¼ IB RB þ VBE þ ðIB þ bIB ÞRE

Simplifying, we get
VCC  VBE
IB ¼
RB þ ðb þ 1ÞRE

VBE ffi 0:7 V for Si transistor

Substituting all the given values, we obtain

144 3 Bipolar Junction Transistor (BJT)

20  0:7
IB ¼
430  103 þ ð50 þ 1Þ  1  103

or

IB ¼ 4  105 amp:

Also,
IC ¼ bIB ¼ 50  4  105
IC ¼ 2 mA:

Now, applying KVL to the output side, we get

VCC ¼ IC RC þ VCE þ IE RE

or

VCC ¼ IC RC þ VCE þ ðIC þ IB ÞRE

or

VCE ¼ VCC  IC RC  ðIC þ IB ÞRE

or

VCE ¼ 20  2  103  2  103  2  103 þ 4  106  1  103 :

Solving, we get

VCE ¼ 13:96 V:

* VE ¼ IE RE

or

VE ¼ ðIC þ IB ÞRE ¼ 2  103 þ 40  106  1  103

or
VE ¼ 2:04 V:

Again,

VB ¼ VCC  IB RB ¼ 20  40  106  430  103

3.12 Overall Voltage Gain 145

or

VB ¼ 2:8 V:

* VC ¼ VCE þ VE ¼ 13:96 þ 2:04

VC ¼ 16 V:

Example 3.22 In the given circuit shown hFE = 100, VBE ¼ 0:8 V; VCE ¼ 0:2 V.
Determine whether or not the Si transistor is in saturation and find IB and IC.
Solution As VCE = 0.2 V for the Si transistor which is in saturation state,
applying KVL to the input side, we have

5 ¼ 5  103 IB þ VBE þ ðIC þ IB Þ  2  103 ðiÞ

But

IC ¼ bIB

or

IC ¼ hFE  IB

or

IC ¼ 100IB ðiiÞ
146 3 Bipolar Junction Transistor (BJT)

Using Eqs. (i) and (ii), we get

5  0:8
IB ¼
5000 þ 101  2  103

or

IB ¼ 16:67 mA:

Also,

IC ¼ 100IB

IC ¼ 100  16:67  106

¼ 1:67 mA:

Now applying KVL to the output side, we get

10 ¼ IC  3000 þ VCE þ ðIC þ IB Þ  2  103

or

VCE ¼ 10  3000  1:67  103  1:67  103 þ 16:67  106  2  103

Solving, we get

VCE ¼ 1:617 V:

Thus, in the given circuit, we have

VCE ¼ 1:617 V [ 0:2 V:

Therefore, the transistor is not working in saturation region; rather, it is inactive

region.
Example 3.23 An Si transistor with (VBE)sat = 0.8 V, b = hFE = 100, (VCE)sat =
0.2 V is used in the circuit shown in the given figure. Find the minimum value of
RC for which the transistor remains in saturation.
Solution Using KVL in base circuit for saturation, we have
3.12 Overall Voltage Gain 147

VBB ¼ ðIB Þsat RB þ ðVBE Þsat

5 ¼ ðIB Þsat 200  103 þ 0:8
5  0:8
ðIB Þsat ¼
200  103
4:2
¼ ¼ 21  106 amp
200  103

Now, we have

ðIC Þsat ¼ bðIB Þsat

¼ 100  21  106 ¼ 2:1 Amp:

Again, using KVL in collector circuit, we get

VCC ¼ ðIC Þsat RC þ ðVCE Þsat

10 ¼ 2:1  103  RC þ 0:2

Simplifying, we get

10  0:2 9:8  103

RC ¼ ¼ ¼ 4666 ohms:
2:1  103 2:1

Example 3.24 A transistor with b = 100 is used in CE configuration. The collector

circuit resistance is RC ¼ 1 kX and VCC = 20 V. Assuming VBE = 0, find the value
of collector to base resistance, such that quiescent collector–emitter voltage is 4 V.
Solution From the figure, it may be observed that
148 3 Bipolar Junction Transistor (BJT)

IC0 ¼ IC þ IB

* IC  IB

Therefore,

IC0 ¼ IC

Again from the figure, we have

VCC ¼ IC RC þ VCE

Substituting values, we shall have

20 ¼ IC  1  103 þ 4

or

16 ¼ IC  103

or

IC ¼ 16 mA

We know that

IC ¼ bIB

or
3.12 Overall Voltage Gain 149

IC 16  103
IB ¼ ¼ ¼ 160 mA
b 100

From the figure,

VCE ¼ IB RB þ VBE
VCE ¼ IB RB þ 0
VCE 4 4
RB ¼ ¼ ¼
IB 160  10 6 16  105
1
RB ¼  105 ¼ 0:25  105
4
RB ¼ 25  103
RB ¼ 25 kX:

Example 3.25 Find IC and VCE for the following circuit. What will happen to VCE
if b increases due to temperature?
Solution Applying KVL to the input side, we get

VCC ¼ IC RC þ IB RB þ VBE þ IE RE

Substituting values, we get

18 ¼ 2:23  103 IC þ 510  103 IB þ 0 þ 1:8  103 IE

or
150 3 Bipolar Junction Transistor (BJT)

18
¼ 4IE þ 510IB þ 0 ðiÞ
1000
) IE ffi IC and VBE ¼ 0 (assuming)

18
¼ 4ðIC þ IB Þ þ 510 IB
1000

But,

IC
b¼ ¼ 90 or IC ¼ 90IB ðiiÞ
IB

Substituting the value of IC in Eq. (i), we have

18
¼ 4  90IB þ 514IB
1000
18
IB ¼ ¼ 20:595 lA
1000  874

Now, value of IC will be (using Eq. ii)

IC ¼ 90  20:95 m Amp
IC ¼ 1:85  103 m amp ¼ 1:85 mA:

Again applying KVL to the output side, we get

VCC ¼ 18 ¼ 2:2  103 IE þ VCE þ 1:8IE

18 ¼ 4  103 IE þ VCE

or

18  4  103 1:85  103 þ 20:595  106 ¼ VCE

or

18  7:4824 ¼ VCE

or

VCE ¼ 10:52 V:

If B increases due to temperature, then VCE will decrease.

Example 3.26 If IC = 5 mA and IB = 0.02 mA, what is current gain?
3.12 Overall Voltage Gain 151

Solution Given

IC ¼ 5 mA

and

IB ¼ 0:02 mA

Current gain

IC 5  103
b¼ ¼
IB 0:02  103
b ¼ 250:

Example 3.27 Draw the load line for the following figure. What is IC at saturation
point? Find VCE at cut-off point.
Solution We know that

VCC ¼ IC RC þ VCE

or

1 VCC
IC ¼  VCE þ
RC RC

It cuts the X-axis on output characteristic at

VCE ¼ VCC fVCE at cut - off g

VCE ¼ 20 V
152 3 Bipolar Junction Transistor (BJT)

It cuts the Y-axis on output characteristic

VCC 20
IC ¼ ¼
RC 3:3 k
IC ¼ 6:06 mA:
 
Load line can be drawn by joining two points having coordinates 0; VRCCC and
ðVCC ; 0Þ; i.e:ð0; 6:06 mAÞ and ð20 V; 0Þ.
Here, we can plot load line as shown in below figure and slope of load line is

1
¼
RC
1
¼ ¼ 0:3:
3:3

Here, the coordinates at Y-axis and X-axis represent the saturation of IC and
cut-off of VC, respectively.
Example 3.28 Find VCE and IE in the given figure.
Solution This is potential divider biasing of transistors, so first let us calculate the
RTH and VTH input circuit, where
3.12 Overall Voltage Gain 153

R1  R2 VCC  R2
RTH ¼ and VTH ¼
R1 þ R2 R1 þ R2

Now,

10  2:2
RTH ¼ ¼ 1:8 kX
12:2

and

10  2:2
VTH ¼ ¼ 1:8 V
12:2

Applying KVL to input side, we get

VTH ¼ IB RTH þ VBE þ IE RE

We know that

IE ¼ ðb þ 1ÞIB

IE
VTH ¼ RTH þ VBE þ IE RE
bH
154 3 Bipolar Junction Transistor (BJT)

or
VTH  VBE
IE ¼
RE þ bRþTH1

Here, VTH ¼ 1:8 V; VBE ¼ 0:7 V; RE ¼ 1 kX; RTH ¼ 1:8 kX; b ¼ 100:
Therefore, we have
So,
18  0:7
IE ¼ ¼ 1:081 mA
1000 þ 1800
101

Now,

IC ¼ bIB ¼ 100  10:7 mA ¼ 107 mA:

Further, KVL in output loop will yield

VCC ¼ IC RC  VCE þ IE RE

or

VCE ¼ VCC  IC RC  IE RE

or
VCE ¼ 10  1:07  103  3:6  103  1:081  103
VCE ¼ 5:067 V:

Example 3.29 Determine VC and IB for the following network in the given figure.
3.12 Overall Voltage Gain 155

Solution Here,

VCC  R2 16 kX
VTH ¼ ¼  ð þ 22Þ
R1 þ R2 82 kX þ 16 kX

or

VTH ¼ þ 3:59 V:

and
R1  R2 16  82
RTH ¼ ¼ ðkXÞ
R1 þ R2 16 þ 32
¼ 13:39 kX:

Kirchoff’s law in input loop will yield

VTH ¼ IE RE þ VBE þ IB RTH

We know that

IE ¼ ðb þ 1ÞIB

and VBE for Si transistor

¼ 0:7 V

So,
VTH ¼ ðb þ 1ÞIB RE þ VBE þ IB RTH
156 3 Bipolar Junction Transistor (BJT)

Thevenin's equivalent circuit

or

VTH  VBE
IB ¼ :
RTH þ ðb þ 1ÞRE

Here,

VTH ¼ þ 3:59 V; RTH ¼ 13:39 k

RE ¼ 750 X
b ¼ 200
VEB ¼ 0:7 V

So,

3:59  0:7
IB ¼
13:39  103 þ ð200 þ 1Þ750

or,

IB ¼ 17:61 lAðin the shown direction)

We know that

IC ¼ IB ¼ 200  17:61  106 ¼ 3:52 mA: ðin the shown direction)

KVL in the output loop will yield

VCC ¼ IC RC þ VC
3.12 Overall Voltage Gain 157

So,

VC ¼ VCC þ IC RC

Here,

VCC ¼ 22 V; RC ¼ 2:2 K; IC ¼ 3:52 mA

So,

VC ¼ 22 þ 3:52  103  2:2  103

¼ 14:256 V:

Example 3.30 For the emitter follower with Rs ¼ 0:5 kX and RL ¼ 5 kX, calcu-
late AI ; Ri ; AV . Assume hfe ¼ 50 kX; hie ¼ 1 kX; hoe ¼ 25 microamp/volt.
Solution For emitter follower,
(i) The current gain

1 þ hfe 1 þ 50
AI ¼ ¼
1 þ hoe  RL 1 þ 25  106  5  103
51
AI ¼ ¼ 45:33:
1:125

(ii) Input resistance

Ri ¼ hie þ hre AI  RL
Ri ¼ hie þ 1  AI  RL
Ri ¼ hie þ A1  RL

Putting all the values,

Ri ¼ 1  103 þ 45:33  5  103

Ri ¼ ð1 þ 226:6Þ103 ¼ 227:6 kX:

Vo Al  RL
AV ¼ ¼
Vi Ri
ðiiiÞ
45:33  5 226:6
¼ ¼ ¼ 0:9958:
227:6 227:6
158 3 Bipolar Junction Transistor (BJT)

Example 3.31 Find the values of voltage gain, current gain, input resistance and
power gain for a common-emitter transistor amplifier with RL = 1600 Ω and Rs ¼
1 kX. The transistor has hie ¼ 1100 X, hfe ¼ 2:5  104 , hoe ¼ 25 microamp/V.
Solution For common-emitter transistor amplifier,
(i) Current gain

hfe 2:5  104

AI ¼  ¼
1 þ hoe  RL 1 þ 25  106  1600
4
2:5  10
AI ¼  ¼ 2:4  104 :
1:04

(ii) Input resistance

Ri ¼ hie þ hre  AI  RL
ffi hie (neglecting the factor hre  AI  RL Þ
Ri ffi 1100 ohm:Ans:

(iii) Voltage gain

RL 2:4  104  1600

AV ¼ AI  ¼
Ri 1100
38:4  104
AV ¼  ¼ 3:49  104 :
11

(iv) Power gain

¼ AI  AV
 
¼ 2:4  104  3:49  104
¼ 8:37  108 :

Example 3.32 In the following circuit given, bdc ¼ hFE ¼ 130.

(a) Find ICQ and VCEQ.
(b) Find AV and Rin for the circuit of part (a) if hfe ¼ 50; hie ¼ 1 kW; hre ¼ 0 and
hoe ¼ 0.
Solution
(a) ∵ Base voltage
3.12 Overall Voltage Gain 159

R2
VB ¼ VCC 
R1 þ R2
8  510
VB ¼
510 þ 510
18
VB ¼ ¼ 9V
2

Value of IC is given by

VB  VBE VB  0
IC ¼ ¼ (neglecting VBE Þ
RE RE
VB
IC ¼
RE
9 9  103
¼ ¼
7:5  10 3 7:5
IC ¼ 1:2 mA

or
ICQ ¼ 1:2 mA:

Now,
VCE ¼ VCC  IC ðRC þ RE Þ
¼ 18  1:2  103 ð9:1 þ 8:5Þ  103
VCE ¼ 18  1:2  16:6 ¼ 18  19:9
VCE ¼ 1:9 V or VCEQ ¼ 1:9 V:
160 3 Bipolar Junction Transistor (BJT)

(b) Input resistance

Ri ffi hie ffi 1 kX:

Input resistance of amplifier stage

Rin ¼ Ri k ðR1 k R2 Þ ¼k ð510 k 510Þ

Rin ¼k 255 ¼ 0:99 kX:

Current gain
AI ffi hfe ¼ 50

Voltage gain
AI  RL AI  RC 50  9:1
AV ¼ ¼ ¼
Ri Ri 1
¼ 455:

Example 3.33 Given that hfe ¼ 50; hie ¼ 0:83 kX. Find out the current gain (hfb)
and input impedance (hib) for a transistor in CB configuration.
Solution We know that

hfe
hfb ¼ ; substituting the given values,
1 þ hfe

we have
50
hfb ¼ ¼ 0:98:
1 þ 50

Also,
hie 0:83  103
hie ¼ ¼ ¼ 16:27 X:
1 þ hfe 1 þ 50

Example 3.34 The h-parameters for a CE configuration are hie ¼ 2600 X; hfe ¼
100; hre ¼ 0:02  102 and hoe ¼ 5  106 S. Find h-parameters for CC
configuration.
Solution We know that hic ¼ hie .
It is given that hie ¼ 2600 X.
Therefore, hic ¼ hie ¼ 2600 X:
Also,

hfc ¼ ð1 þ hfe Þ ¼ ð1 þ 100Þ

3.12 Overall Voltage Gain 161

or
hfc ¼ 101:

and
hrc ¼ 1  hrc ffi 1:

hoc ¼ hoe ¼ 5  106 S:

Example 3.35 A bipolar junction transistor has the following h-parameters: hie ¼
2000 X; hre ¼ 1:6  104 ; hfe ¼ 49, hoe ¼ 50 mA=V. Determine the current gain,
voltage gain, input resistance and output resistance of the CE amplifier, if the load
resistance is 30 kW and the source resistance is 600 Ω.
Solution We know that
current gain
hfe
Ai ¼
1 þ hoe RL

Substituting the given values, we get

49
Ai ¼ ¼ 19:6
1 þ 50  106  30  103

Input resistance,

hre  hfe
Ri ¼ hie 
hoe þ R1L

Substituting the given values, we get

1:6  104  49
Rin ¼ 2000  ¼ 1:9062:
50  106 þ 3010
1
3

Also, voltage gain,

hfe hfe  RL Ai RL
AV ¼ h i ¼ ¼
hoe þ 1
Rin ð1 þ hoe RL ÞRin Rin
RL

Substituting the given values, we get

19:6  30  103
AV ¼ ¼ 308:5:
1:906

Overall voltage gain

162 3 Bipolar Junction Transistor (BJT)

AV  Rin
AVS ¼
Rin þ RS

or

308:5  1:906
AVS ¼ ¼ 235:
1:906 þ 600

Overall current gain

RS
AiS ¼ Ai
Rin þ RS

or

19:6  600
AiS ¼ ¼ 4:7:
1:906 þ 600

Output conductance,

hfe  hre
Gout ¼ hoe 
hie þ RS

or

49  1:6  104
Gout ¼ 50  106 
21000 þ 600
6
Gout ¼ 46:985  10 s:

Output resistance,

1 1
Rout ¼ ¼
Gout 46:985  106

or

Rout ¼ 21; 283 X or 21:283 kX:

Example 3.36 A BJT has hie ¼ 2 kX; hfe ¼ 100; hre ¼ 2:5  104 and hoe =
25 mA/V as parameter in CE configuration. It is used as an emitter follower
amplifier with Rs ¼ 1 kX and RL ¼ 500 X. Determine for the amplifier the volt-
age gain AVs ¼ VVos , the current gain Ais ¼ IIos , the input resistance Ri and output
resistance Ro.
3.12 Overall Voltage Gain 163

Solution For emitter follower (i.e. common-collector amplifier), transistor

parameters are given as under:

hic ¼ hie ¼ 2 kX
hfc ¼ ð1  hfe Þ ¼ ð1 þ 100Þ ¼ 101
hrc ¼ 1  hre ¼ 1  2:5  104 ¼ 0:99975 ’ 1
hoc ¼ hoe ¼ 25  106 s

Current gain,

hfc ð101Þ
Ai ¼ ¼ ¼ 99:75
1 þ hoc RL 1 þ 25  106  500

Input resistance,

hic  hrc  hfc

Rin ¼
hoc þ R1L

or
1  ð101Þ
Rin ¼ 2  103 ¼ 51:876 kX:
25  106 þ 500
1

Voltage gain

hfc ð101Þ
Av ¼ h i ¼
6
¼ 0:9432
hoc þ R1L Rin 25  10 þ 500
1
 51:876  103

Overall current gain

Rs
Ais ¼ Ai 
Rin þ Rs

or
1
Avs ¼ 99:75  ¼ 1:886
51:876 þ 1

Output conductance

hfc  hrc 106  ð101Þ  1

Go ¼ hoc ¼ 25 
hic þ Rs 2  103 þ 1  103
3
Go ¼ 33:69  10 s
164 3 Bipolar Junction Transistor (BJT)

Output resistance,

1 1
Ro ¼ ¼ ¼ 29:68 X:
Go 33:69  103

Example 3.37 Find Av and Rin for the given circuit as below, if hfe = 50,
hie ¼ 1 kX; hre ¼ 0 and hoe ¼ 0.
Solution From the figure, we have

Base voltage
VCC  R2
VB ¼
R1 þ R2

or

18  510
VB ¼
510 þ 510
18
VB ¼ ¼ 9V
2

Value of current IC is given by

VB  VBE VB  0
IC ¼ ¼ (neglecting VBE Þ
RE RE
3.12 Overall Voltage Gain 165

or

VB 9 9  103
IC ¼ ¼ ¼
RE 7:5  103 7:5

or

IC ¼ 1:2 mA
ICQ ¼ 1:2 mA

Again from figure, we have

VCE ¼ VCC  IC  ðRC þ RE Þ

Substituting values, we get

VCE ¼ 18  1:2  103 ð9:1 þ 7:5Þ  103

¼ 18  1:2  16:6 ¼ 1:9 V
VCEQ ¼ 1:9 V:

Also, input resistance

Ri ffi hie ffi 1 kX:

Further, input resistance of amplifier stage is given by

Rin ¼ Ri k ðR1 k R2 Þ ¼ 1 k ð510 k 510Þ ¼ 1 k 255

¼ 0:99 kX

or current gain is given by

Ai ¼ hfe ¼ 50

Voltage gain,

Ai RL
AV ¼ but RL ¼ RC ; therefore
Ri
Ai RC 50  9:1
AV ¼ ¼ ¼ 455
Ri 1
AV ¼ 455:

Example 3.38 Find ICQ and ICEQ for the given circuit shown below, given that
bdc ¼ hFE ¼ 130.
166 3 Bipolar Junction Transistor (BJT)

Solution From figure, we have

R1  R2 510  510
RTH ¼ ¼ ½* R1 and R2 in k
R1 þ R2 510 þ 510

or

RTH ¼ 255 kX

and

VCC  R2 510  18
VTH ¼ ¼ ¼9V
R1 þ R2 510 þ 510

Therefore, we have

9  0:7 8:3
IB ¼ ¼
255 þ ð130 þ 1Þ  7:5 255 þ 131  7:5

or

8:3
IB ¼
1237:5

or

IB ¼ 0:00670 mA

We know that
3.12 Overall Voltage Gain 167

IC ¼ bIB ¼ 130  6:7  103

IC ¼ 0:8719 mA:

Again, from figure, we get

VCE ¼ VCC  IC  RC  IE RE
VCE ¼ 18  0:8719  91  ð0:8719 þ 0:0067Þ  7:5
VCE ¼ 3:476 V:

Example 3.39 A transistor has adc of 0.98 and a collector leakage current ICO of
1 mA.
Calculate the collector and the base current when IE = 1 mA.
Solution Width

IE ¼ 1 mA

We can use equation

IC ¼ adc IE þ ICO
¼ 0:98  1  103 þ 1  106 ¼ 0:981  103
¼ 0:981 mA

Now using equation

IB ¼ IE  IC
¼ 1  103  0:981  103
¼ 0:019  103 ¼ 0:019 mA
¼ 19 mA

Note that IC and IE are almost equal and IB is very small.

Example 3.40 In a transistor, a change in emitter current of 1 mA produces a
change in collector current of 0.99 mA. Determine the short-circuit current gain of
the transistor.
Solution The short-circuit current gain of the transistor is given as

DiC 0:99  103

a or hfb ¼ ¼ ¼ 0:99:
DiE 1  103
168 3 Bipolar Junction Transistor (BJT)

Example 3.41 When the emitter current of transistor is changed by 1 mA, its
collector current changes by 0.995 mA. Calculate (a) its common-base short-circuit
current gain a and (b) its common emitter short-circuit current gain b.
Solution
(a) Common-base short-circuit current gain is given by

DiC 0:995  103

a¼ ¼ ¼ 0:995
DiE 1  103

(b) Common-emitter short-circuit current gain is

a 0:995
b¼ ¼ ¼ 199:
1  a 1  0:995

Example 3.42 The dc current gain of a transistor in common-emitter configuration

is 100. Find its dc current gain in common-base configuration.
Solution We can use the given equation to calculate the dc current gain in
common-base configuration.

bdc 100
adc ¼ ¼ ¼ 0:99
bdc þ 1 100 þ 1

Example 3.43 Calculate the collector current and the collector to emitter voltage
for the circuit given as follows:
Solution
(a) The base current IB is given as

ðVCC  VBE Þ VCC 9

IB ¼ ¼
RB RB 300  103
¼ 3  105 A ¼ 30 lA:

(b) The collector current IC is given as

IC ¼ bIB ¼ 50  30  106 A
¼ 1:5 mA:
3.12 Overall Voltage Gain 169

Let us check if this current is less than the collector saturation current

VCC 9
ICðsatÞ ¼ ¼ ¼ 4:5  103 A ¼ 4:5 mA
RC 2  103

Thus, the transistor is not saturated.

(c) The collector to emitter voltage

VCE ¼ VCC  IC RC ¼ 9  1:5  103  2  103 ¼ 6 V

Example 3.44 Calculate the coordinates of the operating point as fixed in the
given circuit shown below. Given RC ¼ 1 kX; RB ¼ 100 kX.
Solution
(a) The base current is

VCC  VBE VCC 10

IB ¼ ’ ¼ A ¼ 100 lA
RB RB 100  103
170 3 Bipolar Junction Transistor (BJT)

(b) The collector current is

IC ¼ bIB ¼ 60  100  106 A ¼ 6 mA

We shall not check if this current is less than the collector saturation current

VCC 10
ICðsatÞ ¼ ¼ A ¼ 10 mA:
RC 1  103

Therefore, the transistor is not in saturation.

(c) The voltage between the collector and emitter terminals is

VCE ¼ VCC  IC RC ¼ 10  6  103  103 ¼ 4 V

The figure shows the value and the direction of base current IB, collector current
IC and collector–emitter voltage VCE.
Example 3.45 In the given circuit following the figure, the transistor is replaced
by another unit of ac 125. This new transistor has b = 150 instead of 60. Determine
the quiescent operating point.
Solution
(a) The base current remains the same, i.e. 100 mA.
(b) The collector current is
3.12 Overall Voltage Gain 171

IC ¼ bIB ¼ 150  100  106 A ¼ 15 mA

The collector saturation current was 10 mA in the last example. Here also, this
current remains the same. But the calculated current IC is seen to be greater than
IC (sat). Hence, the transistor is now in saturation. In this case, the operating point is
specified as

IC ¼ ICðsatÞ ¼ 10 mA
VCE ¼ 0 V:

Example 3.46 How much is the emitter current in the following circuit, and also
calculate VC.

Solution From given equation, the base current is given as

172 3 Bipolar Junction Transistor (BJT)

VCC
IB ¼
RB þ bRC

Here,
VCC ¼ 10 V; RB ¼ 500  103 X
RC ¼ 500 X; b ¼ 100

Therefore,
10
IB ¼
500  þ 100  500
103
¼ 18  106 A 6¼ 18 mA

The emitter current is then given as

IC ffi IC ¼ bIB ¼ 100  18  106 ¼ 1:8  103 A ¼ 1:8 mA

The collector voltage

VC ¼ VCE ¼ VCC  IC RC ¼ 10  1:8  103  500 ¼ 9:1 V:

Example 3.47 Calculate the value of the 3 currents in the following circuit:
Solution From the equation given, the base current is given as
3.12 Overall Voltage Gain 173

VCC
IB ¼
RB þ ðb þ 1ÞRE

Here,

VCC ¼ 10 V; RB ¼ 1 MX ¼ 1  106 X
RE ¼ 1 kX ¼ 1  103 X; b ¼ 100

Therefore,

10
IB ¼
1 106 þ ð100 þ 1Þ  1  103
¼ 9:09  106 A
¼ 9:09 mA

Now, the collector current

Ic ¼ bIB ¼ 100  9:09  106

¼ 0:909  103 A
¼ 0:909 lA

The emitter current

IE ¼ IC þ IB ’ IC ¼ 0:909 mA:

Example 3.48 If the collector resistance RC in given circuit is changed to 1 kW,

determine the new Q-points for the minimum and maximum values of b.
Solution Since the value of the emitter current does not depend upon the value of
RC Eq. (i), the emitter current IE remains the same as calculated in previous
example. That is,
174 3 Bipolar Junction Transistor (BJT)

ðVCC  VBE Þðb þ 1Þ

IE ¼
RB þ ðb þ 1ÞRE

(i) For b ¼ 50; IE ¼ 19:25 mA

(ii) For b ¼ 200; IE ¼ 38:2 mA:
In case (i), the collector to emitter vol. is given by

VCE ¼ VCC  ðRC þ RE ÞIE ¼ 6  ð1000 þ 100Þ  19:25  103

¼ 6  21:17 ¼ 15:17 V

The above result is not acceptable as sum of V drop across RC and RE cannot be
greater than the supply vol. VCC. Is our calculation wrong? Certainly not, we face
such difficulties when the transistor is in saturation. The maximum possible current
that can be supplied by the battery VCC to the output section is

VCC 6
ICðsatÞ ¼ ¼ ¼ 5:45  103 A ¼ 5:45 mA
RC þ RE 1000 þ 100

Under saturation, the collector to emitter vol. is

VCEðsatÞ ¼ 0 V
3.12 Overall Voltage Gain 175

(ii) We have seen that the transistor is in saturation when its b = 50. In case
b = 200, there is all the more reason for the transistor to be in saturation. So,
the Q-point will be the same as calculated earlier, i.e.

ICðsatÞ ¼ 5:45 mA; VCðsatÞ ¼ 0 V

Example 3.49 Calculate the value of RB in the biasing circuit of given below
circuit so that the Q-point is fixed at IC = 8 mA and VCE = 3 V.

Solution The current IB is given as

IC
IB ¼
b

Here,

IC ¼ 8 mA ¼ 8  103 A and b ¼ 80

Therefore,

8  103
IB ¼ ¼ 1  104 A ¼ 100 mA
80
176 3 Bipolar Junction Transistor (BJT)

From equation,
VCC  VBE VCC
IB ¼ ’
RB þ ðb þ 1ÞRE RB þ bRE

We have
IB RB þ ðb þ 1ÞIB RE ¼ VCC  VBE ’ VCC

or
VCC  ðb þ 1ÞIB RE
RB ¼
IB

Here,
VCC ¼ 9 V; b ¼ 80; IB ¼ 1  104 A; RE ¼ 500 X

Therefore,
9  ð80 þ 1Þ  1  104  500 4:95
RB ¼ 4
¼ X
1  10 1  104
¼ 49:5 kX:

Example 3.50 To set up 100 mA of emitter current in the power amplifier circuit
of given figure.
Calculate the value of the resistor RE. Also, calculate VCE. The dc resistance of
the primary of the output transformer is 20 X.
3.12 Overall Voltage Gain 177

Solution Given

R1 ¼ 200 X; R2 ¼ 100 X; RC ¼ 20 X; VCC ¼ 15 V;

IC ’ IE ¼ 100 mA ¼ 0:1 A

From equivalent

VCC  R2
VB ¼
R1 þ R2

the base voltage is

100
¼  15 ¼ 5 V
200 þ 100

Neglecting VBE,

VE ¼ 5 V

From equivalent

VE
IE ¼
IE
5
¼ ¼ 50 X
0:1

The collector to emitter voltage is then calculated using equation

VCE ¼ VCC  ðRC þ RE ÞIC

¼ 15  ð20 þ 50Þ  0:1 ¼ 8 V:

Example 3.51 Calculate IC and VCE the emitter bias circuit of given figure, where
VCC ¼ 12 V; VBE ¼ 15 V; RC ¼ 5 kX; RE ¼ 10 kX; RB ¼ 10 kX; b ¼ 100.
178 3 Bipolar Junction Transistor (BJT)

Solution From equation, IE ¼ VREEE , the emitter current is

VEE 15
IE ¼ ¼ ¼ 1:5  103 A ¼ 1:5 mA
RE 10  103

The collector current is

IC ffi IE ¼ 1:5 mA

Using equation

VCE ¼ VCC  IC Rc ; the voltage VCE is

¼ 12  1:5  103  5  103
¼ 12  7:5 ¼ 4:5 V:

Summary
1. Basics: Bipolar junction transistor (BJT) is just called a transistor. It is a
three-terminal device, namely emitter, base and collector. It has three semi-
conductor layers having a base or centre layer, a great deal thinner than the other
two layers. The outer two layers are both of either N- or P-type material, and the
sandwiched layer the opposite type. The arrow in the transistor symbol defines
the direction of conventional current flow for the emitter current and thereby
defines the direction for the other currents of the device. The arrow in the
symbol of an NPN transistor points out of the device, whereas the arrow points
into the centre of symbol for PNP transistor.
3.12 Overall Voltage Gain 179

2. Biasing: In the active region of a transistor, the base–emitter junction is

forward-biased and the collector–base junction is reverse-biased. In the cut-off
region, the base–emitter and collector–base junctions of a transistor are both
reverse-biased. In the saturation region, the base–emitter and collector–base
junctions are forward-biased.
3. Currents: The dc emitter current is always the largest current of a transistor, and
the base current is always the smallest. The emitter current is always the sum of
the other two. The collector current is made up of two components—the
majority component and the minority current also called the leakage current.
4. VBE, a and b: Base to emitter voltage (VBE) is 0.7 V approximately. a is always
close to one. b is usually between 50 and 400.
5. Impedance between transistor terminals: The impedance between terminals
of forward-biased junction is always relatively small, whereas the impedance
between terminals of reverse-biased junction is usually quite large.
6. Important Formulae:
(i) IE = IC + IB
VBE 0:7 V for silicon transistor
(ii)
0:3 V for germanium transistor
(iii) a ¼ adc ¼ IICE


C

(iv) aac ¼ DI
DIE
V ¼constant


CB
CBO

(v) ICEO ¼ I1a IB ¼0lA
(vi) b ¼ bdc ¼ IICB


C

(vii) bac ¼ DI
DIB
VCE ¼constan t
(viii) a ¼ b þb 1
(ix) IC ¼ bIB þ ICEO bIB for ICEO  IB
(x) IE ¼ ðb þ 1ÞIB
(xi) PC max ¼
VCE IC


(xii) ri ¼ DV
DIE
V ¼constant for CB configuration
EB

CB
CB

(xiii) ro ¼ DVDIC
I ¼constant for CB configuration

E
DVBE

(xiv) ri ¼ DIB


VCE ¼constant for CE configuration
0 DVCE

(xv) ro ¼ DIC

IB ¼constant
(xvi) RB ¼ VCCIV
B
BE
for base resistor method.
(xvii) RB ¼ VCC VBE
IB
bIB IC
for feedback resistor
(xviii) IC ¼ V2 V
RE ,
BE

 
where V2 ¼ R1VþCCR2 R2 .
180 3 Bipolar Junction Transistor (BJT)

and VCE ¼ VCC  IC ðRC þ RB Þ for potential divider

RAC
Av ¼ b  ; where RAC ¼ ac load
Ri
(xix)
¼ RC if no load connected
¼ RC k RL if load RL connected:
(xx) Ap ¼ b2  RRACi = current gain  voltage gain
(xxi) AC load line is between VCE max and IC max

VCE max ¼ VCE þ IC RAC

VCE
IC max ¼ IC þ
RAC

Exercises
3:1 Why is an ordinary transistor called BJT? Explain basic construction and
operation of a transistor.
3:2 Give brief operations of input/output characteristics of a transistor.
3:3 Derive the relationship between a and b.
3:4 What are the factors responsible for the stability of operating point?
3:5 Draw a self-bias circuit and derive an expression for stability factor.
3:6 State various methods of improving stability.
3:7 Define stability factor w.r.t. transistor biasing.
3:8 Explain the function of emitter in the operation of a junction transistor.
3:9 Derive the hybrid or h-parameters for a two-port network.
3:10 Find the hic in terms of the CB h-parameters.
3:11 In a common-base connection, current amplification factor is 0.9. If the
emitter current is 1 mA, determine the base current. [Ans. 0.1 mA].
3:12 In a common-base connection, the emitter current is 1 mA. If the emitter
circuit is open, the collector current is 50 µA. Find the total collector current
given that a = 0.92. [Ans. 0.97 mA]
3:13 Find the value of b if
(i) a = 0.9
(ii) a = 0.98
(iii) a = 0.99 [Ans. 9,49,99]
3:14 The base current in a transistor is 0.01 mA, and emitter current is 1 mA.
Calculate the values of a and b. [Ans. 0.99,99].
3:15. The collector leakage current in a transistor is 300 µA in CE arrangement.
3.12 Overall Voltage Gain 181

If the transistor is now connected in CB arrangement, what will be the leakage

current? Given that b = 120. [Ans. 2.4 µA].
3:16 For a certain transistor, IB = 20 µA, IC = 2 mA and b = 80. Calculate ICBO.
[Ans. 0.0008 mA].
3:17 In the following circuit, find the operating point given that b = 100. Neglect
VBE.

[Ans. 8 V, 4 mA].
3:18 The given figure shows a silicon transistor biased by feedback resistor
method. Determine the operating point. Given that b = 100.
[Ans. 10.4 V, 9.6 mA].

3:19 Find the operating point in the circuit shown below. Assume b = 75 and
VBE = 0.7 V. [Ans. 10.59 V, 2.47 mA].
182 3 Bipolar Junction Transistor (BJT)

3:20 Given figure shows the voltage divider bias method. Draw the dc load line
and determine the operating point. Assume the transistor to be of silicon.
[Ans. 8.55 V, 2.15 mA].

3:21 An NPN transistor circuit has a = 0.985 and VBE = 0.3 V. If VCC = 16 V,
calculate R1 and RC to place Q-point at IC = 2 mA, VCE = 6 V.
3.12 Overall Voltage Gain 183

3:22 What are CB, CE and CC configurations of a transistor? Explain with circuit
diagram.
3:23 What do you understand by biasing of a transistor? Explain various methods
for biasing a transistor.
3:24 Give comparison of various methods of biasing a transistor.
3:25 What is graphical analysis of a transistor? Describe in detail.
3:26 Give the concept of voltage gain and current gain of a transistor.
Chapter 4
Field Effect Transistor (FET)

4.1 Introduction

In the bipolar junction transistor, the output collector current is dependent on the
amount of current flowing into the base terminal; therefore, it is known as a
current-operated device. Field effect transistors or FETs use the voltage which is
applied to the gate and source terminals to control the output current. Hence, FET is
a voltage-operated device. The operation relies on the electric field generated by the
input voltage; hence, the name is field effect transistor (FET), and it also implies
that FET is voltage-operated device. As it is voltage-controlled device similar to a
vacuum tube, hence, others are replaced by vacuum tubes.
FETs are unipolar devices which have very similar properties as that of BJTs.
FETs also have high efficiency and instant operation, and they are also robust,
cheap and can be used in most of the applications where BJTs are used. FETs can
be made much smaller than an equivalent BJT. It also has lower power con-
sumption and dissipation; hence, they are ideal for use in integrated circuits and
computer circuit chips. As an amplifier, the JFET offers a higher input impedance
than JBT, generates less self-noise and has greater resistance to nuclear radiations.
Thus, JFETs have also replaced vacuum tubes.
FETs have extremely high input impedance; hence, these are very sensitive. This
also implies that FETs can be damaged by static electricity. FETs are of two major
types: the junction field effect transistor (JFET) and the metal–oxide semiconductor
field effect transistor (MOSFET) which are also called the insulated gate field effect
transistor (IGFET).

© The Author(s), under exclusive license to Springer Nature Switzerland AG 2022 185
O. N. Pandey, Electronics Engineering,
https://doi.org/10.1007/978-3-030-78995-4_4
186 4 Field Effect Transistor (FET)

FET tree

4.2 Junction Field Effect Transistor (JFET)

A BJT is constructed using P–N junctions on the current path between emitter and
collector terminals. The FET has no junction instead has a narrow “channel” of N-
type or P-type silicon with electrical connections at either and commonly called the
drain and the source. Figure 4.1 shows the basic construction of the N-channel
JFET. The major part of the structure is then-type material which forms the channel
between the embedded layers of P-type material. The top of the N-type channel is
enacted through an ohmic intact to a terminal known as the drain (D). The lower
end of the same material is enacted through an ohmic intact to a terminal known as
sure (5). Both P-type materials are connected together and both through the gate
(G). In short, the drain and the source are connected to the ends of the N-type
channel and the gate to the two layers of P-type materials. If no potential is applied,
there are no-bias renditions. This loads to a depletion region at each junction which
looks similar to the same region of a diode under no-bias renditions. Similarly, P-
channel JFET is as per Fig. 4.2, please bite-that in this case the major part of
construction is the P-type material. Further, the two P–N junctions in terming
diodes are connected internally and gate. The important analogy between BJT and
JFET is as follows:
Bipolar junction transistor Junction field effect transistor
(BJT) (JFET)
Emitter (E) Source (S)
Base (B) Gate (G)
Collector (C) Drain (D)

Instead of an ac current, a JFET has a dc source current IS ; instead of a dc base

current IB , it has a dc drain current ID .
In a JFET, there is only one type of carrier, holes in P-type channel and electrons
in N-type channel. Hence, FET is also known as unipolar. In the ordinary transistor,
4.2 Junction Field Effect Transistor (JFET) 187

Fig. 4.1 Construction of

N-channel JFET

Fig. 4.2 Construction of P-

channel JFET

both holes and electrons play its part in construction. Therefore, ordinary transistors
are also known as bipolar transistor.

4.3 Working Principle of JFET

Polarities of N-channel JFET and P-channel JFET are shown in Fig. 4.3.
The voltage between the gate and source is as such that the gate is reverse
biased. The drain and source terminals are interchangeable. D and S terminals are
interchangeable. That is why, polarity of bias voltage between D and S has not
changed in both types of JFET.
Suppose a VDS voltage is applied between drain and source terminals while there
is no voltage on the gate as shown in Fig. 4.4a, the two P–N junctions at the sides
of the bar establish depletion layers. Hence, electrons will flow from source to drain
through a channel between the depletion layers, the size of the depletion layers
188 4 Field Effect Transistor (FET)

Fig. 4.3 Biased JFET

Fig. 4.4 Working of JFET

determines the width of the channel, and therefore, the amount of electron flow
through the channel. If a reverse voltage VGS is applied between gate and source as
shown in Fig. 4.4b, the width of the depletion layer is increased. In turn, the width
of conducting channel is reduced and as such the resistance of N-type bar is
increased. This leads to reduction in current from source to drain. However, if the
reverse voltage on the gate is decreased, the width of depletion is also reduced,
thereby increasing the width of the conducting channel. This in turn decreases the
resistance of N-type bar which increases the current from source to drain.
In short, the current from source to drain can be controlled by applying voltage
on the gate. A P-channel JFET operates similar to an N-channel JFET with only one
exception that the current carrier will be holes instead of electrons, and also the
polarities of VGS and VDS are reversed.
JFET symbols are shown in Fig. 4.5.
The arrow points in the direction IG current would flow of the P–N junction
which is forward biased. The arrow points in for N-channel JFET, whereas arrow
points out for P-channel.
4.4 Concept of Pinch-Off and Maximum Drain Saturation Current 189

Fig. 4.5 JFET symbols

4.4 Concept of Pinch-Off and Maximum Drain Saturation

Current

Consider JFET of Fig. 4.6, when VDS voltage is increased from zero to a few volts,
the current will increase linearly as per Ohm’s law. The plot of ID versus VDS for
VGS = 0 is shown in Fig. 4.7, when VDS approaches a level VP of.
In Fig. 4.7, the depletion regions widen causing reduction in channel width. This
increases the resistance of the current, and finally there is a situation that when VDS
goes beyond a value of VP0 , the width of conduction does not reduce further and
current density is very high. Further increase of VDS does not affect the channel
width, and the ID remains at saturation level. The voltage VP is known as pinch-off
voltage. IDSS is the
maximum

drain current for a JFET defined by the conditions
VGS ¼ 0 and VDs [
Vp
.

Fig. 4.6 JFET at

VGS ¼ 0 and VDS [ 0
190 4 Field Effect Transistor (FET)

Fig. 4.7 ID versus VDS plot

for VGS ¼ 0 V

4.5 Input and Transfer Characteristics

The relationship between input and output of JFET is not linear. The relationship
between VGS (input) and ID (output) is defined by Shockley’s characteristics
equation given under:
 
VGS 2
ID ¼ IDsS 1  ð4:1Þ
Vp

where
IDSS ¼ a constant value
VP ¼ a constant value

The squared term in the equation gives a nonlinear relationship between VGS and
ID . This produces a curve. ID increases exponentially with decreasing magnitude of
VGS . The transfer characteristics given by the equation are unaffected by the net-
work in which the device is employed. The input VGS and transfer characteristics
are shown in Fig. 4.8. ID is maximum (IDSS ) when VGS ¼ 0. ID is zero when
VGS ¼ 4 V. The transfer characteristics are obtained for various values of VGS as
shown in the right-hand side of the plot in Fig. 4.8.
The important aspects of the characteristics may be noted, i.e., initially, the drain
current ID increases rapidly with drain–source voltage VDS0 but finally it becomes
constants.
The gate–source voltage where the channel is completely cutoff and drain cur-
rent becomes zero is known as gate–source cutoff voltage (VGsOFF ).

4.6 Parameters of JFET

The main parameters of JFET are ac drain resistance, transconductance and

amplification factor.
4.6 Parameters of JFET 191

Fig. 4.8 Input and transfer characteristics

(i) AC Drain Resistance ðrd Þ

The ratio of change in drain–source voltage ðDVDS Þ to the corresponding change
in drain current ðDID Þ at constant gate–source voltage is known as ac drain resis-
tance ðrd Þ.

DVDS
ac drain resistance, rd ¼ at a constant VGS : ð4:2Þ
DID

It is expressed in kX or MX.
(ii) Transconductance ( gm )
The ratio of change in drain current ðDIo Þ to the corresponding change in gate–
source voltage ðVGS Þ at a constant drain–source voltage VDS is known as
transconductance (gm ).

DID
Tranconductanec; gm ¼ at a constant VDS ð4:3Þ
DVGS

It is expressed in ma/V, millimhos or micromhos.

(iii) Amplification Factor ( l)
The ratio of change in drain–source voltage (ΔVDS) to the change in gate—source
voltage ðDVGs Þ at a constant drain current is known as amplification factor (l).
192 4 Field Effect Transistor (FET)

DVDS
Amplification factor, l ¼ at a constant ID ð4:4Þ
DVGS

Basically, it gives gate voltage effectiveness compared to the drain voltage in

controlling the drain current. It can also be expressed in terms of ac drain resistance
and transconductance.
It is known that
DVDS
l¼
DVGS
 
VGS 2
ID ¼ IDSS 1 
VP

The above expression can be manipulated as follows:

  
@ID VGS 1
¼ 2IDS 1  
@VGS VP VP
 
DVDS DID 2 ID 1=2
l¼  ¼ IDSS
DVGS DID jVP j IDSS

DVDS DID 2
¼  ¼ ðID IDSS Þ1=2
DID DVGS jVP j

DVDS DFD
) l ¼ rd  gm as ¼ rd and ¼ gm
DID DVGS
 
VGS
gm ¼ gm 0 1 
VP
where

2IDSS
gm 0 ¼
VP

4.7 JFET Biasing

JFET gate must be negative with respect to source for the proper operation.
A battery in gate circuit or a biasing circuit is essential. JFET biasing circuit is
preferred as batteries are costly and require frequent replacement.
4.7 JFET Biasing 193

Fig. 4.9 Fixed biasing of a

N-channel JFET

4.7.1 Fixed-Biasing of JFET

Proper gate–source voltage VGS is required to give desired drain current ID . A fixed
biasing is achieved through batteries as shown in Fig. 4.9.
For dc analysis, capacitors work as open circuit (Xc ¼ 2pfC
1
¼ 1 as f ¼ 0).
From the gate–source voltage circuit, we get

VGS ¼ VG  VS ¼ VGG  0

or
VGS ¼ VGG ð4:5Þ

The drain current gets fixed by equation (1), i.e.,

 
VGS 2
ID ¼ IDSS 1 
VP

The voltage drop drain resistor RD is

VRD ¼ ID RD

) Output voltage,
V0 ¼ VDD  ID RD ð4:6Þ

4.7.2 Self-Biasing of JFET

A self-biasing circuit is shown in Fig. 4.10, and RS is the bias resistor.

194 4 Field Effect Transistor (FET)

Fig. 4.10 Self-biasing of

JFET

The drain current dc component flowing through resistor RS creates the desired
biasing voltage. The ac component of drain current gets bypassed through CS
capacitor voltage across source resistor RS is given by

VS ¼ ID RS

)
VGS ¼ VG  VS ¼ 0  VS as gate current is negligibleVG ¼ 0:

or
VGS  ID RS :

The above equation keeps the gate negative w.r.t. source to terminal.
The dc operating, i.e., zero signal ID and VDS can be determined by following
equations:
 
VGS 2
ID ¼ IDSS 1 
VP

and
VDS ¼ VDD  ID ðRD þ RS Þ:

4.7.3 Potential Divider Method of Biasing JFET

Potential divider method of biasing JFET is shown in the circuit of Fig. 4.11.
The resistors R1 and R2 form a potential divider across drain power supply VDD .
4.7 JFET Biasing 195

Fig. 4.11 Potential divider

method of biasing of JFET

VDD
V2 ¼  R2
R1 þ R2

and

V2 ¼ VGS þ ID RS

or

VGS ¼ V2  ID RS

V2 is smaller than ID RS as per design to keep VGS negative for proper biasing.
From above equation, we get

VDD  VD
ID ¼
RD

and

VDS ¼ VDD  ID ðRD þ RS Þ:

4.8 JFET Connections

It can be connected in three configurations, namely common gate (CG), common

source (CS and common drain (CD).
196 4 Field Effect Transistor (FET)

4.8.1 Common Gate JFET Configuration

Figure 4.12 shows the circuit of a common gate amplifier. The equivalent circuit of
the same is shown in Fig. 4.13.
The last JEET configuration to be analyzed in detailed is the common gate
configuration of Fig. which parallel the common base configuration employed with
BJT transistors.
The network of interest is redrawn in Fig. 4.14. The voltage V ′ = VGS. Applying
Kirchhoff's voltage around the output parameter of the network results in

V 0  VRD  VRD ¼ 0
VRD ¼ V 0  VRD
¼ V 0  IRD

Applying Kirchhoff's current law at mode results in

I 0 þ gm VGS ¼ IRD

Fig. 4.12 JEET common

gate configuration

Fig. 4.13 JEET ac equivalent model

4.8 JFET Connections 197

Fig. 4.14 Determining Zi for

the network

and

I 0 ¼ gm VGS
V 0  I 0 RD
¼  gm VGS
RD

or

V 0 I 0 RD
I0 ¼   gm ½V 0 
RD RD

so that
 
0 RD
I ¼ 1þ
rd
 
0 1
¼V þ gm
rd

and
h i
V0 1 þ RrdD
RGS ¼ 0 ¼h i
I gm þ r1d

or
0
RGS ¼ VI 0 ¼ 1rdþþgmRrDd

V0 rd þ RD
RGS ¼ ¼
I0 1 þ gm rd
198 4 Field Effect Transistor (FET)

and

Rin ¼ RS kRCS

which results in
h i

Rin ¼ RS  1rdþþgmRrDd

If rd  10RD , Eq. permits the following approximation since RVDd \1 and r1d  gm
h i
1þ
RD
rd 1
RGS ¼ ffi
gm þ r1d gm

and


Ri ffi RS g1m

Z0 substitutions Vi ¼ OV in figure will “short-out” the effects of Rs and get VGS

to OV. The results are gm VGs ¼ 0, and rd will be in parallel with RD . There are

R0 ¼ RD krd

For
rd  10RD

R0 ffi RD

Figure reveals that

vi ¼ VGS

and
vo ¼ ID RD

The voltage across rd is

VRD ¼ vo  vi
4.8 JFET Connections 199

and
vo  vi
IRD ¼
fr

Applying Kirchhoff’s current law and note b in figure results in

IRD þ ID þ gm VGS ¼ 0
ID ¼ IRD  gm VGS
 
vo  vi
¼  gm ½vi 
rd
vi  ve
In ¼ þ gm v i
rd

So that
vo ¼ ID RD
 
vi  vo
¼ þ gm v i R D
rd
vi  vo vo RD
¼  þ gm vi RD
rd rd
   
RD RD
vo 1 þ ¼ vi þ gm RD
rd rd
RD
rd þ gm RD
Av ¼
1þ RD
rd

for rd  10RD

Av ffi gm RD

4.8.2 Common Source JFET Configuration

Common source JFET configuration is shown in Fig. 4.15, and the equivalent
circuit of the same is shown in Fig. 4.16.

Zi Due to open circuit condition between the gate and output network, the input
remains the following:
Ri ¼ RG

Zo The output impedance is defined by

200 4 Field Effect Transistor (FET)

Fig. 4.15 Common

source JFET configuration

Fig. 4.16 Equivalent circuit

vo


R0 ¼

I0 vi ¼0

Setting vi = OV in figure results in the gate terminal being at around potential

(OV). The voltage across RG is then OV, and RG has been effectively “sorted out” of
the picture.
Applying Kirchhoff’s current law results in

I0 þ ID ¼ gm VGS

With

VGS ¼ ðI0 þ I0 ÞRS

so that

I0 þ ID ¼ gm ðIO þ ID ÞRS ¼ gm Io RS  gm ID RS

or

Io ½1 þ gm RS  ¼ I0 ½1 þ gm RS 
4.8 JFET Connections 201

Fig. 4.17 Equivalent circuit if RD is included in the network

and I0 ¼ ID (the controlled current source gm VGS ¼ OA for the applied
conditions)
vo ¼ I D R D
vo ¼ ðIo ÞRD ¼ I0 RD

R0 ¼ vvoo ¼ RD

If RD is included in the network, the equivalent will appear as shown in

Fig. 4.17.
Since


vo
ID RD
R0 ¼

¼
I0 vi ¼ov I0

We shortly try to find an expression for I0 in terms of ID .

Applying Kirchhoff’s current law, we have

vo þ VGS
I0 ¼ gm VGS þ Ird  ID
rd
Vrd ¼ vo þ VGS

and

I0 ¼ gm VGS þ  ID

or
 
1 Id rd
I0 ¼ gm þ VGS   I0 using VD ¼ ID RD
rd rd
202 4 Field Effect Transistor (FET)

Now

Vgs ¼ ðID þ I0 ÞRs

So that
ID R D
I0 ¼ ðID þ I0 ÞRt   ID
rd

with the result that

   
RS RS RD
I 0 1 þ gm R s þ ¼ ID 1 þ gm RS þ þ
rd rd rd

or
h i
ID 1 þ gm Rs þ rd þ rd
Rs RD

I0 ¼
1 þ gm Rs þ Rrds

and
vo ID RD
R0 ¼ ¼ 
I0 ID 1 þ gm Rs þ Rd
rd rd

1 þ gm Rs þ Rr s
d

1 þ gm R s þ Rs
R0 ¼ h rd
i Rd
1 þ gm Rs þ Rs
rd þ RD
rd

For

rd  10RD
R0 ¼ RD

AV—for the network of Fig. 4.17 application of Kirchhoff’s voltage law to the
input circuits results.

vi  VGs  VRS ¼ 0

VGS ¼ vi  ID RD

The voltage across RD using Kirchhoff's voltage law is

VRD ¼ vo  VRS
4.8 JFET Connections 203

and

VRD v0  VRs
I0 ¼ ¼
rd rd

So that application of Kirchhoff current law results in

v0  VRS
ID ¼ gm VGS þ
rd

Substituting for VGS from above and substituting for V0 and VRS0 we have

ðID RD Þ  ID Rs
I D ¼ gm ½ v i  I D R s  þ
rd

So that
 
RD þ Rs
I D 1 þ gm R s þ ¼ gm v i
rd
gm v i
ID ¼ RD þ Rs ID
1 þ gm R s þ rd

The output voltage is then

vo ¼ ID RD
gm RD vi
¼
1 þ gm Rs þ RD rþd Rs
vo
Av ¼
vi
gm RD
¼
1 þ gm Rs þ RD rþd Rs

Again if rd  10ðRD þ Rs Þ

vo gm R D
AV ¼ ¼
vi 1 þ gm R s

4.8.3 Common Drain JFET Configuration

Figure 4.18 shows the common drain (CD) JFET configuration, and the equivalent
circuit of the same is shown in Fig. 4.19.
204 4 Field Effect Transistor (FET)

Fig. 4.18 CD JFET amplifier circuit

Fig. 4.19 Equivalent circuit for CD amplifier

We can see that

VGS ¼ vi  vo and RGS ¼ R1 kR2

and also

v o ¼ I D ð r d kR s kR L Þ

or

vo ¼ gm VGS ðrd kRs kRL Þ

We can also see that

vi ¼ VGS þ vo ¼ VGS þ VGS gm ðrd kRS kRL Þ

4.8 JFET Connections 205

We consider that

rd  Rs kRL

) Voltage gain,
vo
Av ¼
vi

or
gm ðRS jjRL Þ
Av ¼
1 þ gm ðRS jjRL Þ

We should also note that

Rin ¼ RG ¼ R1 kR2

For output resistance, we get

RGS
VGS ¼ vo 
ðRGS kRG Þ þ RGS

We take

RGS  ðRS kRS Þ; hence, VGS ¼ vo and ID ¼ gm VGs

Further,

vo VGS 1
RS ¼ ¼ ¼
ID gm VGS gm
1
In fact, rd is in parallel with gm ,
but
1
rd 
gm

)   
1
Ro ¼ RS 
g
m
206 4 Field Effect Transistor (FET)

4.9 Metal–Oxide Semiconductor Field Effect Transistor

(MOSFET)

Metal–oxide semiconductor field effect transistor (MOSFET) is a semiconductor

device which is similar to JFET with some modifications. The constructional details
of N-channel MOSFET are shown in Fig. 4.20. It has only one P-region which is
called substrate. A thin layer of metal–oxide normally silicon oxide is deposited
over the left side of the channel. Over the oxide layer, a metallic gate is deposited.
Since silicon dioxide (SiO) is an insulator, hence, gate is insulated from the channel.
Due to this fact, MOSFET is also known as insulated gate field effect transistor
(IGFET). Similar to JFET, MOSFET also has three terminals, namely source (S),
gate (G) and drain (D). Electrons flow from source to drain through N-channel.
Symbol of N-channel MOSFET is shown in Fig. 4.20. Gate looks like a
capacitor plate. The thick dark line represents the channel. The top lead is drain, and
bottom lead is source. The arrow points from substrate to N-channel material.
Normally, substrate terminal is internally connected; therefore, N-channel MOSFET
symbol becomes as shown in Fig. 4.21b.
Similarly, P-channel MOSFET construction is shown in Fig. 4.22. The parts are
quite clear except that N-type substrate constructs the conducting P-channel
existing between the source and drain. In this case, holes flow from source to drain
the narrow P-channel. The P-channel MOSFET symbols are shown in Fig. 4.23.
Similar to N-channel MOSFET, Fig. 4.23a shows P-channel MOSFET with four
terminals; Fig. 4.23b shows with three terminals wherein substrate is internally
connected.

Fig. 4.20 N-channel MOSFET construction

4.9 Metal–Oxide Semiconductor Field Effect Transistor (MOSFET) 207

Fig. 4.21 N-channel MOSFET symbol and internal connection

Fig. 4.22 P-channel MOSFET construction

Fig. 4.23 Symbol of P-channel MOSFET

208 4 Field Effect Transistor (FET)

It is important to note that the arrow is on the channel and points to the substrate,
and flow of holes takes place from source to drain through the narrow P-channel.

4.10 MOSFET Operation

The gate and the N-channel act like the plates of a capacitor. The metal–oxide layer
acts as dielectric between two capacitor plates. Consider the circuit of Fig. 4.24. If
the gate voltage is changed, then the electric field of the so-called capacitor
changes. Consequently, the resistance of the N-channel is changed. We can apply
either negative or positive voltage on the gate as it is insulated from the N-channel.
When negative voltage is applied, the operation is known as depletion mode. On the
other hand, when positive voltage is applied at the gate, the operation is known as
enhancement mode. Any MOSFET which can be operated, both in depletion and
enhancement modes, is designated as DE-MOSFET.

4.10.1 Depletion Mode Operation

The circuit used for depletion mode operation is shown in Fig. 4.24a. As the gate is
negative, hence, electrons are on gate acting as plate of capacitor. The electrons on
the plate repel the free electrons in N-channel. This leaves a layer of positive ions on
the part of N-channel next to oxide layer as shown in Fig. 4.24b. Consequently, N-
channel is emptied or depleted of some electrons. Hence, a lesser number of free
electrons are available for conduction of current through N-channel. It is just like N-
channel resistance increase. If the negative voltage on the gate is increased, the
current from source to drain is reduced. It can be seen that a change of negative
voltage at the gate changes the resistance of N-channel. This leads to change in
current from source to drain.

Fig. 4.24 N-channel MOSFET circuit

4.10 MOSFET Operation 209

Fig. 4.25 Enhancement mode operation of N-channel MOSFET

4.10.2 Enhancement Mode Operation

A circuit for enhancement mode operation of MOSFET is shown in Fig. 4.25a. As

explained earlier, the gate and N-channel act as plates and oxide layer as insulator of
a capacitor. As the gate is positive in this case, it induces negative change in the N-
channel as shown in Fig. 4.25b.
Basically, the negative charges on the plate of capacitor are electrons. Hence, the
number of free electrons in the N-channel is increased. Consequently, the con-
duction of current from source to drain is increased, i.e., resistance of N-channel is
reduced. Thus, higher the positive voltage on the gate, lower is the current con-
duction from source to drain. In short, any change of the positive voltage on the
gate changes the conductivity of the N-channel. Any increase in positive voltage on
the gate enhances the conductivity of N-channel; hence, it is known as enhancement
Mode of operation.

4.11 Characteristics of MOSFET

It has been explained that in an N-channel MOSFET, the gate (positive plate),
metal–oxide film (dielectric) and substrate (negative plate) form a capacitor. The
electric field of this capacitor controls N-channel resistances. The N-channel
resistance is dependent on the potential of the gate. If the gate is negative, then the
N-channel resistance increases. However, if the gate is positive, the N-channel
resistance decreases. Typical drain characteristics are shown in Fig. 4.26 for
threshold voltage VT ¼ 2V when the N-channel MOSFET operation begins.
Threshold voltage is the one when no drain current flows.
The transfer characteristics of depletion mode N-channel MOSFET operation are
shown in Fig. 4.27. In this case, the gate voltage must be sufficiently negative to
210 4 Field Effect Transistor (FET)

Fig. 4.26 Drain

characteristics of N-channel
MOSFET

Fig. 4.27 N-channel

MOSFET (depletion) transfer
characteristics

ensure that no drain current flows in the OFF condition. Any suitable voltage
between this value and zero results in the device being switched ON.
The transfer characteristics of enhancement mode N-channel MOSFET operation
are shown in Fig. 4.28. The operation in enhancement mode avoids the need for
negative voltage to ensure the OFF operation since this is its normal condition.
Again a positive gate voltage causes ON operation to occur.
Salient points of MOSFET operation are as follows.
The gate, oxide layer and N-channel form a capacitor in the operation of a
MOSFET, therefore, the following advantages may be noted:
(i) The drain current is controlled by voltage at the gate.
(ii) It can be operated with positive and negative gate voltage.
4.11 Characteristics of MOSFET 211

Fig. 4.28 N-channel

MOSFET (enhancement)
characteristics

(iii) Negligible gate current flows irrespective of gate having negative or positive
voltage; hence, the input impedance is very high in the range of several
thousand megaohms.
Solved Examples
Example 4.1 The pinch-down voltage of a P-channel junction FET is Vp ¼ 5 V,
and the drain-to-source saturation current IDSS ¼ 40 mA.The value of drain–
source voltage VDS is such that the transistor is operating in the saturated region.
The drain current is given as ID ¼ 15 mA. Determine the gate–source voltage
VGS .
Solution It is found experimentally that a square law characteristic closely
approximates the drain current in saturation.
 
VGS 2
IDðsatÞ ¼ IDss 1 
VP

given that:
Vp ¼ 5 V
IDSS ¼ 40 mA
ID ¼ 15 mA
 2
VGS
15 mA ¼ 40 mA 1 
5

or
rffiffiffiffiffi
15 VCS
¼1
40 5

)
212 4 Field Effect Transistor (FET)

VGS
1 ¼ 0:612
5
VGS
¼ 0:612  1 ¼ 0:3876
5
VGS ¼ 1:938 volt: þ ve:

Example 4.2 A JFET amplifier with stabilized biasing circuit shown below has the
following parameters:

Vp ¼ 2 V, VDSS ¼ 5 mA, RL ¼ 910 X, RF ¼ 2:29 kX, R1 ¼ 12MX,R2 ¼ 8:57

MX and VDD ¼ 24 V.
Determine the value of drain current ID at the operation point and also verify that
FET will operate in pinch-off region.
Solution Given that drain supply Vol,

VDD ¼ 24 V

Load resistance,

RL ¼ 910 X

Source circuit resistance Rp ¼ 2:29 kX.

Drain–source saturation current

IDSS ¼ 5 mA
¼ 5  103 A

Pinch-off voltage
4.11 Characteristics of MOSFET 213

VP ¼ 2 V
R1 ¼ 12 MX
R2 ¼ 8:57 MX

Now, we know that the gate vol is given by

VDD  R2 24  8:57
VG ¼ ¼ ¼ 10 V
R1 þ R2 12 þ 8:57

Also, drain current ID is given by

   2
VGS 2 3 1  10  2:29  10 ID
3
ID ¼ IDSS 1 ¼ 5  10
VP 2

or

ID ¼ 5  103 ½1 þ 5  1; 145 ID 2 ¼ 0:005½6  1; 145 ID 2

Solving, we get

ID ¼ 4:46 mA

Gate–source voltage VGS is given by

VGS ¼ VG  ID RF ¼ 10  2:29  103  4:46  103

or

VGS ¼ 0:2134 volt:

Current at operating point is given by

VG  VGS 10  0:2134
ID ¼ ¼ ¼ 4:27 mA:
RF 2:29  103

It may be noted that the value of ID at operating point is almost equal to

previously computed value of ID . Therefore, we can say that the FET is operating in
pinch-off region.
Example 4.3 A JFET amplifier has gm ¼ 2:5 mA=V and rd ¼ 500 kW. The load
resistance is 10 kW. Find the value of voltage gain.
214 4 Field Effect Transistor (FET)

Solution Given that

gm ¼ 2:5 mA=V ¼ 2:5  103 A=V;

rd ¼ 500 kX  8RD ¼ 10 kX:

We know that the ac equivalent resistance is given by

RD  rd 10  500
rL ¼ ¼ kX ¼ 9:8 kX
RD þ rd 10 þ 500
¼ 9:8  103 X

Now voltage gain

   
Av ¼ gm  rL ¼  2:5  103  9:8  103
Av ¼ 24:5:

Example 4.4 An FET follows the following relations:

 
VGS
ID ¼ IDSS 1 
VP

IDSS ¼ 8:4 mA VP ¼ 3 V. What is the value of ID for VGS ¼ 1:5 V ? Find gm

at this point.
Solution Drain–source saturation current,

IDSS ¼ 8:4 mA

Pinch-off voltage
Vp ¼ 3 V

Gate–source voltage
VGS ¼ 1:5 V

We know that the drain current is

 2
VGS
ID ¼ IDSS 1
VP

Substituting all the values, ID ¼ 8:4 1  1:5
3 ¼ 2:1 mA.
4.11 Characteristics of MOSFET 215

Transconductance for VGS ¼ 0 is given by

2IDSS 2  8:4
gm 0 ¼ ¼ ¼ 5:6 mA=V or 5:6 mS:
Vp 3

Transconductance,
   
VGS 1:5
gm ¼ gm 0 1  ¼ 5:6 1  ¼ 2:8 mS:
VP 3

Example 4.5 An N-channel JFET has a pinch-off voltage of −4.5 V and

IDSS ¼ 9 mA. At what value of VGS will IDS equal to 3 mA? What is its gm at this
IDS ?
Solution Pinch-off voltage

VP ¼ 4:5 V

Drain–source saturation current

IDSS ¼ 9 mA ¼ 9  103 A

Drain–source current

IDS ¼ 3 mA ¼ 3  103 A

From Shockley’s equation

 rffiffiffiffiffiffiffiffi " rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi#
IDS 3  103
VGS ¼ Vp 1  ¼ 4:5  1  ¼ 1:902 V:
IDSS 9  103

Transconductance gm for IDS ¼ 3 mA mA for which

VGS ¼ 1:902 V
   
2IDSS VGS 2  9  103 1:902
gm ¼ 1 ¼ 1
Vp Vp 4:5 4:5

gm ¼ 2:31 mA=V ¼ 2:31 mS:

Example 4.6 A JFET has VP ¼ 4:5 V, IDSS ¼ 10 mA and IDS ¼ 2:5 mA.
Determine the transconductance.
Solution Drain–source saturation current
216 4 Field Effect Transistor (FET)

IDSS ¼ 10 mA

Pinch-off voltage
Vp ¼ 4:5 V

Drain–source current
IDS ¼ 2:5 mA

From Shockley's equation, drain–source current

 2
VGS
IDS ¼ IDSS 1
VP

or
 rffiffiffiffiffiffiffiffi " rffiffiffiffiffiffiffi#
IDS 2:5
VGS ¼ VP 1  ¼ 4:5 1 
IDSS 10
VGS ¼ 22:5 V

Transconductance
   
2IDSS VGS 2  10  103 2:25
gm ¼  1 ¼ 1 ¼ 2:22 mA=V:
VP VP 4:5 4:5

Example 4.7 An n-channel JFET has IDSS = 10 mA and VP = – 9 V. Determine

the minimum value of VDS for pinch-off region and drain current ID for VGS = – 2 V
in pinch-off region.
Solution Pinch-off voltage,

Vp ¼ 4 V

Gate–source voltage
VGS ¼ 2 V:

Drain–source saturation current,

IDSS ¼ 10 mA ¼ 10  103 A
4.11 Characteristics of MOSFET 217

Drain current
 
VGS 2
ID ¼ IDSS 1 
VP
 
3 2 2
¼ 10  10 1  ¼ 2:5 mA
4

The minimum value of VDS for pinch-off region is equal to VP . Thus, the min-
imum value of VDS

VDSðminÞ ¼ VP ¼ 4 V:

Example 4.8 A data sheet gives these JFET values.

IDSS ¼ 20 mA and Vp ¼ 5 V:

What is the maximum drain current? What is the gate–source cutoff voltage?
Solution For any gate voltage, the drain current has to be in this range

0\ID \20 mA

When the gate voltage is zero, the drain current has its maximum value of
ID ¼ 20 mA.
The gate–source voltage has the same magnitude as the pinch-off voltage but the
opposite sign. Since the pinch-off voltage is 5 V,

VGSðoffÞ ¼ 5 V:

Example 4.9 Suppose a JFET has IDSS ¼ 7 mA and VGSðoffÞ ¼ 3 V: Calculate the
drain current for a gate–source voltage of −1 V.
Solution With equation (i), you can work out the K factor as follows:
 2
K ¼ 1  V VCS ðiÞ
GSðoffÞ Þ

 2
1V
K¼ 1 ¼ ð0:667Þ2 ¼ 0:445
3V

Now, multiply the K factor by IDSS to get the drain current.

218 4 Field Effect Transistor (FET)

ID ¼ 0:445ð7 mAÞ ¼ 3:12 mA:

Example 4.10 In the given figure, the resistor is changed to 3.6 kW. If VGS ¼ 0,
what is the drain–source voltage?
Solution Assume the JFET act as a current source. Since the ground voltage is
zero, the drain current is at its maximum value of 10 mA.
Therefore, the drain–source voltage is

VDS ¼ 10 V  ð10 mAÞð3:6 kXÞ ¼ 26 V

Impossible! The drain voltage current be (–) ve. We have an absurd result, which
means the JFET cannot be operating in the current source region. It must be
operating in the ohmic region.
Here is what to do next. Since the JFET is operating in the ohmic region, we
need to calculate the value of RDS . It equals the pinch-off voltage divided by the
maximum drain current.

4V
RDS ¼ ¼ 400 X:
10 mA

The equivalent circuit for the drain current is given below. The drain–source
voltage can be calculated as follows:

10 V
VDS ¼ ð400 XÞ ¼ 1 V
4 kX
4.11 Characteristics of MOSFET 219

Equivalent circuit

Equivalent circuit
Example 4.11 What is the drain–source voltage in Example 4.10 for
VGS ¼ 2:2 V?
Solution Since VGS has changed from 0 to –2.2 V, there is less drain current, and
it is possible that the JFET no longer operates in the ohmic region. Here is how to
proceed. Assume the JFET is operating as a current source. JST gets the K factor
and the drain current as follows:
 
2:2 V 2
K ¼ 1 ¼ ð0:45Þ2 ¼ 0:203
4V

and
ID ¼ 0:203ð10 mAÞ ¼ 2:03 mA:

Second, the drain–source voltage is

VDS ¼ 10 V  ð2:03 mAÞð3:6 kXÞ ¼ 2:69 V

Third, calculate the proportional pinch-off vol:

VP ¼ ð2:03 mAÞð400 XÞ ¼ 0:812 V:

This voltage separates the ohmic region and the active region when

VGS ¼ 2:2 V. Since a VDS of 2.69 V is greater than a V′P of 0.812 V, the JFET
is operating as a current source. This agrees with the original assumption.
Therefore, the final answer is
VDS ¼ 2:69 V:

Example 4.12 In the given figure, the resistor is changed to 4.7 kΩ. If VGS ¼ 0
what is the drain–source voltage?
Solution Assume the MOSFET acts like a current source. Since the gate vol is
zero, the drain current is 10 mA.
220 4 Field Effect Transistor (FET)

Therefore, the drain–source voltage is

VDS ¼ 20V  ð10mAÞð4:7kXÞ ¼ 27V

Impossible! The drain voltage cannot be (–) ve. We have an absurd result, which
means the MOSFET cannot be operating in the active region. It must be operating
in the ohmic region.
Here is what to do next. Since the MOSFET is operating in the ohmic region, we
need to calculate the value of RDS . It equals the pinch-off vol divided by the
maximum drain current.
4V
RDS ¼ ¼ 400 X:
10 mA

The MOSFET acts like a resistance of 400 W. The total resistance in the drain
circuit is the sum of 400 W and 4.7 kW.
Therefore, the drain–source vol is

20 V
VDS ¼ ð400 XÞ ¼ 1:57 V:
5:1 kX

Example 4.13 In the given figure shown in Example 4.12, what is the drain–
source vol when VGS ¼ þ 1 V?
Solution Assume the MOSFET is operating as a current source. First, get the
K factor and the drain current as follows:
 2
þ1V
K¼ 1 ¼ ð1:25Þ2 ¼ 1:56
4 V

and

ID ¼ 1:56ð10 mAÞ ¼ 15:6 mA:

4.11 Characteristics of MOSFET 221

Second, the drain–source vol is

VDS ¼ 20 V  ð15:6 mAÞð470 XÞ ¼ 12:7 V

Third, calculate the proportional pinch-off vol:

VP0 ¼ ð15:6 mAÞð400 XÞ ¼ 6:24 V

Since VDS is greater than VP0 , the MOSFET is operating as a current source.
Example 4.14 In the given figure, the drain resistor increases to 36 kΩ.
What is the drain–source vol when VGS is 5 V?
Solution

Assume the MOSFET acts as a current source. Since the gate voltage is +5 V,
the drain current is 1 mA. Therefore, the drain–source voltage is

VDS ¼ 20 V  ð1 mAÞð36 kXÞ ¼ 16 V:

Impossible! The drain vol. cannot be –ve. We have an absurd result, which
means the assumption about the current source is incorrect. The MOSFET cannot
be operating in the current source region. It must be operating in the ohmic region.
The MOSFET acts as a resistance of 1 kΩ. The total resistance in the drain
circuit is the sum of 1 and 36 kΩ. Therefore, we can calculate the drain–source vol
to like this:

20 V
VDS ¼ ð1 kXÞ ¼ 0:54 V:
1 kX þ 36 kX

Example 4.15 In the above figure, what is the drain–source voltage when
VGS ¼ 3 V?
222 4 Field Effect Transistor (FET)

Solution Assume the MOSFET is operating as a current source. First, get the
K factor by substituting the given equation (i).
 
VGS  VGSðthÞ 2
K¼ ðiÞ
VGSðonÞ  VCSðthÞ
 
3V  1V 2
K¼ ¼ ð0:5Þ2 ¼ 0:25
5V  1V

and ID ¼ 0:25ð1 mAÞ ¼ 0:25 mA:

Second, the drain–source vol is

VDS ¼ 20 V  ð0:25 mAÞð3:6 kXÞ ¼ 19:1 V:

Example 4.16 Mathematical derivation.

In the enhancement mode MOSFET, the basic equation of drain current was
given as
 2
ID ¼ K VGS  VGSðthÞ ðiÞ

Solution The derivation of this basic formula is given in engineering textbooks on

FETs. Here we want to show how this equation is rearranged into the more useful
form

ID ¼ KIDðonÞ ðiiÞ

where
 2
VGS  VGSðthÞ
K¼ ðiiiÞ
VGSðonÞ  VGSðthÞ

To begin, substitute IDðonÞ and VGSðonÞ into equation (i) to get

 2
IDðonÞ ¼ K VGSðonÞ  VGSðthÞ

Solve for K to get

IDðonÞ
K¼ 2 :
VGSðonÞ  VGSðthÞ

Substitute this K into equation (i) to get

4.11 Characteristics of MOSFET 223

IDðonÞ  2
ID ¼  2 VGS  VGSðhÞ
VCSðonÞ  VGSðthÞ

Now, define
 2
VGS  VGSðthÞ
K¼ :
VGSðonÞ  VGSðthÞ

which means
ID ¼ KIDðonÞ :

Example 4.17 A 2 M 5457 has IDSS = 5 mA and gm 0 = 5000 m mho. What is

the value of ID for VGS ¼ 1 V? What is the gm for this drain current?
Solution From width equation (i) to get an accurate value of VGSðoffÞ

VGSðoffÞ ¼ 2I
gm0
DSS

2ð5 mAÞ ðiÞ

¼ 5000 l mho
¼ 2 V

To get the drain current, first calculate the K factor with equation (ii)
 2
K ¼ 1  VGSðoffÞ
VGS
 2 ðiiÞ
K ¼ 1  12 ¼ ð0:5Þ2 ¼ 0:25

Then
ID ¼ 0:25ðtmAÞ ¼ 1:25 mA:

Next use equation (iii) to calculate gm at VGS ¼ 1 V:


gm ¼ gm0 1  VGSðoffÞ
VGS
 ðiiiÞ
¼ ð5000 lmhoÞ 1  12V V ¼ 2500 lmho

As you see, gm is 2500 m mho when ID is 1.25 mA.

Example 4.18 If a JFET has gm = 2500 m mho, what is the ac drain current for
VGS = 1 mV ? Compare this to a tripolar transistor width a gm of 50,000 µ mho.
Solution In the given figure, the current source has a value of gm VGS . Therefore,
an ac input of 1 mV produces
224 4 Field Effect Transistor (FET)

id ¼ ð25000 lmhoÞð1 mVÞ ¼ 2:5 lA

The same ac input voltage to a tripolar transistor would produce an ac collector

current of

ic ¼ ð50; 000 lmhoÞð1 mVÞ ¼ 50 lA:

This bipolar output current is 20 times greater than the JFET output current.
Given the same load resistances, a bipolar amplifier would produce 20 times more
output vol than the JFET.
Example 4.19 If gm = 2500 m mho for the JFET of given circuit, what is the ac
output voltage?
Solution The ac drain resistance is

rd ¼ 3:6 kXk10 kX ¼ 2:65 kX

The voltage gain is

A ¼ ð2500 lmhoÞð2:65 kXÞ ¼ 6:63

The input impedance of the amplitude is

Zin ¼ 1 MX

We are ignoring the RGS of the JFET because it is usually in the hundreds of
megaohm.
4.11 Characteristics of MOSFET 225

The generator has an internal resistance of 47 kΩ. Therefore, some of the signal
voltage is dropped across this 47 kΩ. But not much, the ac voltage at the gate is
found with ohm’s law.

1 mV
Vin ¼ ð1 MXÞ ¼ 0:955 mV
47 kX þ 1 MX

The ac output voltage equals the V gain time the input voltage

Vout ¼ 6:63ð0:955 mVÞ ¼ 6:33 mV

Example 4.20 If gm = 2500 m mho for the source follows of in figure, what is the
ac output voltage?
Solution

The input voltage drives the gate, and the output voltage appears at the source.
The ac source resistance is
226 4 Field Effect Transistor (FET)

rs ¼ 1 kXk1 kX ¼ 500 X

Width equation, A ¼ 1 þgmgrmSrS , the V gain is

ð2500 lmhoÞð500 XÞ
A¼ ¼ 0:556
1 þ ð2500 lmhoÞð500 XÞ

The input impedance of the source full is

Zin ¼ 10 MX

The generator has an internal resistance of 47 kΩ. Therefore, almost none of the
ac voltage is dropped across the generator resistance:

1 mV
vi ¼ ð10 MXÞ ¼ 0:995 mV
47 K þ 10 MX

The ac output voltage equals the V gain times the input voltage

vo ¼ ð0:556Þð0:995 mVÞ ¼ 0:553 mV:

Example 4.21 JFET shunt switch like in the figure has RD ¼ 10 kX, IDSS ¼ 10 mA
and VGSðoffÞ ¼ 2 V.If vi ¼ 10 mV peak to peak, what does vo equal when VGS ¼
0? When VGS ¼ 5 V?
Solution Calculate the ideal value of RDS as follows:

2V
RDS ¼ ¼ 200 X
10 mA

When VGS ¼ 0, the circuit acts like the equivalent circuit of given circuit width
ohm’s law.
4.11 Characteristics of MOSFET 227

10 mV
vo ¼ ð200 XÞ
10 kX þ 200 X
¼ 0:196 mV

Thus, the equivalent circuit is as follows:

When

VGS ¼ 5 V; the JFET is like an open circuit.

In figure, visualize the 200 V increasing to input. You can see that

vo ¼ vi ¼ 10 mV
Summary
1. JFET Basics: The junction field effect transistor (JFET) has source–gate and
drain terminals. It has two built-in diodes—the gate–source diode and the gate–
drain diode. These diodes will conduct if these are forward biased with more
than 0.7 V. Both the gate–source diode and gate–drain diode are reverse biased
for normal operation. It has input resistance which approaches infinity, but it has
less voltage gain than a bipolar transistor. Some additional details are as follows:
(i) JFET can be used as a voltage-controlled resistor as it has a unique
sensitivity of the drain-to-source impedance to the gate-to-source voltage.
(ii) The maximum current IDSS occurs when VGS = 0 V; and the minimum
current occurs at pinch-off defined by VGS = VP.
(iii) The relationship between the drain current and gate-to-source voltage is
nonlinear defined by Shockley’s equation.
2. Input and Transfer Characteristics of JFET: The drain characteristics are
similar to those of a BJT, except that VGS is the controlling input rather than IB.
The transconductance characteristics are the plot of drain current versus gate
voltage. The curve is nonlinear, part of a parabola and also called a square law
curve.
3. MOSFET Basics: The metal–oxide semiconductor field effect transistor
(MOSFET) has source, gate and drain terminals. The gate is electrically insu-
lated from the channel. Due to this, the dc input resistance is even higher than
that of a JFET. Some additional details are as follows:
228 4 Field Effect Transistor (FET)

(i) MOSFETs should always be handled with additional conduct and the static
electricity that exists in places we might least expect. Any shorting
mechanism between the leads of the device should not be removed until it
is installed.
(ii) A complementary MOSFET (CMOS) device uses a unique combination of a
P-channel and an N-channel MOSFET with single set of external leads. It
has very high input impedance, fast switching speeds and low operating
power levels.
4. Depletion Mode MOSFET: Normally, the depletion mode MOSFET is ON
when VGS is zero. It has drain curves and equivalent circuits similar to JFET
except that MOSFET can operate with positive as well as negative gate voltages.
5. Enhancement Mode MOSFET: It is normally OFF when the gate voltage is
zero. A positive sufficient gate voltage forms it ON. The voltage at which this
turns ON is the threshold voltage. It can act as a current source or as a resistor.
The transfer characteristics of an enhancement type MOSFET are not defined by
Shockley’s equation but rather by a nonlinear equation controlled by the
gate-to-source voltage, the threshold voltage and a constant k defined by the device
used. The plot of ID versus VGS rises exponentially with increasing values of VGS.
6. The arrow in the symbol of N-channel JEFTs or MOSFETs joins into the center
of symbol, whereas those of a P-channel device will always point out of the
center of the symbol.
7. Important Equations:
(i) Gate cutoff and pinch-off.

VGS ðoffÞ ¼ VP

(ii) Drain—source resistance.

VP
RDS ¼
IDSS

(iii) Drain current as a function of gate voltage:

ID ¼ kIDSS

swhere  2
VGS
k¼ 1
VGS off

k value is between 0 and 1.

4.11 Characteristics of MOSFET 229

(iv) Proportional pinch-o¢ ff

VP 0 ¼ ID RDS

If VDS is greater¢ than VP0 , the JFET acts as a current source; and if VD is less
than VP0 , the JFET acts like a resistor.
(v) Enhancement—mode drain current for MOSFET

ID ¼ kIDOH

Where
 2
VGS  VGSðhÞ
k¼
VGSðonÞ  VGSðthÞ

for
VGS [ VGS ðthÞ:

(vi) AC drain resistance

DVDS
rd ¼ (from drain-to-source)
DID

(vii) Amplification Factor:

DVDS
l¼ :
DVGS

Exercises
1. Explain basic construction of a JFET with illustrative diagrams.
2. Describe principle of working of a JFET with illustrative diagrams.
3. What is concept of pinch-off? Explain with diagrams.
4. Explain maximum drain saturation current. Where is it applicable?
5. Describe input and transfer characteristics of JFET and characteristic
equation.
6. Give CG, CS and CD configurations of JFET and describe their important
aspects.
7. Describe fixed biasing of JFET amplifier.
8. Describe self-biasing of JFET amplifier.
9. Explain basic construction of a JFET with illustrative diagrams.
10. What is depletion-type MOSFET? Explain with diagrams.
11. Explain enhancement-type MOSFET with diagrams.
230 4 Field Effect Transistor (FET)

12. Describe operation of MOSFETs with diagram. Give its characteristics.

13. The data sheet of a certain JFET indicates that IDSS is equal to 15 mA and
VGSðoffÞ is equal to −5 V. Find the drain current for VGS equal to 0 V, –1 volt
and −4 volt. 
14. A JFET has parameters of VGSðoff equal to −20 V and IDSS equal to 12 mA.
Plot the transconductance curve for the device using VGS values of 0 V, −10 V,
−15 V and −20 V.
15. A 2N5486 JFET has values of VGSðoffÞ equal to −2 V to −6 V and IDSS is
equal to 8–20 mA. Plot the minimum and maximum transconductance curves
for the device.
16. The following information is included on the data sheet for an N-channel JFET:

IDSS ¼ 20 mA; VP ¼ 8 V; and gm0 ¼ 5000 ls

Find the values of the drain current and transconductance at VGS ¼ 4 V.

17. The data sheet for a certain enhancement-type MOSFET reveals that IDðonÞ ¼
10 mA at VGS ¼ 12 V and VGSðthÞ ¼ 3 V. Is this device P-channel or
N-channel? Find the value of ID, when VGS ¼ 6 V.
18. Sketch the transfer curve defined by IDSS ¼ 12 mA and Vp ¼ 6 V using
Shockley’s equation.
19. Sketch transfer characteristics for n-channel depletion-type MOSFET with
IDSS ¼ 10 mA and Vp ¼ 4 V.
20. A data sheet gives these JFET values:

IDSS ¼ 20 mA and VP ¼ 5 V:

Find the dc resistance of the JFET in ohmic region.

21. In the figure given below, what is the drain–source voltage when VGS is zero?
4.11 Characteristics of MOSFET 231

22. An n-channel JFET has IDSS ¼ 8 mA and VP ¼ 5 V. Find the minimum

value of VDS for pinch-off region and the drain current IDS for VGS ¼ 2 V in
the pinch-off region.
Chapter 5
Operational Amplifier (Op-Amp)

5.1 Introduction

Operational Amplifier is abbreviated as op-amp. Op-amp is an amplifier which

could be easily modified by external circuitry to perform mathematical operations—
addition, scaling, integration, etc. The advance of solid-state technology has made
op-amp highly reliable, miniaturized and consistently predictable in performance.
Op-amps are building blocks in basic amplification, signal conditioning, active
filters, function generators and switching circuits.

5.2 Op-Amp Integrated Circuit

Op-amps are now available in hundreds of types. A very good all-round performer
is the popular LF411 (“411” for short), originally introduced by National
Semiconductor. It is packed similar to all op-amps, and its looks are shown in
Fig. 5.1.
An op-amp IC 411 is a piece of silicon containing 24 transistors (21 BJTs,
3FETs, 11 resistors and 1 capacitor). The pin configurations are shown in Fig. 5.2.
The dot in the corner or notch at the end of the package identifies the end from
which to begin counting the pin numbers. As with most electronic IC packages,
pins are run counted clockwise, view counted from the top. The “offnull” terminals
(also known as “balance” or “trim”) have to do with correcting externally the
asymmetries that are unavoidable when making op-amp.

© The Author(s), under exclusive license to Springer Nature Switzerland AG 2022 233
O. N. Pandey, Electronics Engineering,
https://doi.org/10.1007/978-3-030-78995-4_5
234 5 Operational Amplifier (Op-Amp)

Fig. 5.1 Op-amp integrated circuit

Fig. 5.2 Op-amp 411 pin configurations (top-view)

5.3 Op-Amp Symbol

Basic form of operational amplifier is shown in Fig. 5.3. It shows the complete
triangular schematic symbol showing the pin connections to different points. Pin 7
connects to +VCC, and pin 4 connects to −VCC. Pin 6 connects to the op-amp output.
Pin 2 and Pin 3 connect to the op-amp inputs. Pin 2 is inverting (−) input, and pin 3
is non-inverting (+) input.

Fig. 5.3 Basic operational

amplifier
5.3 Op-Amp Symbol 235

Fig. 5.4 Simplified symbol

of op-amp

Figure 5.4 shows the simplified symbol of op-amps. This symbol is in most of
the representation in various circuits.
Figure 5.4 gives the difference, vd ¼ v1  v2 , between two input signals,
exhibiting the open-p gain
v
AOL = 0 ð5:1Þ
vd

Terminal 1, labeled with minus sign, is inverting input; signal v1 is amplified in

magnitude and appears phase inverted at the output. Conversely, terminal 2, labeled
with plus sign, is the non-inverting input; output due to v is phase preserved. In
magnitude, open-loop voltage gain in op-amp ranges from 104 to 107. The maxi-
mum magnitude of output voltage from an op-amp is called saturation voltage; this
voltage is approximately 2 V smaller than power supply voltage. In other words, the
amplifier is linear over the range:

ðVcc  2Þ\v0 \ðVcc  2Þ

5.4 Concept of Ideal Op-Amp

The common IC op-amp has a very high gain. Op-amps are used in analog linear
amplification systems and digital logic systems. The properties common to all
op-amps are as follows:
(i)) An inverting input.
(ii)) A non-inverting input.
(iii)) A high input impedance, normally assumed infinite at both inputs.
(iv)) A low output impedance.
(v)) A large voltage gain when operating without feedback, typically 105.
(vi)) Voltage gain remains constant over a wide frequency range.
(vii)) Almost no drift due to ambient temperature change; hence, the direct
voltage output is zero when there is no input signal.
(viii)) Good stability.
236 5 Operational Amplifier (Op-Amp)

5.5 Inverting Amplifier

Figure 5.5 shows a basic invertin amplifier circuit having two resistors R1 and Rf
to an op-amp. Normally, the power supply connections to op-amp are not shown.
The open-loop gain of the op-amp is taken as A. Hence, the output voltage
v0 ¼ Avi .

) vi  v ¼ ii R1

Now, if input impedance of op-amp is very high, then i ffi 0.

) ii ¼ if

We also know that if ¼ vRi v

1

) vRi v1
¼  v0Rv
f
¼ vv
Rf .
0

If the input is exactly out of phase with the input voltage, the op-amp being in its
inverting mode, then we get:

v0 ¼ Av
v0
or v ¼ 
A
v1 þ vA0  vA0  v0
) ¼
R1 Rf
v0 v0 R1 R1
vi þ ¼    v0
A A Rf Rf

Normally, R1 and Rf are of the same range of resistance say R1 = 100 k and
Rf = 1 M, and A ¼ 105 .
∴ vA0 and vA0  RR1f can be neglected.
∴

R1
v1 ¼ v0 ð5:2Þ
Rf

Fig. 5.5 Inverting amplifier

5.5 Inverting Amplifier 237

∴ Overall gain,
Rf
∴ Overall gain, AV = – ð5:3Þ
R1

Normally, in practice, the non-inverting input is earthed through R2 which

minimizes the worst effects of the offset voltage and thermal drift. The offset
voltage is the voltage difference between the op-amp input terminals required to
bring the output to zero. Further, the output often includes a resistance of about 50–
200 Ω in order to give protection in the event of load being short circuited.

5.6 Non-inverting Amplifier

Non-inverting amplifier circuit is shown in Fig. 5.6. It shows two common forms
which are identical electrically, but the conversion from one diagram layout to the
other can give difficulty.
Due to the very high input resistance, the input current is negligible; therefore,
the voltage drop across R2 is negligible.

) vi ¼ v:

Using form of Fig. 5.6b, it can be seen that

R1
v¼ v0
R1 þ Rf
R1
) v1 ¼ v0 ð5:4Þ
R1 þ Rf
v0 Rf
) Av ¼ ¼ 1 þ
vi R1

Fig. 5.6 Non-inverting amplifier circuit

238 5 Operational Amplifier (Op-Amp)

5.7 Unity Gain or Voltage Follower Amplifier

The unity gain amplifier circuit is shown in Fig. 5.7. It has voltage gain of 1, and
the output is in phase with the input. It also has an extremely high input impedance,
leading to use as an intermediate stage (buffer) amplifier to prevent a small load
impedance from loading the input.
By writing loop equation from the circuit of Fig. 5.7, we get


1
vi ¼v0  vd ¼ v0 1 
A
ð5:5Þ
or vi ¼v0 as A is very high:
) v0 ¼vi

5.8 Op-Amp as Adder or Summer

An adder circuit is shown in Fig. 5.8 . The three inputs v1 ,v2 and v3 have series
resistors R1 , R2 and R3 , respectively. The currents are given by

Fig. 5.7 Unity gain amplifier

Fig. 5.8 Op-amp as an adder

5.8 Op-Amp as Adder or Summer 239

v1  v v2  v v3  v
i1 ¼ ; i2 ¼ and i3 ¼
R1 R2 R3
v1  v v2  v v 3  v
i1 ¼ þ þ
R1 R2 R3

and if ¼ v0Rv
f
as i  0
Normally, v is very small as compared to other voltages, hence, we get
v1 v2 v3
i1 ¼ ; i2 ¼ and i3 ¼
R1 R2 R3

We know that

if ¼i1 þ i2 þ i3 as i ffi 0 :
v0 v1 v2 v3
) ¼ þ þ
Rf R1 R2 R3

IfRf ¼ R1 ¼ R2 ¼ R3 then we get

v0 ¼ v1 þ v2 þ v3

or

v0 ¼  ð v1 þ v2 þ v3 Þ ð5:6Þ

Thus, apart from phase reversal, the output voltage is the sum of input voltages.

5.9 Op-Amp as Difference Amplifier

Op-amp usage as differential amplifier is quite common. Differential amplifier

amplifies the difference between two signals as op-amp is a linear amplifier, and the
output is proportional to the difference in signal between two input terminals.
Figure 5.9 shows differential amplifier circuit.
If v2 ¼ 0, then the circuit becomes as shown in Fig. 5.10. Circuit becomes
inverting type.
In this case, voltage output is

R2
v0 ¼  v1
R1

Now, v1 ¼ 0, the + ve circuit becomes as shown in Fig. 5.11.

240 5 Operational Amplifier (Op-Amp)

Fig. 5.9 Differential

amplifier circuit

Fig. 5.10 Inverting amplifier

with v2 ¼ 0

Fig. 5.11 Non-inverting

amplifier with v1 ¼ 0
5.9 Op-Amp as Difference Amplifier 241

In this case, circuit becomes inverting type, hence, we get


v0 R2
¼ A ¼ 1þ
vi 2 R1


R2
or v0; ¼vi2 1 þ
R1

we also know that


R4
vi2 ¼ v2
R3 þ R4



R4 R2
) v01 ¼  v2  1 þ
R3 þ R4 R1

The value of full output is given by

v0 ¼v01 þ v01




R2 R4 R2
or v0 ¼D v1 þ  v2  1 þ
R1 R3 þ R4 R1
 
R4

R2 R3 R2
¼   v1 þ    v2  1 þ
R1 1 þ R4 R1
R3

In case, R2
R1 ¼ RR43 , we get

R2

R2 R2
v0 ¼   v1 þ 
R1
  v2  1 þ
R1 1 þ RR21 R1

R2 R2
or v0 ¼   v1 þ  v2
R1 R1
R2
or v0 ¼ ð v2  v1 Þ
R1

Thus, a differential amplifier amplifies the difference between two voltages.

5.10 Subtractor

It subtracts one voltage from other. Consider Fig. 5.12 wherein

R1 ¼ R2 ¼ R3 ¼ R4 ¼ R.
242 5 Operational Amplifier (Op-Amp)

Fig. 5.12 Subtractor circuit

Using differential amplifier principle, we get

R2
v0 ¼ ðv2  v1 Þ
R1
or v0 ¼v2  v1 as R1 ¼ R2 ¼ R

5.11 Differentiator

A differentiating circuit is shown in Fig. 5.13.

From the circuit of the figure, we know

dV
i1 ¼ c
dt

Fig. 5.13 Differentiator

circuit
5.11 Differentiator 243

But iin ¼ 0 for an op-amp, hence, we get

dV
v0 ¼  if R ¼ is R ¼ RC
dt
dV
or v0 ¼  RC
dt

i.e., output voltage is differentiation of input voltage.

5.12 Integrator

An integrator circuit is shown in Fig. 5.14.

Thecurrent i ¼ Rv Rsince ii ¼ 0V
R
) v0 ¼  1c if dt ¼  1c idt

By substituting i ¼ Rv , we get
Z
1
v0 ¼  Vdt
RC

Thus, the output is integral of the input.

Fig. 5.14 Integrator circuit

244 5 Operational Amplifier (Op-Amp)

5.13 Op-Amp Parameters

5.13.1 Input Offset Voltage

Ideal amplifier gives zero output against zero input. In practice, there has to be a
little voltage present at input, to get output as zero.
Figure 5.15 shows an amplifier wherein input voltage has some nonzero value to
get zero output.

Thus, vi0 = vdc1 – vdc2

5.13.2 Input Offset Current

The algebraic sum of difference between two bias current inputs must be zero.
Demonstration circuit for input offset current is shown in Fig. 5.16

The offset current, I i0 = I B1 − I B2

It is used as an indicator of mismatching between two currents.

Fig. 5.15 Demonstration of

input offset

Fig. 5.16 Demonstration of

input offset current
5.13 Op-Amp Parameters 245

5.13.3 Bias Current

Figure 5.16 shows demonstration of bias currents as well. Bias current is the
average of current that flows between two terminals.

bias current, IB = I B1 + I B2
2

5.13.4 Slew Rate

It is the maximum rate of change of output voltage with respect to time. It is given
in V/µs.

dvo
SR = = Vp V/μs
dt max


dvo  2pfVp
) ¼ V=ls
dt max 106

Where f = input frequency

Vp = peak value of output voltage.

5.13.5 Common-Mode Rejection Ratio (CMRR)

This is a figure of merit for a differential amplifier, and it is defined as follows:

differential voltage gain

CMRR ¼
common mode voltage gain

or CMRR ¼ AAcmd

where

Ad = differential voltage gain.

Acm = common-mode voltage gain.

246 5 Operational Amplifier (Op-Amp)

Fig. 5.17 Common-mode

circuit

A common-mode circuit is shown in Fig. 5.17

Common voltage in applied to both input terminals,
In practice, Ad is very large and Acm is very small; hence, CMRR is very large
value.
Solved Examples
Example 5.1 For a given op-amp, CMRR = 105 and differential gain Ad = 105,
determine the common-mode gain Acm of the op-amp.
Solution Since CMRR is defined as

Ad
CMRR ¼
Acm

Differential gain
Common mode rejection ratio ¼
Common mode gain

given that CMRR = 105

and Ad ¼ 105.
therefore Acm ¼ CMRR
Ad
105 ¼ 1.
¼ 105

Example 5.2 The output voltage of a certain op-amp circuit changes by 20 V in 4

microsec. What is slew rate?
Solution The slew rate,

dv0 20V
SR ¼ ¼ ¼ 5V=ls:
dt 4ls

Example 5.3 Design a non-inverting amplifier circuit that is capable of providing

a voltage gain of 10. Assume an ideal operational amplifier. (Resistor should not
exceed 30 kΩ).
Solution Gain AF is given as
5.13 Op-Amp Parameters 247

R2
AF ¼ 1 þ
R1

given that AF ¼ 10
R2
10 ¼ 1 þ
R1
R2
¼ 9 or R2 ¼ 9R1
R1

Taking R1 ¼ 1 kX
so that R2 ¼ 9 kX
) AF ¼ 1 þ R2
R1
9
AF ¼ 1 þ ¼ 10
1
AF ¼ 10

Figure shows the required non-inverting amplifier.

Example 5.4 A 5 mV, 1 kHz sinusoidal voltage is applied at the input of an
op-amp integrator for which R = 100 kΩ and C = 1 µf. Calculate the output voltage.
Solution: Given that
vi ¼5 sin x t mV
¼ 5 sin 2pxt mV
¼ 5 sin 2000pt mV

We know that the output of an integrator is

Zt Zt
1 1
vo ¼ vi dt ¼ 5 sin 2000p tdt
RC 100  103  1  106
0 0

Zt  t
1 5 cos 2000pt
vo ¼ 5 sin 2000ptdt ¼ 10
0:1 2000p 0
0
 
cos 2000pt  1 1
vo ¼ 50 ¼ ðcos 2000pt  1ÞmV:
2000p 40p

Example 5.5 Show that the output of the inverting integrator of given figure is the
time integral of the input signal, assuming the op-amp is ideal.
248 5 Operational Amplifier (Op-Amp)

Solution We know that for an op-amp

v0
A¼
vid

Assuming op-amp is an ideal one:

v0 v0
A ffi 1; vid ¼ ¼ ¼0
A 1
i.e:; vid ¼ 0:
i.e:; v1  v2 ¼ 0 or v1 ¼ v2 ;

Op-amp is ideal, and it will draw zero current.

Therefore, iR ¼ iC from figure the value of

v1  v2
iR as ¼ iC But iC ¼ 0:
R
vi  0 vi
) ¼ iC or iC ¼ :
R R

But iC = current through capacitor.

We know that the current through a capacitor may be expressed as
5.13 Op-Amp Parameters 249

dvc
iC ¼ C
dt

Therefore, C ddvtc ¼ vRi (here vC is the V across C)

given as vc ¼ v2  v0 .
Substituting the value of vC , we get

d vi
C: ½v2  v0  ¼ But v2 ¼ 0
dt R

Hence; C: ddt ½0  V0  ¼ vRi

R ¼ C: dt ðv0 Þ:
vi d
or

Integrating both sides of above equations, w.r.t. we get

Zt
vi
dt ¼ C:ðv0 Þ þ A
R
0
Zt
1
v0 ¼ vi dt þ A ðiÞ
RC
0
Zt
1
v0 ¼ vi dt þ A
RC
0

where A is the integration constant and is proportional to the value of the output
voltage v0 at time t = 0 s. From Eq. (i), it is clear that the output voltage v0 is equal
to the integration of input voltage vi .
Example 5.6 In the given figure, the variable resistance varies from zero to
100 kW. Find out the maximum and the minimum closed-loop voltage given.
Solution The given circuit is a non-inverting op-amp amplifier
250 5 Operational Amplifier (Op-Amp)

Therefore,

vo RF
AF ¼ ¼ 1þ
vi R1
 
RF
or v0 ¼ vi 1 þ
R1
But for RF ¼ 0; R1 ¼ 2 kX

Hence using (i), we get

 
0
vo ¼ vi 1 þ
R1

vo ¼ vi ð1 þ 0Þ ¼ vi

Then minimum closed-loop voltage gain

AFmin ¼ vvoi ¼ 1
Similarty for RF ¼ 100 kX; R1 ¼ 2 kX

Therefore, using (i), we get

 
100
vo ¼vi 1 þ ¼ vi :51
2
vo
vo ¼51vi or ¼ 51
vi

Then maximum closed-loop voltage gain

vo
AFmax ¼ ¼ 51:
vi

Example 5.7 Find an expression for the output v0 of the amplifier circuit of given
figure. Assume op-amp is ideal. What mathematical operation does this circuit
perform?
5.13 Op-Amp Parameters 251

Solution Making vB ¼ 0, we have

vR  R vA
V2 ¼ ¼
RþR 2

Let vB ¼ 0,the value

 of v0 will be v01 .
then v01 ¼ 1 þ R1 v2 .
R2

 
v0 1 ¼ 1 þ R2 vA
[∵ It is a non-inverting amplifier].
R1 2


R 2 vA
or v01 ¼ 1 þ ðiÞ
R1 2

Similarly, making vA ¼ 0, we have

 
R2 vB
v02 ¼ 1 þ ðiiÞ
R1 2

Applying principle of superposition, the output voltage v0 of amplifier will be

vo ¼v01 þ v02

  
R 2 vA R 2 vB
¼ 1þ þ 1þ
R1 2 R1 2
 
1 R2
or vo ¼ 1 þ ð vA þ vB Þ
2 R1

From above equation, it is clear that the given circuit performs the mathematical
operation of a non-inverting adder.
Example 5.8 For difference mode, gain of an amplifier is A = 2000 and
CMRR = 10,000. Calculate output voltage V out when v1 ¼ 1:0 mV and
v2 ¼ 0:9 mV.
252 5 Operational Amplifier (Op-Amp)

Solution Given that

v1 ¼ 1:0 mV; v2 ¼ 0:9 mV

Difference vol vd ¼ v1  v2
vd ¼ 1:0  0:9 ¼ 0:1 mV

Also, common-mode voltage will be

v1 þ v2 1:0 þ 0:9
vc ¼ ¼ ¼ 0:95 mV
2 2

Difference voltage gain A ¼ 2000.

and CMMR ¼ 10; 000.
The output voltage is expressed as
 
1 vC
vo ¼ Avd 1 þ
CMRR vd

Substituting all the values, we get

 
1 0:95
vo ¼ 2000  0:1 mV 1 þ 
10:000 0:1

We get

vo ¼ 200:19 mV:

Example 5.9 Figure shows an op-amp. Obtain the value O/P voltage in stea-
dy-state condition where (i) switch S is open and (ii) switch S is closed.
Solution Case (i) when switch S is open, then RF ¼ 1 þ 1 ¼ 2 kX.
5.13 Op-Amp Parameters 253

Therefore, output voltage

RF
vo ¼  vi 
R1
2kX
¼ 1 
1kX
vo ¼  2 volt

Case (ii) when the switch S is closed, then the impedance at the feedback circuit
will be

R3 R3 þ R2 ð1 þ jxc R3 Þ
ZF ¼ þ R2 ¼
1 þ jxcR3 1 þ jxcR3

Therefore,

ZF R3 þ R2 ð1 þ jxcR3 Þ
AF ¼ ¼
R1 ð1 þ jxcR3 ÞR1

Now, since the gain at the steady-state corresponds to dc or low frequency,

therefore neglecting jx terms, we get

R3 þ R2 1 kX þ 1 kX
gain AF ¼  ¼ ¼ 2:
R1 1 kX

Hence, the output voltage ve ¼ AF vi ¼ 2V.

Example 5.10 An op-amp has feedback resistor R5 ¼ 12 kX and the resistors in
the Input sides are R1 ¼ 12 kX, R2 ¼ 2 kX and R3 ¼ 3 kX. The corresponding inputs
are vh ¼ þ 9V; vh2 ¼ 3V and vts ¼ 1V. Non-inverting terminal is grounded.
Calculate the output voltage.
Solution Given

RF ¼12 kX; R1 ¼ 12 kX; R2 ¼ 2 kX and R3 ¼ 3 kX

v1 ¼9V; v2 ¼ 3V and v3 ¼ 1V

Output voltage
 
v1 v2 v3
ve ¼ RF þ þ
R1 R2 R3
 
9 2 1
¼ 12 kX þ þ
12 kX 2 kX 3 kX
254 5 Operational Amplifier (Op-Amp)

vo ¼ 9 þ 12 þ 4 ¼ 7V:

Example 5.11 Realize a circuit to obtain v0 ¼ 2v1 þ 3v2 þ 4v3 using operational
amplifier. Use minimum value of resistance as 10 kΩ.
Solution For an operational amplifier, we have
 
RF RE RF
vo ¼  v1 þ v2 þ v3
R1 R2 R3

Comparing the above expression with the given expression for the output, i.e.,
vo ¼ 2v1 þ 3v2 þ 4v3
We have RRF1 ¼ 2; RRF2 ¼ 3 and RRF3 ¼ 4.
Resistance R3 will be of minimum value of 10 kΩ.

Thus RF ¼ 4R3 ¼ 4  10 ¼ 40 kX
RF 40
R2 ¼ ¼ ¼ 13:33 kX
3 3
RF 40
R1 ¼ ¼ ¼ 20 kX
2 2

Example 5.12 Given figure shows a non-inverting op-amp summer with v1 ¼ 2V

and v2 ¼ 1V Calculate the output voltage vo .
Solution According to superposition theorem, we have

v0 ¼ v00 þ v000

when v00 ′ is the output produced by v1 of + 2 V.

and v00 ′ is the output produced.
by v2 ¼ 1V.
When v2 ¼ 1V is made zero, input at non-inverting I/P terminal will be
5.13 Op-Amp Parameters 255

RkR
vs1 ¼v1 
R þ ðRkRÞ
R=2
¼2  ¼ 2=3V
R þ R=2
   
RF 2 2R
v00 ¼vs1 1 þ ¼ 1þ ¼ 2V
R 3 R

When v1 ¼ 2V is made zero, we have

R1 kR
vs2 ¼v2 
R þ ðR1 kRÞ
R=2 1
¼1 ¼ V
R þ R=2 3
 
RF
and v000 ¼vs2 1 þ
R
 
1 2R
¼ 1þ ¼ 1V
3 R

Hence, O/P voltage v0 ¼ v00 þ v000

¼ 2 þ ð1Þ ¼ 1V:

Example 5.13 If the non-ideal op-amp of the circuit of following figure has an
open-loop gain.

Aoh ¼ 104 : Find v0

Solution It is an inverting op-amp because input is applied at the inverting

terminal while other terminal is grounded.
256 5 Operational Amplifier (Op-Amp)

vid ¼ v0  Eb v0 ¼ AaC  vMd

¼ AoL ðv0  Eb Þ
Aor
v0 ¼ Eb
1  Aor
104
¼
1  ð104 Þ
½v0 ¼ 0:99Eb :

Example 5.14 The output voltage of the summer is shown below. Calculate the
value of feedback resistance.
Solution The output of a summer circuit is given by

 
RF RF RF
v0 ¼ v1 þ v2 þ v3
R1 R2 R2
 
v1 v2 v3
¼RF þ þ
R1 R2 R3
 
0:1 1 0:1
2:4 ¼RF þ þ
10  103 10  103 50  103
5

2:4 ¼RF 10 þ 105 þ 0:2  105

2:4
RF ¼
2:2  105
RF ¼1:009  105 ¼ 100:9 k

Example 5.17 Design a circuit to give a weighted average 3x þ 2y þ 6z where x, y and

z are input voltages. What input resistors do you need if the feedback resister is
60 k?
5.13 Op-Amp Parameters 257

Solution Let v1 ¼ x; v2 ¼ y; v3 ¼ z, then the output is

 
Rf Rf Rf
v0 ¼  v1 þ v2 þ v3
R1 R2 R3
 
60kX 60kX 60kX
¼ xþ yþ z
R1 R2 R3
hx y zi
¼ þ þ
3 2 6
60 kX x 60 kX y 60 kX z
) x¼ ; y¼ ; z¼
RI 3 R2 2 R3 6

• R1 ¼ 180 X; R2 ¼ 120 X; R3 ¼ 360 X.

Here input resistances are needed; if R1 ¼ 180 X, R2 ¼ 100 X and R3 ¼ 36 X,
then feedback resistance Rs = 60 X.
Example 5.18 For an inverting amplifier in the given figure, R1 ¼ 1 X and
Rf ¼ 100 kX. Assuming an ideal amplifier, determine (i) the voltage gain, (ii) input
impedance and (iii) the output impedance.
Solution For the ideal inverting op-amp, we have

Rf
Vgain ¼
R1
 
100 kX

1 kX

Since point A is in ground potential virtually, therefore, the impedance zin ¼

R1 ¼ 1kQ and the output impedance of the circuit equal the output impedance of
the operational amplifier.
Here output impedance of op-amp is zero.

)2out ¼ 0
Example 5.19 A non-inverting amplifier in given figure is to be applied with a
gain of 1.5 of R1 ¼ 4 kX, what value of Rf should be used?
258 5 Operational Amplifier (Op-Amp)

Solution We know that

Vgain of the non-inverting amplifier

v0 Rf
¼1 þ
v1 R1


v0 Rf
1 ¼
v1 R1


v0
)Rf ¼R1 1
v1
¼ 4 kXð1:5  1Þ
¼ 4 kXð0:5Þ ¼ 2:0 kX

Example 5.20 Find the output voltage for the inverting summing circuit of given
below for R1 ¼ 5 kX, R2 ¼ 3 kX, Rf ¼ 5 kX, V1 ¼ 5 sin xt, V2 ¼ 6 sin xt and
U3 ¼ 5 sin xt.

Solution The output voltage of an inverting summing circuit with three I/P is
given by
 
Rf Rf Rf
v0 ¼ v1 þ v2 þ v3
R1 R3 R2
5.13 Op-Amp Parameters 259

Using the value given, then we get


5 6 5
v0 ¼  sin xt þ  6 sin xt þ  ð5 sin xÞ
5 3 2
¼ ½ þ 5 þ 10  12:5 sin x
¼ 2:5 sin xt

Example 5.21 A subtracting amp or difference circuit of figure has v1 ¼ 60 cos xt,
v2 ¼ 18 cos xt volt, R1 ¼ Rf ¼ 5 kX and R2 ¼ R3 ¼ 10 kX. Find the value of v0 .

v2 v3

¼ð
R2 þ R3 Þv0
Solution From given figure, v1 v2 RR2 =R
1
2 þ R3
Rf .
For R1 ¼ Rf and R2 ¼ R3 , we get
v1  v2=2 v2=2  v0
¼
Rf Rf
or v0 ¼ v2  v1 ¼ 18 cos xt  6 cos 0t
¼ 12 cos xt

Example 5.22 For an integrated circuit of given figure, v1 ¼ ð1VÞ sin xt. If R1 ¼
5 kX and C ¼ 1:0  103 PF. Find v0 at xt ¼ p2 if v0 ð0Þ ¼ 0 and x ¼ 1 MHz .
Solution The O/P potential of the integrator circuit

Zt
1
v0 ¼ v1 dt given v0 ð0Þ ¼ 0
R1 C
0

In the present exercises,

260 5 Operational Amplifier (Op-Amp)

R1 ¼5 kX; C ¼ 1  103 PF
p p
v1 ¼ð1VÞ sin xt and xt ¼ or t ¼
2 2x
Zt
1
v0 ¼ ð1VÞ sin xt dt
R1 C
0
1 p=2x
¼ ½cos xt0
R1 Cx
1 h p i 1
¼ cos  cos 0 ¼
R1 Cx 2 R1 C0
1
¼ ¼ 0:2V
5  103  1  105  106

Example 5.23 The given figure shows an active differentiator which has a very
high input impedance. The second stage is an inverting buffer. If the given O/P
signal is a triangular wave with its slope of ± 400 mV/20 µ sec, find the output
voltage.

Solution The input of a triangular wave, therefore the output, must be a square
wave. The output of the differentiator circuit is given by the relation.
Here,
5.13 Op-Amp Parameters 261

dvl 400 mV
C ¼0:001 lF; RF ¼ 10 kX; ¼
dt 20 ls
 
v01 ¼  10  10  10 400  10  20  106
3 9 3

¼  200mV

It will acts as O/P for the second stage, which is an inverting buffer.

¼ the output voltage v02 ¼ ðR2 =R1 Þvi

¼ 10ð200mVÞ
¼ 2V:

Example 5.24 It is desired to have an output which is sum of the integrals of the
various inputs, i.e.,
Z Z Z
e0 ¼ e1 dt þ e2 dt þ e3 dt þ   

Give an appropriate circuit and prove the result.

Solution From the givencircuit

de0
I ¼ I1 þ I2 þ I3 . . . ¼ C
dt
e1 e2 e3 de0
¼ þ þ ¼ C
R R R dt
R R R

Or e01 ¼ R1t e1 dt þ e2 dt þ e3 dt þ    .
Selecting R ¼ 10kX and C ¼ 100lF we get RC ¼ 1
Z Z Z 
e01 ¼ e1 dt þ e2 dt þ e3 dt   

R R R
If RR43 ¼ 1 then e0 ¼ e0 ¼ e1 dt þ e2 dt þ e3 dt.
and hence, the result.
262 5 Operational Amplifier (Op-Amp)

Example 5.25 Design an op-amp-based non-inverting op-amp heavy with a gain

of 11. Determine the input impedance of this, and the chosen op-amp has open-loop
gain of 10,000 and open-loop input impedance of 1 µΩ.
Solution Figure shows the basic non-inverting amplifier using the op-amplifier.
The gain of this amplifier is given by


R2
1þ required gain ¼ 11
R1

Therefore, RR21 ¼ 10.

for R1 ¼ 10 kX; R2 ¼ 100 kX.
Now for the non-inverting amplifier, the impedance Rm is given by

open loop gain

open loop input impedance  loop gain = open loop impedance 
closed loop gain
10000
¼1 lX
11
¼ 9091 lX

Example 5.26 Design an op-amp-based logging-type phase shifter that can shift
the phase of an input sinusoidal signal by—60 with a gain of unity. If the input
signal has a peak amplitude of 5 V and the highest input frequency is 50 kHz, what
should be the slew rate of the chosen op-amp so that it does not limit the
bandwidth?
5.13 Op-Amp Parameters 263

Solution For unity gain, R1 ¼ R2 .

The phase shift introduced by the circuit ðhÞ is given by

h ¼ 2 tan1 ð2p f RCÞ

 
60 ¼ 2 tan1 2p  50  103 RG
105 pRC ¼ tan 30 ¼ 0:577
for C ¼ 0:001lF

0:184  105
R¼ ¼ 1840 ¼ 1:84 kW
0:001  106
Let R1 ¼ R2 ¼ 10kX
if I=P signal amp ¼ 5V peak
slew rate
fmax ¼
2pvoðmaxÞ
or slew rate ¼ 2p  5  50  103 ¼ 31:4  50  103
¼ 157  104 v/s ¼ 1:57 ls

Example 5.27 For the non-invertingcircuit RL ¼ 5kX and Rf ¼ 200kX, determine

the vgain .
Solution (Ar) vgain 1 þ RF
RL ¼ 1þ 200
5 ¼ 41.
Example 5.28 Find the output of the given circuit.

Solution The O/P voltage equation for this circuit can be obtained by using the
superposition theorem. For instance to find the O/P voltage due to va along, reduce
all the I/P voltage v0 ; vc ; vd to zero vd .
In fact, this circuit is an inverting amplifier in which the inverting input is at
virtual ground ðv2 ¼ 0VÞ. So, v0a ¼ Rva ¼ va2 . Now its input voltages va ; vb and
vd are set R to zero, and the circuit is becoming an inverting amplifier in which the
voltage v at the non-inverting input pin
264 5 Operational Amplifier (Op-Amp)

vc  R12  vcb
v1 ¼
R þ R12
 
This means that the O/P voltage due to vc alone is voc ¼ 1 þ R
R1 v 1 ¼ vc .

Similarly ¼ vod ¼ vd . Thus, by superposition theorem, the O/P voltage due to

all form voltage is given by
v0 ¼ v0 a þ v0 b þ v 0 c þ v0 d

v0 ¼ va  vb þ vc þ vd

Example 5.29 If time constant of the integration is one sec and input is a step
(dc) voltage as shown in the figure, determine the O/P voltage and sketch it
assuming that the op-amp is initially null.
Solution The function is constant beginning at two seconds.
This is vi ¼ 2V for 0
t
4, therefore,

t ¼4
Z4
v0 ¼  2dt
0
2 1 3
Z Z2 Z3 Z4
¼  4 2dt þ 2dt þ 2dt þ 2dtv0 5
0 1 2 3
¼  ð2 þ 2 þ 2 þ 2Þ ¼ 8V
5.13 Op-Amp Parameters 265

Example 5.30 Sketch all output waveform of the differential amplifier if input is

(i) sine wave

(ii). square wave
Solution

Summary
1. Basics: An op-amp has inverting and non-inverting inputs. It has high input
impedance at both input terminals and a low output impedance. It has large
voltage gain which remains constant over a large frequency range.
2. Inverting amplifier

Rf
Av ¼ 
R1
266 5 Operational Amplifier (Op-Amp)

3. Non-inverting amplifier

Rf
Av ¼ 1 þ
R1

4. Voltage follower amplifier gives unity voltage gain.

5. Adder

v0 ¼  ð v1 þ v2 þ v3 Þ

6. Difference amplifier

R2
v0 ¼ ð v2  v1 Þ
R1

7. Subtract or

v0 ¼ v2  v1 for R1 ¼ R2

8. Differentiator

dv
v0 ¼ RC
dt

9. Integrator

Z
1
vO ¼ vdt
Rc
5.13 Op-Amp Parameters 267

10. Op-amp parameters.

(i) Input offset voltage

vi0 ¼ vdc1  vdc2

(ii) Input offset current

Ii0 ¼ jIB1  IB2 j

(iii) Bias current

I B1 þ I B2
IB ¼
2

(iv) Slew rate

2pfvP
SR ¼ v/ls
106

(v) Bullet CMMR ¼ AAcmd .

Exercises
5:1. Explain an ideal op-amp with circuit diagrams.
5:2. What do you understand by inverting and non-inverting in an op-amp?

Explain in detail.

5:3. Derive equation for an adder.

5:4. What is output from a differentiator? Derive the formula.
5:5. Describe integrators and differentiators. Give their output equations.
5:6. What is an op-amp? Draw and explain the block diagram of op-amp.
5:7. Explain the significance of virtual ground in a basic inverting amplifier. How
would you explain its existence?
5:8. Draw the pin diagram of an IC used as an operational amplifier. Explain the
functions of the different pin connection.
268 5 Operational Amplifier (Op-Amp)

5:9. Explain the functioning of a buffer amplifier.

5:10. Explain why open-loop op-amp configuration are not used in linear
applications.
5:11. Find the output voltage of an open-looped op-amp having A = 200,000
when the differential I/P voltage is ± 50 µV.[Ans. 10V]
5:12. For a given op-amp, CMRR = 105 and differential gain Ad = 105.
Determine the common-mode gain Acm of the op-amp.[Ans. 1]
5:13. The output voltage of a certain op-amp circuit changes by 20 V in 4 s. What
is its slew rate?[Ans. 5 ls]
5:14. In the circuit of figure if R1 ¼ R2 ¼ 1 kX, Rr ¼ R3 ¼ 10 kX, vd ¼ 5 mV sine
wave at 1 kHz and Vm (noise voltage) ¼2 mV at 60 Hz, calculate (a) the
output voltage at 1 kHz and (b) the amplitude of the induced 60 Hz noise at
the output. The op-amp is the m741 with CMRR ðdBÞ ¼ 90dB.

[Ans. 50mV; 0:63mVðat60Hz:Þ].

5:15. Find the closed-loop circuit gain and the output voltage for an inverting
op-amp having input signal vi as 1 V (peak to peak) and R1 and Rf as 1 kΩ
and 10 kΩ, respectively.[Ans. 10V].
5:16. Find the closed-loop circuit gain and the output voltage for a non-inverting
op-amp circuit having input signal V in as 1 V (peak to peak) and R1 and Rf
as 1 kΩ and 10 kΩ, respectively.[Ans. 11; 11V].
5:17. An operational amplifier is to have a voltage of 50. Calculate the required
values for the external resistors R1 and Rf if (a) a non-inverting (b) an
inverting gain is required.[Ans. 2kX; 2kX].
5:18. In a differential amplifier of the type shown in fig.R1 ¼ 10 kX R2 ¼ 100 kX
R3 ¼ 10 kX and R4 ¼ 10 kX R4 = 10 kΩ. Calculate the output voltage of the
circuit if
(i) v1 ¼ 10 mV; v2 ¼ 0, (ii) v1 ¼ 0; v2 ¼ 10 mV (iii) v1 ¼ 100 mV; v2 ¼ 50 mV,
and.
(iv) v1 ¼ 50 mV; v2 ¼ 1 mV.[Ans. 100mV þ 100mV; 500mV þ 500mV].
5.13 Op-Amp Parameters 269

5:19. Find an expression for the Input impedance of the unity follower amplifier.
Ans. zin ¼ AOLRd ].

5:20. Find an expression for the output v0 of the amplifier circuit of the given
figure Assume an ideal op-amp. What mathematical operation does the cir-
cuit perform?
h i
[Ans 2 1 þ R1 ðvs1 þ vs2 Þ].
1 R2

5:21. For the non-inverting amplifier of figure, find an exact expression for the
vgain ratio.

R1 þ R2
[Ans Av ¼ vv02 ¼ R1 R2 ðR þ R Þ ].
1A  1A 2
OL Rd OL
270 5 Operational Amplifier (Op-Amp)

5:22. Find the V gain ratio Av of the non-inverting amplifier of given figure in
terms of its CMRR. Assume v1 = v2 insofar as the common-mode gain is
concerned.

AOL
[Ans Av ¼ vv02 ¼ A R  CMRR
AOL
].
1R OLþ R1
1 2 A R
1 OL 1
R1 þ R2

5:23. An inverting summer (fig) has n input with R1 = R2 = R. Assume that the
open-loop basic op-amp gain AOL is infinite, but that the inverting terminal
input current is negligible. Derive a relationship that shows how gain mag-
nitude is reduced in the presence of multiple inputs for a practical op-amp.

Rf =R
[Ans. An ¼  nRf ].
1ð1 þ RÞA
OL
Chapter 6
Switching Theory and Logic Design
(STLD)

6.1 Introduction

Switching circuits are for the use of binary variables and application of binary logic.
Electronic digital circuits are also types of switching circuits. In digital systems, the
numbers are represented by binary numbers rather than decimal system. The binary
numbers are also used in arithmetic operations. Digital circuits use binary signals to
control conduction or non-conduction or non-conduction state of an active element
such as transistor, FET, MOSFET, etc. Digital circuits use transistor as switch.
Switching circuits are also called logic circuits as it can establish logical manipu-
lation with proper controlled inputs. Logic circuits are used to compute and control
any desired information in the form of binary signals. Logic circuits which perform
logical functions are called logic gates. Logic gates are the basic building blocks of
any combinational logic network as per requirement.

6.2 Number System

6.2.1 Decimal System

Decimal system is normally used for expressing numbers. In decimal system, there
are ten digits from 0 to 9; therefore, it has a base of 10. This implies that each digit
in a decimal number represents a multiple of a power of 10.
Consider decimal number 468. It has four hundreds, six tens and eight units.
This can be written as:

4
102 þ 6
101 þ 8
100

© The Author(s), under exclusive license to Springer Nature Switzerland AG 2022 271
O. N. Pandey, Electronics Engineering,
https://doi.org/10.1007/978-3-030-78995-4_6
272 6 Switching Theory and Logic Design (STLD)

A weight is assigned to the position of each digit. Whole numbers have weights
which are positive, increasing from right to left. The lowest is 100= 1. In the case of
fractional numbers, the weights are negative decreasing from left to right, starting
with 10−1 = 0.1. Hence, the number 268.17 can be written as:

2
102 þ 6
101 þ 8
100 þ 1
101 þ 7
102

6.2.2 Binary System

Binary system has a base of 2, and there are only two digits, 0 and 1. These are
called bits; thus, a binary number can only be expressed in 0's and 1's. For example,
binary number 101 can be written as:

1
22 þ 0
21 þ 1
20

In decimal system, this represents 4 + 0 + 1 = 5. Table 6.1 shows four digit

binary numbers. It may be noted that number of bits has to be increased to represent
larger numbers. 5 bits would double the range compared to 4 bits. 6 bits would
double the range of 5 bits. It can be seen from the table that 11012 ¼ 13100 .
A binary number is also a weighted number similar to the decimal system. The
least significant bit (LSB) is the right-hand bit and it has a weight 20 = 1. Increase of

Table 6.1 Four digit binary Binary

numbers
Decimal 23 = 8 22 = 4 21 = 2 20 = 1
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1
6.2 Number System 273

Table 6.2 Binary fractional number bits

Binary 26 25 24 23 22 21 20 2−1 2−2 2−3 2−4
Decimal 64 32 16 8 4 2 1 0.5 0.25 0.125 0.625

weights are from right to left by a power of 2 for each bit. The most significant bit
(MSB) is the left-hand bit. The size of the binary number determines the weight.
Representation of fractional binary numbers is done by placing bits to the right
of the binary number; hence, Table 6.2 gives details.

6.2.3 Octal System

It was observed that as decimal numbers become larger, the binary number takes up
more and more digits; octal system can reduce the digits as it has eight digits 0 to 7.
This means that octal has a base of 8 and each digit represents a power of 8.

6.2.4 Hexadecimal System

Hexadecimal system has base of 16 and has 16 digits out of which ten are numbers
from 0 to 9; and remaining six are first 6 letters of the alphabet. Hexadecimal codes
are used quite often to represent binary numbers. Table 6.3 shows the comparison
of binary, decimal and hexadecimal numbers.

Table 6.3 Comparison of Binary Decimal Hexadecimal

binary, decimal and
hexadecimal numbers 0000 0 0
0001 1 1
0010 2 2
0011 3 3
0100 4 4
0101 5 5
0110 6 6
0111 7 7
1000 8 8
1001 9 9
1010 10 A
1011 11 B
1100 12 C
1101 13 D
1110 14 E
1111 15 F
274 6 Switching Theory and Logic Design (STLD)

Groups of four digits can be represented by single digit using hexadecimal base.
For example:

ð100111000100Þ2 ¼ 9C416

ð101100011010Þ2 ¼ B1 A16

Decimal equivalent of 9C416 is given as:




9C416 ¼ 9
162 þ C
161 þ 4
160
¼ ð9
256Þ þ ð12
16Þ þ ð4
1Þ
¼ ð2304 þ 192 þ 4Þ10
¼ ð2500Þ10 :

6.3 Conversion of Bases

6.3.1 Decimal to Binary

Successive division of decimal number by 2 is done. The quotient and remainders

are noted till the completion of division process. The remainders give the binary
number. The first remainder is LSB, and the last remainder is MSB. Conversion of
decimal number 29 into its binary equivalent is as follows:
2 29
2 14 → 1 → LSB
2 7 →0
2 3 →1
2 1 → 1 → MSB

Hence, 2910 ¼ ð11101Þ2 .

6.3.2 Binary to Decimal

Use weight of a bit ¼ nth bit
2n1 and add to get decimal number. For example:

ð11101Þ2 ¼ 1
24 þ 1
23 þ 1
22 þ 0
21 þ 1
20
¼ 16 þ 8 þ 4 þ 0 þ 1 ¼ 2910
6.3 Conversion of Bases 275

6.3.3 Fractional Decimal Number to Binary

It is done by successive multiplication of 2 and carry of the number after decimal is

recorded. The process is continued until a fractionless decimal number is reached.
For example:
Conversion of 0.683 into binary is as follows:
Carry
0.683 × 2 = 1.366 1 MSB
0.366 × 2 = 0.732 0
0.732 × 2 = 1.464 1
0.464 × 2 = 0.928 0

0.928 × 2 = 1.856 1
0.856 × 2 = 1.712 1
0.712 × 2 = 1.424 1
0.424 × 2 = 0.848 0
0.848 × 2 = 1.696 1
0.696 × 2 = 1.392 1 LSB

Hence, 0.68310 = (0.1010111011)2.

6.3.4 Fractional Binary to Decimal

The weightage followed is 2–1, 2–2, 2–4, ……2–n.

For example:


ð0:11001Þ2 ¼ 1
21 þ 1
22 þ 0
23 þ 0
24 þ 1
25 10
 
1 1 1
¼ þ þ0þ0þ
2 4 32 10
¼ ð0:5 þ 0:25 þ 0:3125Þ10
or ð0:11001Þ2 ¼ ð0:0625Þ10

6.3.5 Octal to Decimal

Multiply each digit of octal number to the subsequent powers of eight.

276 6 Switching Theory and Logic Design (STLD)

For example:


ð36Þ8 ¼ 3
81 þ 6
80 10
¼ ð24 þ 6Þ10
or ð36Þ8 ¼ ð30Þ10

6.3.6 Decimal to Octal

Continuous division is done by 8. First remainder is LSD, and last is MSD.

For example: (37)10 Remainder.
10
8 37
8 4 → 5 → LSB
8 0 → 4 → MSB
∴ (37)10 = (45)8

6.3.7 Binary to Octal

The base is 8 = 23; hence, group of 3 bits are formed from right side.
For example:

ð101110011Þ2 ¼ ð 101 110 011 Þ2

¼ ð5 6 3 Þ8

6.3.8 Octal to Binary

Each digit of the octal number is converted to its three-bit binary equivalent.
For example:

ð43Þ8 ¼ð100 011Þ2

or ð43Þ8 ¼ð100011Þ2
6.3 Conversion of Bases 277

6.3.9 Hexadecimal to Decimal

Multiply the digits to the 16 with its corresponding power.

For example:


ð8AÞ16 ¼ 8
161 þ A
160 10
¼ ð128 þ 10
1Þ10
¼ ð138Þ10

6.3.10 Decimal to Hexadecimal

Successive division by 16 is done. First remainder is LSD, and last remainder is

MSD.
For example: (73).
10
16 73
16 4 → 9 → LSB
0 → 4 → MSB

Hence, ð73Þ10 ¼ ð49Þ16 .

6.3.11 Hexadecimal to Binary

Each digit is converted into its equivalent four-bit binary equivalent.

For example:

ð5CABÞ16 ¼ ð0101 1100 1010 1011Þ2

¼ ð0101110010101011Þ2

6.3.12 Binary to Hexadecimal

Groups of four bits are made from RHS, i.e., LSB, and then converted into
hexadecimal.
278 6 Switching Theory and Logic Design (STLD)

For example:

ð1000111Þ2 ¼ ð1000 1101Þ16

¼ ð8DÞ16

6.3.13 Hexadecimal to Octal

Convert each digit into its binary equivalent, and then binary system number is
divided into the groups of three bits starting from, RHS, i.e., LSB. Convert these
groups into octal.
For example:

ð4ABÞ16 ¼ ð 0100 1010 1011 Þ2

¼ ð 010 010 101 011 Þ2
¼ ð2 2 5 3 Þ8
¼ ð2253Þ8

6.4 Binary Coded Decimal (BCD) Numbers

Each digit of decimal number is converted into four binary bits, and group sepa-
ration is maintained.
For example:
ð3Þ10 ¼ ð0011ÞBCD
ð12Þ10 ¼ ð00010010ÞBCD

6.5 Binary Addition

Digits are added from LHS, i.e., LSB, and carry is taken to RHS for addition.
For example: (11001)2 + (10010)2
← carry
1 1 0 0 1
+ 1 0 0 1 0
1 0 1 0 1 1

Hence, ð11001Þ2 þ ð10010Þ2 ¼ ð101011Þ2 .

6.6 Binary Subtraction 279

6.6 Binary Subtraction

Digits are subtracted from LHS, i.e., LSB, and digits are borrowed from RHS if
needed.
For example: (1101)2 – (1010)2
Borrow→
1 1 0 1
– 1 0 1 0
0 0 0 1

Hence, ð1101Þ2  ð1010Þ2  ð0001Þ2 .

6.7 Boolean Algebra

6.7.1 Basics

De Morgan related Boolean with algebra. George Boole constructed an algebra

known as Boolean algebra. Boolean algebra implements operations of a system of
logic required for digital circuits based on on–off/true–false/high-low/ 1–0 bistates.
Boolean statements may take the form of algebric equations, logic block diagrams,
or truth tables as:
Logic variables may have only two values 0 or 1.
Logic Operators of Boolean algebra are:
AND = and (.)
OR = or (+)
NOT = not (–)
XOR = exclusive or ⊕
The outputs of any algebraic statements are represented by truth table giving the
output values in 0 or 1. Various operator truth tables are as follows:
(i) Truth table for logical operator AND (0)

Inputs Outputs
A B C = A. B
0 0 0
0 1 0
1 0 0
1 1 1
280 6 Switching Theory and Logic Design (STLD)

(ii) Truth table for logical operator OR (+)

Inputs Outputs
A B C=A+B
0 0 0
0 1 1
1 0 1
1 1 1

(iii) Truth table for logical operator NOT ( –)

Input Output
A A
0 1
0 0

6.8 Boolean Algebra Theorems Table

S No. Name Theorem
1 Cumulative law A+B=B+A
2 Associative law (A + B) + C = A + (B + C)
(A  B)  C = A  (B  C)
3 Distributive law A  (B + C) = A  B + A  C
A + (B  C) = (A + B)  (A + C)
4 Identity law A+A=A
AA=A
5 Negation law A=A
6 Redundancy law A+AB=A
A  (A + B) = A
7 Boolean postulates O+A=A
1A=A
OA=0
A+A=1
AA=0
A+AB=A+BA
( A + B) = A  B
8 De Morgan's law AþB ¼ A  B
A  B ¼ AþB
6.9 Logic Gates And Universal Gates 281

6.9 Logic Gates And Universal Gates

The elements of digital circuits which implement the switching logic are known as
digital logic gates, and their symbols are given in the table which follows. Circuit
diagrams which include these symbols are known as logic block diagrams.
S No. Logic gate Symbols
1 AND

2 OR

3 XOR

4 NOT

5 NAND

6 NOR

7 XNOR

AND, OR and NOR gates are known as basic gates as any logic expression can
be realized using these gates together. The gates which can create any desirable
gates are known as universal gates which are NAND and NOR gates.
AND, OR, NOT, etc. can be created using only NAND or NOR gates. Thus, any
Boolean logic statement can be written by using either NAND or NOR gates only.
A general approach in digital circuit design is to write a logic statement or
function describing the required process without regard to complexity.
Subsequently, logic statement is simplified to allow implementation with a mini-
mum number of logic gates. One of the methods of simplification is by manipu-
lation of the function using theorems until an equivalent is found which requires a
minimum combinations of logic gates.
282 6 Switching Theory and Logic Design (STLD)

6.10 Canonical Forms

A binary bit has two states—normal state and complementary state. A literal is
primed or unprimed variable, and each designates an input to a logic gate in a given
function. Suppose, there are two variables A and B which are fed to an AND gate.
As each variable can have two values, as such possible combinations will be four,
i.e., AB, A B, A B, AB, and each of these AND terms is known as minterm or a
standard product. Thus, n variables will have two possible minterms.
Similarly, an OR term product of n variables will have maxterm or standard sum.
Thus, canonical forms can be of two types, namely sum of products (SOP) or
product of sums (POS).
The following table shows the possible combinations of two variables A and B. It
can be noted that each minterm is the complement of its corresponding maxterm
and vice-versa. A Boolean expression can be written algebrically from the truth
table by expressing each combination of the variables which give a 1 in function by
a minterm and then using OR operator for all of the maxterms.
Table for SOP-type canonical form
Input Minterms Output as given
A B Y
0 0 AB 1
0 1 AB 1
1 0 A B 1
1 1 AB 1

Addition of all the minterms of high (1) gives the SOP type canonical form:

FðA; BÞ ¼ AB þ AB þ AB þ AB

Table for POS-type canonical form

Input Minterms Output as given
A B Y
0 0 A+B 1
0 1 A+B 0
1 0 A+B 0
1 1 A+B 1

Multiplication of all the maxterms of low (0) gives the POS-type canonical
Form:

FðA; BÞ ¼ ðA þ BÞðA þ BÞ
6.11 K-map 283

6.11 K-map

Karnaugh-map (K-map) or witch diagram is a graphical representation of funda-

mental products in a truth table. This method requires drawing number of squares in
a rectangle or squares. Each square represents a minterm. Number of variables
decides the number of squares. In case of n variables, the number of squares will
be 2n.
(i) K-map for two variables
K-map of two variables will have 22 = 4 squares. There is one square corre-
sponding to each of the possible combination of variables, i.e., minterms. K-map in
this case is as follows:

(ii) K-map for three variables

K-map of three variables will have 23 = 8 squares. There is one square corre-
sponding to each of the possible combination of variables, i.e., minterms. K-map in
this case is as follows:

(iii) K-map for four variables

K-map of four variables will have 24 = 16 squares. There is one square corre-
sponding to each of the possible combinations of variables, i.e., minterms. K-map in
this case is as follows:
284 6 Switching Theory and Logic Design (STLD)

6.12 Simplification of Boolean Expression Using K-map

Suppose F ¼ X Y þ XY is to be simplified using K-map. K-map is as follows:

The adjacent two squares showing 1 are grouped together, i.e., encircled. Y is
common to both squares. Hence, simplified expression is F ¼ Y.
Now, consider an example with three variables.
Suppose expression F ¼ XYZ þ XYZ þ XYZ is given. K-map is as follows:
6.12 Simplification of Boolean Expression Using K-map 285

In this case also, two squares each showing 1 are grouped together, i.e., encir-
cled. Hence, simplified expression is F ¼ XZ þ XY.
Further, consider example with four variables.
Suppose expression F ¼ PQRS þ PQRS þ PQRS þ PQRS þ PQRS.
K-map is as follows:

Four squares with 1 are encircled. Column-wise variable Q is common and

row-wise S is common. Hence, adjacent four squares give QS after simplification.
Moreover, the square representing PQRS is alone; therefore, it is encircled by itself.
Thus,
F ¼ QS þ PQRS

6.13 Simplification in Sum of Product (Sop) Form

In this method, groups of o-squares are made, and subsequently, a sum of products
of complementary function is obtained.
Consider expression

F ¼ ðX þ Y þ ZÞðX þ Y þ ZÞðX þ Y þ ZÞ

or
FðX; Y; ZÞ ¼ pð0; 1; 3Þ
286 6 Switching Theory and Logic Design (STLD)

The K-map is as follows:

It is found that two vertical o-squares have common variables X and Y with
o-logic. There is no common variable from row side; therefore, the sum is (X + Y).
Two horizontal o-squares have Z common with Logic 1; therefore, its complement
is taken. From column side, variable X with o-logic is common; therefore, X is
taken. The sum is X + Z . Thus, simplified expression is:

FðX; Y; ZÞ ¼ ðX þ YÞðX þ ZÞ

Solved Examples
Example 6.1 Convert the following binary numbers into decimal.
(i) 101.01 (ii) 10101.0101.
Solution (i) (101.01)2 ! ( )10

101:01 ¼ 1
22 þ 0
21 þ 1
20 þ 0
21 þ 1
22

1
¼ 4þ0þ1þ0þ
4
1
¼ 5 þ ¼ 5:25
4

Therefore, we have
(101.01)2 = (5.25)10.
(ii) (10101  0101)2 ! ( )10

10101:0101 ¼ 1
24 þ 0 þ 23 þ 1
22 þ 0
21 þ 1
20
þ 0
21 þ 1
22 þ 0
23 þ 1
24
1 1
¼ 16 þ 0 þ 4 þ 0 þ 1 þ 0 þ þ 0 þ
4 16
¼ 21:3125

Therefore, we have
(10101  0101)2 = (21.3125)10.
Example 6.2 Convert (4320)10 into binary number system.
6.13 Simplification in Sum of Product (Sop) Form 287

Solution (4320)10 ! ()2.

2 4320
2 2160 →0
2 1080 →0 (Reading from bottom to the top)
2 540 →0 Therefore, we obtain (4320)10
2 270 →0 = (100011100000)2
2 135 →0
2 67 →1
2 33 →1
2 16 →1
2 8 →0
2 4 →0
2 2 →0
2 1 →1
0

Example 6.3 Convert (3451)10 into binary number system.

Solution
2 3451
2 1725 → 1
2 862 → 1
2 431 → 0
2 215 → 1
2 107 → 1
2 53 → 1
2 26 → 1
2 13 → 0
2 6 → 1
2 3 → 0
2 1 → 1
0 → 1

Reading from bottom to the top.

Therefore, we obtain
288 6 Switching Theory and Logic Design (STLD)

ð3451Þ10 ¼ ð110101111011Þ2 :

Example 6.4 Convert the decimal number (250.5)10 to base 3, base 4, base 7 and
base 16.

Solution Given Number = (250.5)10

For base 3
3 250
3 83 → 1 0.5
3 27 → 2 ×3
3 9 → 0 1. 5 → 0.5
3 3 → 0 ↓ ×3
3 1 → 0 1 1. 5
0 → 1

or

ð250:5Þ10 ¼ ð100021:11Þ3

For base 4
4 250
4 62 → 2 0.5
4 15 → 2 ×4
4 3 → 3 2. 0
0 → 3 ↓
2

or

ð250:5Þ10 ¼ ð3322:2Þ4

For base 7
6.13 Simplification in Sum of Product (Sop) Form 289

7 250 0.5
7 35 → 5 ×7
7 5 → 0 3. 5 → 0.5
0 → 5 ↓ ×7
3 3. 5
↓
3

or

ð250:5Þ10 ¼ ð505:33Þ7

For base 16
16 250 0.5
16 15 → A × 16
0 F ↑ 8. 0
↓
8

or

ð250:5Þ10 ¼ ðFA:8Þ16 :

Example 6.5 Convert (1201102)3 = (16)10

Solution

ð1201102Þ3 ¼ 1
36 þ 2
35 þ 0
34 þ 1
33 þ 1
32

þ 0
31 þ 2
3
¼ 729 þ 486 þ 0 þ 27 þ 9 þ 0 þ 2
ð1201102Þ3 ¼ ð1253Þ10 :

Example 6.6 Add the following binary numbers.

11010101 and 1101101

290 6 Switching Theory and Logic Design (STLD)

Solution We have
1 1 1 1 1 1 ← carry
11010101
1101101
101000010

Example 6.7 Add (10111010)2 and (101001)2.

Solution We have
111 ← carry
10111010
101001
11100011

Example 6.8 Add the following without changing the base.

(i) (734)8 + (444)8
(ii) (432)5 – (124)5
(iii) (AID)16 + (99F)16

Solution (i) (734)8 + (444)8.

Here, we have.
11 ← carry
(7 3 4)8
+ (4 4 4)8
(1 4 0 0)8

Therefore, we write

ð734Þ8 þ ð444Þ8 ¼ ð1400Þ8

(ii) (432)5 – (124)5.

Thus,
(432) 5
– (124) 5
(303) 5
6.13 Simplification in Sum of Product (Sop) Form 291

(iii) (A1D)16 + (99F)16

1
(A1D)16
+ (99F)16
(13 B C)16

Example 6.9 Write the sum of (23.53)10 and (23.53)8 in decimal.

Solution Firstly, let us convert (23.53)8 in decimal and then add it with
(23.53)10.
Thus, we have,

ð23:53Þ8 ¼ 2
81 þ 3
80 þ 5
81 þ 3
82

5 3
¼ 16 þ 3 þ þ
8 64
¼ 16 þ 3 þ 0:625 þ 0:046875
ð23:53Þ8 ¼ ð19:671875Þ10

Therefore,
(23.53) 10
(19.671875)10
(43.201875)10

Example 6.10 Convert the following hexadecimals into decimals.

(i) A 13 B
(ii) 7C A 3
(iii) 7F D6

Solution (i) (A 13 B)16 ! ()10.

We have
A 1 3 B
↓ ↓ ↓ ↓
10 1 3 11
= 10 × 163 + 1 × 162 + 3 × 161 + 11 × 160
= 40960 + 256 + 48 +11
= (41275)10
292 6 Switching Theory and Logic Design (STLD)

Therefore, we obtain

ðA13BÞ16 ¼ ð41275Þ10

(ii) (7 C A 3)16 ! ( )10.

We have
7 C A 3
↓ ↓ ↓ ↓
7 12 10 3
= 7 × 163 + 12 × 162 + 10 + 161 + 3 × 160
= 28672 + 3072 + 160 + 3
(7CA3)16 = (31907)10

(iii) (7FD6)16 ! ()10.

We have
7 F D 6
↓ ↓ ↓ ↓
7 15 13 6
= 7 × 163 + 15 × 162 + 13 × 161 + 6 × 160
= 28672 + 3840 + 208 + 6
= 32726

Therefore, we have (7FD6)16 = (32726)10.

Example 6.11 Obtain the following conversion.
(i) (23  AB)16 ! ()2.
Solution We have
(23 · AB)16 = 2 3. A B
↓ ↓ ↓ ↓
0010 0011 1010 1011

Therefore, we obtain

ð23  ABÞ16 ¼ ð00100011:10101011Þ2 :

Example 6.12 Convert the hexadecimal number (1CD  2A)16 to binary.

Solution (1CD  2A)16 ! ()2.

6.13 Simplification in Sum of Product (Sop) Form 293

We have 1 C(12) D(13) .2 A(10)

↓ ↓ ↓ ↓ ↓
0001 1100 1101 0010 1010

Therefore, we obtain

ð1CD  2AÞ16 ¼ ð000111001101  00101010Þ2 :

Example 6.13 Add the following hexadecimal number.

(i) 93 + DE
(ii) ABCD + EF 12

Solution (i) 93 + DE
We have
11 ← carry
(9 3)16
+ (D E)16
(17 1) 16

(ii) (ABCD)16 + (EF12)16

11 ← carry

A B C D
E F 1 2
(19 A D F)16

Example 6.14 Convert the octal number (1745.246)8 into hexadecimal number.

Solution (1745.246) = ( )16

We have
1 7 4 5 · 2 4 6
↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓
001 111 100 101 · 010 100 110
294 6 Switching Theory and Logic Design (STLD)

So,

ð1745:346Þ8 ¼ ð001111100101:010100110Þ2
¼ |ffl{zffl}
0011 |ffl{zffl} 0101  |ffl{zffl}
1110 |ffl{zffl} 0101 |ffl{zffl}
0011 |ffl{zffl}
0000
3 E 5 5 3 0
¼ ð3E5:530Þ16 :

Example 6.15 Simplify

Fða; b; cÞ ¼ abc þ bc þ abc þ abc using k  map:

Solution Here we have

Fða; b; cÞ ¼ abc þ bc þ abc þ abc

So, abc þ bc þ abc þ abc ¼ ab þ abc þ bc

Thus, we have

Fða; b; cÞ ¼ abc þ ab þ bc:

Example 6.16 Obtain 1's and 2's complement of 1010101, 0111000.

Solution
(i)
Binary No: ¼ 1010101
’
1 s complement ¼ 0101010
2’ s complement ¼ 10 s complement þ 1
¼ 0101010 þ 1
¼ 0101011:
6.13 Simplification in Sum of Product (Sop) Form 295

(ii)
Binary No: ¼ 0111000
0
1 s complement ¼ 1000111
20 s complement ¼ 10 s complement þ 1
¼ 1000111 þ 1
¼ 1001000:

Example 6.17 Convert 2 AC5  D to octal.

Solution 2AC5  D to octal.

2 A C 5 · D (Hex)
↓ ↓ ↓ ↓ ↓
0010 1010 1100 0101 · 1101(Binary)
010 101 011 000 101 · 110100
2 5 3 05 · 64 (Octal)

or ð2AC5  DÞ16 ¼ ð25305  64Þ8 :

Example 6.18 Using 10’s complement, subtract 72532 – 3250. Also perform the
operation using 9's complement.

Solution Let

M ¼72532
& N ¼3250 ¼ 03250
M ¼72532
100 s complement of N ¼96750
169282
neglecting end carry
Sum !69282

Using by 9's complement

9's complement of N = 96749
296 6 Switching Theory and Logic Design (STLD)

M = 72532
N = 96749 9’s
169281
1
69282

Example 6.19 Convert decimal number 225.225 to octal and hexadecimal.

Solution Decimal number = 225.225

(i) Decimal to octal

Decimal Integer part Remainder

8 225 –
28 1
3 4
0 3

Octal equivalent (225)10 = (341)8

Fractional part

0:225
8 ¼0:800 with a carry of 1

0:800
8 ¼0:400 with a carry of 6
0:400
8 ¼0:200 with a carry of 3
0:200
8 ¼0:600 with a carry of 1
0:600
8 ¼0:800 with a carry of 4
* ð0:225Þ10 ¼ð0:16314Þ8
Hence; ð225:225Þ10 ¼ð341:16314Þ8

(ii) Decimal to hexadecimal

Decimal Integer part Remainder

16 225 –
14 1
0 14 = E
6.13 Simplification in Sum of Product (Sop) Form 297

Hex equivalent ð225Þ10 ¼ðE1Þ16

Fractional Part 0:225
16 ¼0:600 with a carry of 3
0:600
16 ¼0:600 with a carry of 9
) ð0:225Þ10 ð:39Þ16
Hence; ð225:225Þ10 ¼ðE 1:39Þ16 :

Example 6.20 Write the dual of the following theorem:

A þ ðB  CÞ ¼ ðA þ BÞ  ðA þ CÞ

Solution Given theorem is

A þ ðB  CÞ ¼ ðA þ BÞ  ðA þ CÞ

To obtain dual of above theorem, replacing “+” by “”, “” by “+” and com-
plementing 0's and 1’s.

Dual A  ðB þ CÞ ¼ ðA  BÞ þ A  C
A  ðB þ CÞ ¼ A  B þ A  C:

Example 6.21 Obtain 9’s and 10’s compliment of 13579, 09900.

Solution
(i)
Decimal Number = 13579
9's complement = 99999
13579
86420
10's complement = 9's complement + 1
= 86420 + 1
= 86421
298 6 Switching Theory and Logic Design (STLD)

(ii) Decimal No. = 09900

9's Complement = 99999
09900
90099
10's complement = 90099 + 1
= 90100

Example 6.22 Simplify the following Boolean equations.

(i) F ¼ B  ðA þ BÞ.
(ii) F ¼ A þ B þ A  B  C.
(iii) F ¼ ABCD þ ABC  D.
(iv) F ¼ AC þ AB þ A  BC þ BC.

Solution
(i) F ¼ B  ðA þ BÞ ¼ B:A þ B  B
F ¼ B  A þ B ½* x  x ¼ x
F ¼ BðA þ 1Þ
¼ B  1 ½X þ 1 ¼ 1
¼B
(ii) F ¼ AþBþA  B  C
¼ A  1þBþA  B  C
¼ Að1 þ BCÞ þ B þ A  BC ½*1 þ x ¼ 1
¼ A þ ABC þ B þ ABC
¼ BCðA þ AÞ þ A þ B
¼ BC  1 þ A þ B ½* x þ x ¼ 1
¼ BC þ A þ B
(iii) F ¼ ABCD þ ABC  D
¼ ABCðD þ DÞ
¼ ABC  1
(iv) F ¼ AC þ AB þ A  BC þ BC
F ¼ AB þ CðA þ AB þ BÞ
¼ AB þ C½A þ AB þ BðA þ AÞ
¼ AB þ C½A þ AðB þ BÞ þ A  B
¼ AB þ C½A þ A  1 þ AB
¼ AB þ C½1 þ AB ½*A þ A ¼ 1
¼ AB þ C  1 ½1 þ AB ¼ 1
F ¼ AB þ C:
6.13 Simplification in Sum of Product (Sop) Form 299

Example 6.23 Express the following functions in a sum of minterms and a product
of maxterms.
(i) F(x, y, z) = 1
(ii) F(A, B, C, D) = D (A + B) + B  D.

Solution (i) F(x, y, z) = 1

Since F(x, y, z) equals 1, the minterms are:

Fðx; y; zÞ ¼xyz þ xyz þ xyz þ xyz þ xyz þ xyz þ xyz þ xyz

X
Fðx; y; zÞ ¼ mð0; 1; 2; 3; 4; 5; 6; 7Þ

From above, it is clear that there is no maxterm in the given expression.

(ii) FðA; B; C; DÞ ¼DðA þ BÞ þ BD
FðA; B; C; DÞ ¼D  A þ D  B þ B  D
Now, we will simplify term by term

DA ¼ DAðB þ BÞ
¼ DAB þ DAB
¼ DAB½C þ C þ DAB½C þ C ½*X þ X ¼ 1

DA ¼ DABC þ DABC þ DABC þ DABC

DA ¼ ABCD þ ABCD þ ABCD þ ABCD . . .ðiÞ

DB ¼ D  B  1 ¼ D  BðA þ AÞ ¼ D  BA þ DB  A
¼ D  B  A½C þ C þ D  B  A

½C þ C ¼D
B
A
C þ D
B
A
C þ D
B
A
C
þD
B
A
C . . .ðiiÞ

BD ¼ BDðA þ AÞ ¼ BDA þ BDA

¼ BDAðC þ CÞ þ BD  AðC þ CÞ
¼ BDAC þ BDAC þ BDAC þ BDAC
¼ ABCD þ ABCD þ ABCD þ ABCD ðiiiÞ

Therefore = DA þ D  B þ BD,
Putting the values from (i), (ii) and (iii)
300 6 Switching Theory and Logic Design (STLD)

FðA; B; C; DÞ ¼ ABCD þ ABCD þ ABCD þ ABCD þ ABCD þ ABCD

þ ABCD þ ABCD þ ABCD þ ABCD þ ABCD þ ABCD

FðA; B; C; DÞ ¼ ABCD þ ABCD þ ABCD þ ABCD

þ ABCD þ ABCD þ ABCD þ ABCD ½*X þ X ¼ 1

FðA; B; C; DÞ ¼ m7 þ m5 þ m3 þ m1 þ m15 þ m13 þ m11 þ m9

X
FðA; B; C; DÞ ¼ mð1; 3; 5; 7; 9; 11; 13; 15Þ
*Maxtermsare ¼pMð0; 2; 4; 6; 8; 10; 12; 14Þ:

Example 6.24 Convert the following into other canonical forms:

P
(a) f (x, y, z) = m (1, 3, 6.7)
(b) f (x, y, z) = p m (0, 3, 6, 6.7)

Solution (a) f ðx; y; zÞ ¼ Smð1;X 3; 7Þ

0
f ðx; y; zÞ ¼ mð0; 2; 4; 5; 6Þ
∵ Compliment 0
f ðx; y; zÞ ¼m0 þ m2 þ m4 þ m5 þ m6
Using De Morgan’s theorem

f ðx; y; zÞ ¼m0 þ m2 þ m4 þ m5 þ m6 ¼ m0  m2  m4  m5  m6
f ðx; y; zÞ ¼M0  M2  M4  M5  M6
f ðx; y; zÞ ¼pMð0; 2; 4; 5; 6Þ

(b) f ðx; y; zÞ ¼ p mð0; 3; 6; 7Þ

f 0 ðx; y; zÞ ¼p mð1; 2; 4; 5Þ
Complement 0
f ðx; y; zÞ ¼m1  m2  m4  m5
Using De Morgan’s theorem

f ðx; y; zÞ ¼M1  M2  M4  M5 ¼ M1 þ M2 þ M4 þ M5
f ðx; y; zÞ ¼m1 þ m2 þ m4 þ m5
X
f ðx; y; zÞ ¼ mð1; 2; 4; 5Þ:

Example 6.25 Obtain the simplified expression in sum of product for the fol-
lowing Boolean functions using K-map.
(i) f ¼ xyz þ xyz Pþ xyz þ xyz
(ii) f ðx; y; zÞ ¼ mð0; 2; 4; 5; 6Þ
6.13 Simplification in Sum of Product (Sop) Form 301

Solution
(i) f ¼ xyz þ xyz þ xyz þ xyz
K-map representation for this expression is

In the K-map, the right corner and left corner make a square and the common
term is x z. In the middle square, the common term is yz. Hence, combining the
above two, the simplified expression is

f ¼ xz þ yz

X
f ðx; y; zÞ ¼ mð0; 2; 4; 5; 6Þ ¼ m0 þ m2 þ m4 þ m5 þ m6
(ii)
f ðx; y; zÞ ¼xyz þ xyz þ xyz þ xyz þ xyz

K-map representation for this expression is

In the K-map, combining the four adjacent square in the first and last columns,
the common term is z. The two squares give the common term x y.
Hence, the simplified expression is

f ðx; y; zÞ ¼ z þ xy

f ðx; y; zÞ ¼ z þ xy
302 6 Switching Theory and Logic Design (STLD)

Example 6.26 Given the following truth table:

x y z f1 f2
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

(a) Express f1 and f2 in product of maxterms.

(b) Obtain the simplified function in SOP form using Cap K-map.
Solution (a) From truth table, we have

f1 ¼xyz þ xyz þ xyz þ xyz ¼ m1 þ m2 þ m4 þ m7

* f1 ¼m0 þ m3 þ m5 þ m6

Using De Morgan's theorem

f1 ¼m0 þ m3 þ m5 þ m6
f1 ¼m0  m3  m5  m6
f1 ¼M0  M3  M5  M6

Or f1 ¼ ðx þ y þ zÞ  ðx þ y þ zÞ  ðx þ y þ zÞ  ðx þ y þ zÞ
Similarly, form truth table, we have

f2 ¼xyz þ xyz þ xyz þ xyz

f2 ¼m3 þ m5 þ m6 þ m7
f2 ¼m0 þ m1 þ m2 þ m4

Using De Morgan’s theorem

f20 ¼m0 þ m1 þ m2 þ m4
f2 ¼m0  m1  m2  m4
f2 ¼M0  M1  M2  M4

From truth table f2 ¼ ðx þ y þ zÞ þ ðx þ y þ zÞ  ðx þ y þ zÞ  ðx þ y þ zÞ

6.13 Simplification in Sum of Product (Sop) Form 303
X
(b) f1 ðx; y; zÞ ¼ m1 þ m2 þ m4 þ m7 ¼ mð1; 2; 4; 7Þ

f1 ðx; y; zÞ ¼ xyz þ xyz þ xyz þ xyz

K-map representation

The above K-map cannot be minimized since no pair is possible

) f1 ðx; y; zÞ ¼xyz þ xyz þ xyz þ xyz

Similarly f2 ðx; y; zÞ ¼m3 þ m5 þ m6 þ m7
X
f2 ðx; y; zÞ ¼ ð3; 5; 6; 7Þ
f2 ðx; y; zÞ ¼xyz þ xyz þ xyz þ xyz

K-map representation

Two vertical squares reduce to yz

Two horizontal squares reduce to xy
The one separate square is x yz
Therefore, the simplified expression is

f2 ðx; y; zÞ ¼ yz þ xy þ xyz:

Example 6.27 Convert the hexadecimal no. (1 CD  2A) to binary and decimal
numbers.
Solution (i) Hexadecimal to binary
304 6 Switching Theory and Logic Design (STLD)

Hex No. = 1 CD · 2A
1 C D · 2 A (Hex)
↓ ↓ ↓ ↓ ↓
0001 1100 1101 · 0010 1010 (Binary)

Hence, (1CD  2A)16= (0001 1100 1101  00101010)2

(ii) Hexadecimal to decimal

Hex No: ¼ 1 CD  2A

First we note that C stands for 12 in decimal, D stands for 13 in decimal and A
stands for 10 in decimal.

) 1CD  2A ¼ 1
162 þ C
161 þ D
16 þ 2
161 þ A
162

2 1
1CD  2A ¼256 þ 12
16 þ 13
1 þ þ 10

16 256
¼256 þ 192 þ 13 þ 0:125 þ 0:039
ð1CD  2AÞ16 ð461  164Þ10 :

Example 6.28 Convert the binary number (1011.011) into octal and hexadecimal
numbers.
Solution (i) Binary to octal:

Given Binary number ¼ 1011  011

10 11  011
001 011  011
1 3  3

* ð1011:011Þ2 ¼ ð13:3Þ8

(ii) Binary to hexadecimal

Given Binary number ¼ 1011  011

10 11  01 10
B 6

ð1011:011Þ2 ¼ ðB:6Þ16 :

Example 6.29 Add and subtract without converting the following two numbers.
6.13 Simplification in Sum of Product (Sop) Form 305

ð7571Þ8 and ð4176Þ8

Solution
The given numbers are (7571)8 and (4176)8.
Addition

1 1← carry
(7 5 7 1)8
(4 1 7 6)8
(1 3 7 6 7)8

Therefore, ð7571Þ8 þ ð4176Þ8 ¼ ð13767Þ8 .

Subtraction
(7 5 7 1)8
(4 1 7 6)8
(3 3 7 3)8

Therefore, ð7571Þ8  ð4176Þ8 ¼ ð3373Þ8 .

Example 6.30 Add and subtract the following two numbers without converting
into decimal number.

ð432Þ5 and ð013Þ5

Solution Since base is 5, therefore on simple adding if no. exceeds 4, then, it

will get converted into base 5.
Addition
432
013
1000

Therefore, ð432Þ5 þ ð013Þ5 ¼ ð1000Þ5 .

Subtraction
306 6 Switching Theory and Logic Design (STLD)

432
– 013
414

Therefore, ð432Þ5  ð013Þ5 ¼ ð414Þ5 :

Example 6.31 Convert the following numbers as indicated.
(i) (IBE)16 = ()8
(ii) (676) = ()2
(iii) (321) = ()10
Solution (i) (1BE)16

1 B E Hexadecimal
0001
|ffl{zffl} 1011
|ffl{zffl} 1110
|ffl{zffl} Binary

000
|{z} 110
|{z} 111
|{z} 110
|{z} Octal
0 6 7 6

So, ðIBEÞ16 ¼ ð676Þ8

Hence ðIBEÞ16 ¼ ð0676Þ8
6 7 6
ð676Þ8 
(ii) 110 111 110
ð676Þ8  ð110111110Þ2
ð321Þ4 ¼ 3
42 þ 2
41 þ 1
40
(iii)
¼ 48 þ 8 þ 1
Thus, ð321Þ4 ¼ ð57Þ10 :
Example 6.32 How an exclusive NOR gate can be obtained using NAND gate
only? Sketch the diag.
Solution An exclusive NOR gate is represented as

Here

Y= A B

Y = A · B + A·B
For EX-NOR gate, the truth table representation.
6.13 Simplification in Sum of Product (Sop) Form 307

A B Y = A  B + AB 
0 0 1
0 1 0
1 0 0
1 1 1

Representation of Ex-NOR using NAND gate only.

Now
Y ¼ðA  BÞ  ðA  BÞ

Y ¼A  B þ ðA  BÞ

Using De Morgan’s theorem

Y ¼A  B þ A  B
Y ¼A  B
X
Y¼ NOR gate:

Example 6.33 Simplify FðABCDÞ ¼ ABC þ BCD þ ACD þ AB þ A by using K-

map.
Solution The given expression is FðABCDÞ ¼ ABC þ BCD þ ACD þ AB þ A.
The K-map of the given expression is ahead:
308 6 Switching Theory and Logic Design (STLD)

Hence, the simplified function is given as FðABCDÞ ¼ A þ B:

Example 6.34 Simplify Fða; b; cÞ ¼ ab þ bc þ ca using K-map.
Solution The given function is F ¼ ab þ bc þ ca.
Since this is a SOP form consisting of a three literals (a, b, c), it can be converted
into standard SOP form as under:

F ¼ab þ bc þ ca
F ¼ðc þ cÞab þ bcða þ aÞ þ caðb þ bÞ ½x þ x ¼ 1
F ¼abc þ abc þ abc þ abc þ abc þ abc
F ¼011 þ 010 þ 101 þ 001 þ 110 þ 100
F ¼3 2 5 1 6 4
F ¼m3 þ m2 þ m5 þ m1 þ m6 þ m4
X
F¼ mð3; 2; 5; 1; 6; 4Þ
6.13 Simplification in Sum of Product (Sop) Form 309

Therefore, simplified form is

Fða; b; cÞ ¼ ac þ bc þ ab:

Example 6.35 Convert 2410 to binary.

Solution The highest power of 2 not greater than 24 is 24 = 16.
Take 16 from 24 to leave 8.
The highest power of 2 not greater than 8 is 23 = 8.
Take 8 from 8 to leave 0.
The binary for 2410 is
24 + 23 equivalent to 11000

Thus; 2410 ¼ 110002

This approach can easily lead to mistake, principally because we can overlook
the powers which have zero digits. An alternative which is more reliable is
repeatedly to divide the decimal number by 2, the remainder indicating the
appropriate binary digit. This is known as the repeated division by 2 method.
Example 6.36 Convert 2410 to binary.
Solution

2 24 Remainder 0 0 Least significant digit (LSB)

2 12 Remainder 0 0
2 6 Remainder 0 0
2 3 Remainder 1 1
2 1 Remainder 1 1 Most significant digit (MSB)
0

Thus,
2410 ¼ 110002 :

Example 6.37 Convert 3310 to binary.

310 6 Switching Theory and Logic Design (STLD)

Solution
2 33 Remainder 1 1 (LSB)
2 16 Remainder 0 0
2 8 Remainder 0 0
2 4 Remainder 0 0
2 2 Remainder 0 0 (MSB)
2 1 Remainder 0 1
0

Thus,
3310 ¼ 1000012 :

Example 6.38 Add the binary number 1010 and 80110.

Solution
1 1 ← Carry
1010
0110
1 0 0 0 02

Example 6.39 Add the decimal number 19 and 9 by binary means.

Solution
1 1 ← Carry
10011 19
01001 9
11100 ≡ 28 10

Example 6.40 Add the decimal number 79 and 31 by binary means.

Solution
11111 ← Carry
1001111 79
0011111 31
1 1 0 1 1 1 02 ≡ 11010
6.13 Simplification in Sum of Product (Sop) Form 311

Example 6.41 Subtract 010112 from 110012.

Solution
11001
01011
0 1 1 1 02

Example 6.42 Add 9 and 3 by means of signed binary nos.

Solution
00001001 +9
00000011 +3
00001100 + 12

The first bit is 0, and hence, the no is + ve as expected.

Example 6.43 Add –9 and + 3 by means of signed binary nos. To represent –9,
we take the 2's complements thus.
Solution
11110111 –9
00000011 +3
11111010 –6

The sum is –ve since the first bit is 1. It is in 2’s complement form, and hence, its
magnitude is 0000110 which is 6, and hence, the sum is –6.
Example 6.44 Add –9 and –3 by means of signed binary nos.
Solution
11110111 –9
11111101 –3
Carry → 1 1 1 1 0 1 0 0 – 12

In this solution, we discard the carry bit. The no is (–)ve and its magnitude in
true binary form is 0001100 giving a decimal no. of –12.
Example 6.45 Add signed numbers 00001000, 00011111, 00001111 and
00101010.
312 6 Switching Theory and Logic Design (STLD)

Solution
For convenience, the decimal equivalent numbers appear in the right-hand
column below. 00001000 8
00011111 Ist sum 31
00100111 39
00001111 +15
00110110 2nd sum 54
00101010 +42
01100000 3rd sum 96

Example 6.46 Subtract + 9 from + 12.

Solution
00001100 + 12
11110111 –9 (2's Complement)
00000011 +3

Discard the carry, and we see that the number is positive with a magnitude of 3,
i.e., the outcome is + 3.
Example 6.47 Subtract + 19 from –24.
Solution
11101000 – 24
11101101 – 19
111010101 – 43

Discard the carry and we see that the number is (–)ve with a magnitude of 43,
i.e., the outcome is – 43.
Example 6.48 Convert the actual numbers (236)8 to decimal.
Solution

ð236Þ8 ¼ 2
82 þ 3
81 þ 6
80
¼ 2
64 þ 3
8 þ 6
1
¼ 128 þ 24 þ 6
¼ ð158Þ10

Each octal digit would require to be replaced by three binary digits.

6.13 Simplification in Sum of Product (Sop) Form 313

Example 6.49 Convert (125)8 to binary.

Solution The binary for the first digit is 001
for the second digit is 010.
for the third digit is 101.
Hence, ð125Þ8 ¼ ð001010101Þ2 in binary
Example 6.50 Convert decimal 6735 to binary.
Solution

2 6735
2 3367 → 1
2 1683 → 1
2 841 → 1
2 420 → 1
2 210 → 0
2 105 → 0
2 52 → 1
2 26 → 0
2 13 → 0
2 6 → 1
2 3 → 0
2 1 → 1
0 → 1
673510 = (1101001001111)2

Example 6.51 An electrical control system uses three positional sensing devices,
each of which produce one output when the position is confirmed. These devices
are in to be used in conjunction with a logic network of NAND and OR gates, and
the output of network is to be 1 when two or more of the sensing devices are
producing signals of I. Draw a network diagram of a suitable gate arrangement.
Solution If we consider the possible combinations which satisfy the necessary
conditions, it will be observed that there are four, i.e., any two devices or all three
devices providing the appropriate signals, then.
314 6 Switching Theory and Logic Design (STLD)

F ¼ A  B CþA B  CþA  B  CþA  B  C

The term A. B. C can be repeated as often as desired, hence

F ¼ A  B  CþA  B CþA B  CþA  B  CþA  B  CþA  B  C

Using the second distributive rule

F ¼ A  B  ðC þ CÞ þ A  CðB þ BÞ þ B  C  ðA þ AÞ

but applying the identity A þ A ¼ 1 B þ B ¼ 1; C þ C ¼ 1.

Hence F ¼ A  B þ B  C þ C  A
The network which would effect this function is shown in above figure.
Example 6.52 Draw the ckt. of gates that could affect the function.

F ¼ A  BþA  C

Simplify this function and hence redraw the ckt. that could affect it.
Solution The gate ckt. based on the original function is shown in this figure.
6.13 Simplification in Sum of Product (Sop) Form 315

Using De Morgan’s theorem

F ¼ A  BþA  C
¼ABAC
¼ A  B  A  C ðAssociative ruleÞ
¼ABC

The simplified ckt. is shown in following figure.

Example 6.53 Draw the ckt. of gates that would affect the function.

F ¼ AþB  C

Simplify this function and hence redraw the ckt. that could affect it.
Solution The gate ckt. based on the original function is shown in above figure
using De Morgan’s theorem.

F ¼ AþB  C
¼ A  ðB  CÞ
¼ A  ðB þ CÞ
316 6 Switching Theory and Logic Design (STLD)

This can be realized by the network shown in above figure, which shows that,
rather than there being a saving, we have involved the same number of gates with a
greater number of invertices.
Example 6.54 Draw a logic in circuit corporating any gates of your choice, which
will produce an output 1 when its 2 and I/p’s are different. Also draw a logic ckt.
incorporating only NOR gates, which will perform the same function.
Solution For such a requirement, the function takes the form

F ¼ A  BþA  B

This is the not equivalent function, and the logic ckt. is shown in the figure given
below.

This can be converted directly into NOR logic gate circuits, as shown in in the
figure given below. Examination of the circuitry shows that two pairs of NOR gates
and redundant since the output of each pair is the same as its input.
6.13 Simplification in Sum of Product (Sop) Form 317

Example 6.55 Draw ckts. which will generate the function.

F ¼ B  ðA þ CÞ þ A  B

Using
ðaÞ ¼NOR gates
(b) = NAND gates

Solution Given function

F ¼ B  ðA þ CÞ þ A  B
¼ B  AþB  CþA  B ðSecond distributive ruleÞ
¼ A  ðB þ BÞ þ BC ðSecond distributive ruleÞ
¼ AþB C ðFirst rule of complementationÞ

(a) For NOR gates complement of function is

F ¼ AþB  C
¼ A  ðB  CÞ ðDeMorgan0 s theoremÞ
¼ A  ðB þ CÞ ðDeMorgan0 s theoremÞ
¼ A BþA  C ðSecond distributive rule)

A ⋅ B and A  C are generated separately giving the ckt. shown in the figure.

(b) For NAND gates

F ¼ AþB  C
318 6 Switching Theory and Logic Design (STLD)

I/p’s to the final NAND gates are

A¼A and B  C ¼ BþC

B + C has to be generated separately, giving the ckt. shown in the figure.

F ¼ AþB  C

Example 6.56 Multiply the binary numbers 1101 and 0101.

Solution
1101
0101

1101
0000×
1101××
0000×××

1 1 1 1
1000001

Hence, 1101
0101 ¼ 1000001.

Example 6.57 Multiply the decimal numbers 27 and 10.
6.13 Simplification in Sum of Product (Sop) Form 319

Solution 11011 27
1010 10

11011
1 1 0 1 1

1 1 1
100001110 = 270

Example 6.58 Multiply 4510 by 2510 using binary means.

Solution
101101 45
11001 25
101101
101101
110 010101
1 0 1 1 0 1
10001100101 ≡ 1125

Example 6.59 Divide 6310 by 910 by means of binary numbers.

Solution

6310 ¼ 1111112

910 ¼ 10012

Divisor

111 Quotient
1001 111111 Dividend
1001↓
01101
10 0 1
01001
1 0 0 1
0 0 0 0 Remainder
320 6 Switching Theory and Logic Design (STLD)

Hence 111111 1001 ¼ 111

and 6310 910 ¼ 710
In this case, there was no remainder since 9 divides exactly into 63.
Example 6.60 Divide 6110 by 910 by means of binary numbers.
Solution

6110 ¼ 1111012

910 ¼ 10012

Divisor

110 Quotient
1001 111101 Dividend
1001↓
01100
10 0 1
00111 Remainder

Hence 111101 1001 ¼ 110 remainder 111 and

6110 910 ¼ 610 remainder 710

Example 6.61 Determine the 2's complement of 11011002 by applying the 1's
complement.
Solution

1111111  1101100 þ 1 ¼ 0010011 þ 1

¼ 0010100

An alternative method of finding the 2's complement is as follows:

1. Start with the LSB and moving left, write down the bits as they appear up to and
including the first 1.
2. Continuing left, write the 1's complement of the remaining bits.

Example 6.62 Determine the 2's complement of 1101100 directly. Split the no. to
the left of the lowest 1.
6.13 Simplification in Sum of Product (Sop) Form 321

Solution
1101 change (invert) 0010.
100 no change 100.
Hence, 2’s complement of 1101100 = 0010100.
Example 6.63 Determine the decimal value of the signed binary no. 10011010.
Solution
The weights are as follows

26 25 24 23 22 21 20
0 0 1 1 0 1 0

Summing the weights

16 þ 8 þ 2 ¼ 26

The sign bit is 1, therefore the decimal no. is – 26.

Summary
1. Number system: Number systems are decimal, binary, octal and hexadecimal
which have bases 10, 2, 8 and 16. The digits used are for decimal are 0 to 9,
binary 0 and 1, octal 0 to 7, hexadecimal 0 to 9 and A to F. Binary digit is
known as bit.
2. Conversion of bases:
(i) Conversion from decimal to binary, decimal to octal and decimal to
hexadecimal is done through division by the base number in which it is
being converted to. The first remainder is least significant digit and the
last remainder is last significant digit.
(ii) Conversions from binary to decimal, octal to decimal and hexadecimal to
decimal are obtained by a sum of various digits multiplied by their
respective weights.
(iii) Conversion from binary to octal and hexadecimal by making groups three
bits and four bits, respectively from right side of the binary number.
Subsequently, these groups are converted into the digits of respective
bases.
(iv) Conversion from octal and hexadecimal to binary is obtained by con-
verting each digit to itsthree3-bit and four-bit binary, respectively.
(v) Conversion of hexadecimal to octal is done by converting each digit to its
binary equivalent and binary equivalent is grouped with three bits each
starting from LSB. The groups are converted into octal.
(vi) Fractional binary part conversion to fractional decimal part is obtained by
a sum of various digits by the respective weights –2–1, 2–2, 2–4, …, 2–n.
322 6 Switching Theory and Logic Design (STLD)

(vii) Fractional decimal number part conversion to fractional binary part is

obtained by multiplying fractional decimal number by continued multi-
plication by 2 and noting down carry. First carry is MSB, and the last
carry is LSB.
3. Binary Coded Decimal: Each digit of decimal is converted into four binary
bits, and group separation is maintained.
4. Addition of Binary Numbers: Digits are added from LHS, i.e., LSB, and carry
is taken to RHS for addition.
5. Subtraction of Binary Numbers: Digits are subtracted from LHS, i.e., LSB,
and digits are borrowed from RHS if needed.
6. Logic Gates: The basic logic gates are AND, OR and NAND and NOR logic
gates are universal gates because any gate can construct with these gates. Logic
gates operate in two conditions on–offtrue/false/high-low/1–0 bistates.
7. Logic Operators and Theorems:
Logic operators
OR F ¼ AþB
AND F ¼AB
NOT F¼A
Cumulative law A þ B ¼B þ A
A  B ¼B  A
Associative law A þ ðB þ CÞ ¼ðA þ BÞ þ C
A  ðB  CÞ ¼ðA  BÞ  C
Distributive law A þ B  C ¼ðA þ BÞ  ðA þ CÞ
A  ðB þ CÞ ¼A  B þ A  C
De Morgan’s law A  B  C ¼A þ B þ C
A  B  C ¼A þ B þ C

8. Boolean Algebra: It implements operations of a system of logic required for

digital logics. Boolean algebraic statements use logic gates. These statements
can take the form of algebraic equations, logic variables may have only two
values 0 or 1.
9. Canonical Forms: If each term of a logic expression contains all variables,
then it a called a canonical form. Canonical expression can be in sum of product
(SOP) form, and each product term is known as minterm. Similarly, canonical
expression can be in product of sums (POS) form, and each sum term is known
as maxterm.
10. K-map: It is a graphical representation of fundamental products in a truth table.
It requires number of squares in a rectangle or squares. Each square represents
as minterm. A K-map has 2n squares for n variables.
6.13 Simplification in Sum of Product (Sop) Form 323

11. Simplification of Boolean Expression Using K-map: Squares of showing 1

are combined to simplify, and sum of product (SOP) form is used. In omple-
mentary case, squares showing 0 are combined to simplify, and product of sums
(POS) form is used.
Exercises

6:1. Write the difference in Boolean algebra and ordinary algebra.

6:2. Write and prove:
(i) Involution theorem.
(ii) Absorption theorem.

6:3. How can you connect a NAND gate to make on inverter?

6:4. What are basic logic gates and what are universal logic gates?
6:5. Make the EX-OR gate with minimum number of NAND gates.
6:6. What are Boolean postulates? State them.
6:7. Construct AND gate, NAND gate and OR gate with help of NOR gate.
6:8. What is the difference between canonical form and standard form? Also
write the De Morgan's theorem.
6:9. What is a two inputs NAND gate called universal gate?
6:10. State and prove De Morgan's theorem.
6:11. Using 10’s complement, subtract 72532–3250. [Ans. 69282]
6:12. Use 2’s complement and 1’s complement to preform M–N where
M = 1010100 and M = 1000100.
[Ans. 0010000, 0010000].
6:13. Convert the following decimal numbers to binary:
(i) 12.0625 (ii) 104 (iii) 673.23 (iv) 1998
[Ans. (i) (1100.0001)2, (ii) (10011100010000)2, (iii) (1110110010011
1010111)2, (iv) (11111001110)2]
6:14. Convert the following binary numbers to decimal:
(i) 10.10001 (ii) 101110.0101 (iii) 1101101.111
[Ans. (i) (2.53125), (ii) (46.3125), (iii) (109.875)]
6:15. Convert decimal 255.225 to binary, octal and hexadecimal.
[Ans. (11100001.0011100)2]
[Ans. (341.16314)8 (E1.39)16]
6:16. Convert 2AC5. D to octal.
[Ans. (25305.64)8]
6:17. Obtain 1's and 2's complement of 1010101, 0111000.
[Ans. (i) (0101010, 1000111), (ii) (0101011, 1001000)]
324 6 Switching Theory and Logic Design (STLD)

6:18. Obtain 9's to 10's complement of 13579, 099001.

[Ans. (i) (45470, 49149), (ii) (86421, 90100)]
6:19. Find 10's complement of (935)11.
[Ans. (8873)]
6:20. Determine the value of X in the following equation:
(11001)2 = X 10 [Ans. X = 25]
6:21. Convert hexadecimal B5A and 32F in to decimal no.
[Ans. (i) 2906 (ii) 814]
6:22. Convert following binary numbers into hexadecimal nos.
(i) 11010110 (ii) 11111001[Ans. (i) D6 (ii) F9 ]
6:23. Convert (100101110. 11101)2 to hexadecimal.
[Ans. (12E . E8)16]
6:24. Convert decimal no. 15, 65 into octal nos.
[Ans. (i) 1510 = 178, (ii) 6510 = 1018].
6:25. Convert (1001)2 to Gray code.
[Ans. 11011]
6:26. Convert Gray code no (11010) into binary no.
[Ans. 10011]
6:27. Convert decimal no. 245 to binary coded decimal (BCD).
[Ans. 001001000101].
6:28. Represent the decimal no. 8620 (a) in BCD (b) in X-3 in 8421 code (d) as a
binary number.
[Ans. (a) (1000011000100000)BCD, (b) (1011100101010011)X-3,
(c) (1110110000100000)8421, (d) (10000110101100)2]
6:29. Obtain the weighted binary code for the basic digits using weights of 8421.
[Ans. 0 ! 0000
1 ! 0001
2 ! 0010
3 ! 0011
4 ! 0100
5 ! 0101
6 ! 0110
7 ! 0111
8 ! 1011
9 ! 1100
10 ! 1101
11 ! 1110]
6:30. Write (13)10 in binary term and BCD term.
 6.13 Simplification in Sum of Product (Sop) Form 325

[Ans. (i) (13)10 = (1101)2, (ii) (00010011)BCD]

6:31. Assign a binary code in some orderly manner to the 52 playing cards. Use
mini no. of bits.
[Ans. (2 bits for suit, 4 bits for no. J = 1011, Q = 1100 and K = 1101)]
6:32. Write the logic equation for the output P in terms of I/p's A, B, C and D.
[Ans. P = (A + B) . C + D]
6:33. What is the logic state of Y (see. in fig.) when A, B, C, D are
(i) 0000 (ii) 0110 (iii) 1011 (iv) 1110 (v) 1111[Ans. 0, 0, 1, 1, 0]

6:34. Add the following binary nos.

(i) 101010 and 110110 (ii) 110110 and 111100[Ans. 110000, 1110010]
6:35. Express the following functions in a sum of minterm and product of maxterms.
(i) F(x, y, z) = 1 (ii) (A, B, C, D) = D ⋅ ( A + B) + B ⋅ D.
[Ans. (i) There is no maxterm in it, (ii) Max. terms are = p(0, 2, 4, 6, 8, 10, 12,
4)]
6:36. Convert the following others canonical terms.
(a) f (x, y, z) = R(1, 3, 7)
(b) f (x, y, z) = p(0, 3, 6, 7)
[Ans. (a) = p(0, 2, 4, 5, 6), (b) = R(1, 2, 4, 5)]
6:37. Obtain the simplified expression in sum of products for the following Boolean
function using K-map.
(i) f ¼ xyz þ xyz þ xyz þ zyz
(ii) f (x, y, z) = R m(0, 2, 4, 5, 6)
(iii) f (w, x, y, z) = R m(91, 2, 4, 5, 6, 8, 9, 12, 13, 14)
[Ans. (i) f ¼ xz þ yz, (ii) f ¼ z þ xy , (iii) f ¼ y þ wz þ xz].
6:38. For the following truth table:

x y z f1 f2
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
(continued)
 326 6 Switching Theory and Logic Design (STLD)

(continued)
x y z f1 f2
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

(a) Express f1 and f2 in product of maxterm.

(b) Obtain the simplified function in SOP form using K-map.
(c) Obtain the simplification function in POS form using K-map.
[Ans. (a)f1 ¼ M0  M3  M5  M6 ; f2 ¼ M0  M1  M2  M4 , (b) SOP ¼ yz þ xy
þ xyz; ðcÞ POS ¼ ðx þ zÞ  ðx þ yÞ  ðy þ zÞ.
6:39. Simplify each of the following Boolean function (+) using the do not care
condition (d) in (i) sum of products and (ii) product of sums.
[Ans. (i) (i)SOPF ¼ AC þ BDPOSF ¼ ð~
B þ CÞ  AðC þ DÞ, (ii) SOPF ¼ XZ þ
WZPOSF ¼ ðX þ ZÞðW þ ZÞ],
Chapter 7
Electronics Instruments

Analog instruments are rapidly being replaced by digital instruments.

Measurements of voltage, current, resistance phase and frequency are the param-
eters of interest. Digital voltmeter and digital multimeter will be considered, and
cathode ray oscilloscope (CRO) will be considered.
A digital instrument building block is shown in Fig. 7.1 Analog signal is con-
verted into digital signal for being measured by digital technique.
The display block may be analog or digital in nature. If an analog display is
needed, a digital-to-analog converter will be used.

7.1 Digital Voltmeters (DVMs)

Digital voltmeters convert analog voltage signals into a digital output signal. This
digital output signal is displayed on the front panel. Thus, DVMs have speed of
measurement, accuracy, automation and programming feasibility. It may be noted
that analog voltmeters have pointers and continuous scale which are prone to
human errors and parallax errors. But, DVMs are free from such errors. DVMs are
small in size and power requirement and have reduced prices due to development of
ICs. There are several techniques of converting analog-to-digital signal; therefore,
DVMs are classified based on these methods. Ramp-type DVMs and staircase-
ramp DVMs will be considered here.

7.1.1 Ramp-Type DVMs

Linear ramp technique measures time taken to rise zero volt to the level of the input
voltage or to decrease from the level of voltage to zero volt. An electronic
time-interval counter is used to measure the time interval. The time interval is
© The Author(s), under exclusive license to Springer Nature Switzerland AG 2022 327
O. N. Pandey, Electronics Engineering,
https://doi.org/10.1007/978-3-030-78995-4_7
328 7 Electronics Instruments

Fig. 7.1 Digital instrument building block

displayed as number of digits on a display. Figure 7.2 shows voltage-to-time

conversion. A negative ramp voltage is initiated at the start of the measurement.
This ramp voltage is continuously checked for first and second coincidences. First
coincidence is equal to the voltage to be measured, and the second is equal to zero.
The time interval between the first and second coincidence is measured by counting
the clock pulses by electronic counter. This pulse count is the direct measure of the
input voltage.
Figure 7.2 shows the block diagram of a ramp-type DVM. The dc voltage to be
measured is input to the ranging and attenuator which output different ranges of
measurement. The rate of measurement cycles is initiated by the “sample-rate
multivibrator (MV).” A control on the front panel adjusts the oscillator of MV for
few cycles per second to as high as 1000 or ever more.
An initiating pulse to the “ramp generator” for starting the ramp voltage is
provided by the “sample-rate MV.” The ramp voltage is fed to both the “input
comparator” and “ground comparator.” At the same moment, the sample-rate “MV”

Fig. 7.2 Voltage-to-time conversion

7.1 Digital Voltmeters (DVMs) 329

Fig. 7.3 Block diagram of a ramp-type DVM

gives reset pulse to the decode counting units (DCVs) making them to their state
and this removes momentarily “digital display.”
There is continuous comparator between the input voltage and the ramp voltage
by the “input comparator.” When the ramp voltage equals the voltage to be mea-
sured, then the comparator generate “start pulse” and this opens the “gate.” The
“clock-pulse generator”-generated pulse is allowed to go by the “gate” to the
“decode counting units (DCVs).” The “ground comparator” generates a “stop
pulse” when the continuous reduction of the ramp voltage with respect to time with
ground potential at 0 V. This closes the “gate.” The number of pulses passed
through the “gate” is totalized by the “DCVs.” The measured input voltage can be
seen on the “digital display” unit (Fig. 7.3).

7.1.2 Staircase-ramp DVMs

In this case, the voltage to be measured (Vin) is compared with an internally gen-
erated “staircase-ramp voltage.” Vin is converted to a BCD-code representation
which is subsequently decoded and displayed on a display of digital type.
As an example, a staircase-ramp DVM is shown is Fig. 7.4. It can be seen that
the block diagram has four digit which can be increased if needed.
Consider that for every step of digital input from BCD counter, the D/A con-
verter produces a step of 10 mV. Thus, the counters run up from 0000 to 9999 and
the staircase voltage (V) rises from 0 mV to 99,990 mV, i.e., 99.99 V, which is the
maximum input voltage of the DVM.
A 4.5 kHz relaxation oscillator generates. The clock pulses which are gated
through an AND gate into the counters. Comparator output (COMP) signal enables
the AND gate. LSD counter gives a carry pulse to the lens decode counter at every
tenth input pulse.
330 7 Electronics Instruments

Fig. 7.4 Four-digit staircase-ramp-type digital voltmeter

The lens counter gives its own carry to the hundreds counter and so on. The
display is held for time duration t1 for observation after the counting ends. As long
as the input Vin > staircase-ramp voltage V, the comparator output is 1 and the
AND gate is open for the clock pulses to pass the counters, the counter advances a
step and V goes up another 10 mV with each clock pulse. When V > Vin by a value
of 10 mV, COMP goes to 0 which disables the AND gate.
When COMP goes 0, it also triggers one-shot device OS1, whose output Q1
becomes 1, and it effectively holds the display for time duration t1. When Q1 input
to OS2 goes 0, it is triggered and causes Q2 to clear the A/D converter and BD
counters to the 0 state. The pulse is of duration (t2) about 10 ms. After the clearance
of D/A converter, Vin > V and whole counting process is repeated. Each reading is
displayed until new reading is completed.

7.2 Digital Multimeters (DMMs)

A digital multimeter is used for measurement of ac/dc voltage, ac/dc currents and
resistances. The basic circuit of a DMM is shown in Fig. 7.5.
7.2 Digital Multimeters (DMMs) 331

Fig. 7.5 Block diagram of a digital multimeter

The basic circuit is a dc digital voltmeter. Current is converted to voltage. DC

current is passed through a precision law shunt resistance, while ac current is
converted into dc by using rectifiers and filters. In the case of resistance mea-
surement, DMM includes a precision low current source which is applied across the
resistance to be measured. The dc voltage so developed is digitized and displayed as
ohms. A typical DMM is shown in Fig. 7.6. It has power switch, function switch,
Hz/% select button, data hold button, relative button, select button, range hold
button, display, test leads, etc. Test leads have two test probes red and black, finger
guards and test pins, etc.

Fig. 7.6 A typical digital

multimeter
332 7 Electronics Instruments

7.3 Cathode Ray Oscilloscope (CRO)

The CRO allows the amplitude of electrical signals, whether they are voltage
current, or power to be displayed as a function of time. A block diagram of a
general purpose CRO is shown in Fig. 7.7.
CRO is comprised of CRT, vertical amplifier, delay line, time base, horizontal
amplifier, trigger circuit and power supply units.
Cathode ray tube (CRT) is basically an electron beam voltmeter. The electron
gun generates a narrow electron beam which is bombarded on the screen of the
tube. The screen is the external flat end of the glass tube which is chemically treated
to form a fluorescent screen. The screen glows at the point of collision, i.e., pro-
duces a bright spot. The electron beam is deflected at a constant rate relative of time
along the x-axis and is deflected along the y-axis in response to a stimulus such as
voltage. This produces a time-dependent variation of the input voltage. As the
electron has practically no weight, i.e., no inertia, the beam of electrons can be
moved to follow waveforms varying at a rate of millions of times/second. Thus,
electron beam faithfully follows rapid variations in signal voltage and trans a visible
path on the CRT screen. In this way, rapid variations, pulsations or transients are
reproduced, and the operator can observe the waveform as well as measure
amplitude at any instant of time.
Vertical amplifier is a wide band amplifier used to amplify signals in the vertical
section. Delay time is used to delay the signal for some time in the vertical sections.
Time base is used to generate the sawtooth voltage required to deflect the beam in
this horizontal section. Horizontal amplifier is used to simplify the sawtooth voltage

Fig. 7.7 Block diagram of a CRO

7.3 Cathode Ray Oscilloscope (CRO) 333

Fig. 7.8 A front control panel an CRO

before it is applied to horizontal deflection plants. Trigger circuit is used to convert

the incoming signal into trigger pulses so that the input signal and sweep frequency
can be synchronized. There are two power supplies, a –ve high voltage (HV) supply
and a +ve low voltage (LV) supply. These two voltages are generated in the CRO.
The +ve voltage supply is from +300 to 400 V. The –ve high voltage supply is
from –1000 to –1500 V. This voltage is passed through a bleeder resistor for
intensity, focus and positioning controls.
A front control panel of CRO is shown in Fig. 7.8. The boards and switches are
identified for each function of CRO.

7.4 Measurements Using CRO

7.4.1 Measurement of Voltage

A dc voltage to be measured is given to vertical defection plates. The displacement

of the spot on the screen is measured. The displacement multiplied by the deflection
sensitivity which gives the magnitude of dc voltage.
An ac voltage to be measured is also given to the vertical deflection plates. The
length of the straight line trace obtained on the screen is measured. This length is
multiplied with deflection sensitivity in V/cm giving the peak-to-peak value of the
334 7 Electronics Instruments

pffiffiffi
ac voltage. This value is divided by 2 2 giving the rms value of the ac voltage to
be measured.

7.4.2 Measurement of Current

Current is measured indirectly with the help of CRO. The current to be measured is
passed through a suitable known resistor. The voltage developed across the resistor
is measured using CRO. The voltage is divided by the resistance value which gives
the current value.

7.4.3 Measurement of Phase Difference

CRO can determine phase difference between two sine waves of the same fre-
quency. The two voltages are simultaneously applied to the two sets of deflection
plates. This gives the Lissajous pattern on the screen as an ellipse as shown in
Fig. 7.9.
Figure 7.9 is centered by adjusting the x-shift and y-shift controls. The intercepts
y1 and y2 are measured. The phase difference is given by:
y1
Phase difference; h ¼ sin1
y2

Fig. 7.9 Ellipse created in

measurement of phase
difference between two sine
waves
7.4 Measurements Using CRO 335

7.4.4 Measurement of Frequency

The ac voltage is displayed on the CRO, and measurement of its time period is done
using the calibrated time base. The frequency is calculated as the inverse of this
time period.
Time period of the ac waveform, T = number of divisions in one cycle division
Time

where T = time period of the ac save in sec. frequency, f ¼ T Hz.

1

Summary
1. The building blocks of any digital instruments are A/D converter, D/A con-
verter, single processing unit, analog display, digital display units, etc.
2. Digital voltmeters (DVMs) convert analog voltage signals into a digital output
signal which is displayed. There are various types of DVMs, and the important
ones are amp. type and staircase-ramp type.
3. Digital multimeters use electronic circuits, such as instrumentation amplifier to
amplify the voltage to be measured.
4. Digital multimeters are used to measure ac/dc voltages, ac/dc currents and
resistances. The building blocks are ac/dc alternators, A/D converter, digital
display, etc.
5. Cathode ray oscilloscope (CRO) is a very fast x – y plotter and is used to display
voltage wave forms. The “stylus” of the “plotter” is a luminous spot which
moves on the screen in response to the input voltages.
6. CRO is comprised of CRU, vertical amplifier, delay line, time box, horizontal
amplifier, trigger circuit about and power supply units.
7. Lissajous pattern is formed on the screen of a CRO, when two sine wave
voltages are simultaneously applied to the two sets of deflection plates. The
phase difference between the sine waves applied is determined from this pattern.
Exercises
7.1 What are the advantages of digital instruments over analog instruments?
7.2 Explain working principle of digital voltmeter with block diagrams.
7.3 What are the applications of a digital multimeter? Explain DMM working
principle with block diagram.
7.4 What are the uses of CROS? How is phase difference between two sine waves is
measured using a CRO?
7.5 Describe basic building blocks of a CRO and its working principle.
7.6 A sinusoidal voltage is applied to Y-input of a CRO. Its vertical amplifier
sensitivity is set at 1 V/cm. A straight line trace of length 6.2 cm is obtained on
the screen. What is the rms value of the sinusoidal voltage?
Chapter 8
PSPICE

8.1 SPICE

SPICE stands for Simulation Program with Integrated Circuit Emphasis. SPICE is a
general-purpose, open-source analog electronics circuit simulator. It is used in
integrated circuit and board-level design. This is for checking the integrity of circuit
designs. This also helps to predict circuit behavior. Simulating the circuit with
SPICE is the industry-standard way to verify circuit operation at the transistor level.
When board-level circuit design is bread boarded for testing, some circuit
properties may not be accurate compared to the final printed wiring board. Some
resistances and capacitances can often be estimated more accurately using SPICE
simulation. Circuit performance is affected by component manufacturing tolerances
and such informations are made available using SPICE.
Circuit simulation programs take a text netlist describing the circuit elements viz.
transistors, resistors, capacitors, etc. and their connections, then translate this
description into equations to be solved. These equations are nonlinear differential
algebraic equations. Implicit integration methods, Newton’s method and sparse
matrix techniques are used.
SPICE was developed at the Electronics Research Laboratory of the University
of California, Berkeley. Initially, SPICE was largely a derivative of the CANCER
program. CANCER was an acronym for “Computer Analysis of Nonlinear Circuit
Excluding Radiation.” SPICE inspired and served as a basis for many other circuit
simulation programs, in academia, in industry, and in commercial products.

8.2 PSPICE

PSPICE stands for Personal Simulation Program with Integrated Circuit Emphasis.
It is a SPICE analog and digital logic simulation program for Microsoft Windows.

© The Author(s), under exclusive license to Springer Nature Switzerland AG 2022 337
O. N. Pandey, Electronics Engineering,
https://doi.org/10.1007/978-3-030-78995-4_8
338 8 PSPICE

PSPICE belongs to Cadence Design Systems. PSPICE has evolved into an

analog mixed signal simulator and has developed toward more complex industry
requirements. It has features such as analysis of a circuit with automatic opti-
mization, encryption, a model editor, support for parameterized models,
auto-convergence and checkpoint restart, several internal solvers, a magnetic part
editor, etc.

8.3 Circuit Design and Analysis Using PSPICE

A creation and analysis of a simple MOSFET circuit in PSPICE is considered. The

circuit diagram given in Fig. 8.1 is to be built. The analysis helps to find the current
and the V voltage if the values of V and are given.
On the colored screen, all nodes are green, and all dialog box titles are purple.
Menu names are red and text boxes inside dialog boxes are orange.
Step I: Starting a New Circuit.
1. For launching of PSPICE, “Capture Student” by left clicking on “Start-PSPICE
Student-Capture Student.” This will launch PSPICE capture screen.
2. From the File menu, Choose New Project. Pop up of dialog box will happen.
3. Create a name for the project in the Project dialog box. Choose “Simple
NMOS” as the project name here. Also choose the type of project as “Analog or
Mixed A/D” is selected. In location, choose to store PSPICE files. Refer
Fig. 8.2.
4. Create PSPICE Project dialog box will pop up after clicking OK. Here, type of
project to be created is chosen.
5. After Creating PSPICE Project dialog box, the schematic window opens and the
libraries addition can be done.

Fig. 8.1 Circuit diagram

8.3 Circuit Design and Analysis Using PSPICE 339

Fig. 8.2 New project screen

STEP II: Adding Libraries.

If PSPICE is being used for the first time on the computer, the parts libraries need to
be added. Different libraries are needed for different types of circuits. Focus will be
on the libraries containing the parts which are needed.

1. Libraries addition can be done in one of two ways:

(a) Go to the Place menu and choose Part… see Fig. 8.3
(b) Click the icon from the icon bar on the right of the Capture window.
Point the mouse to each of these icons and the function of the pointed icon
will be displayed. Try to point these entire icons separately to get familiar
with them. These are short-cuts to menu paths which can be very useful in
the circuit design. Some useful icons are select, place part, place wire, place
net alias, place power, place ground, place off-page connector, etc. when the
icon bar does not appear on the right side, just left click anywhere in the
schematics window to make the icon bar appear. Refer Fig. 8.4

Fig. 8.3 Place menu

340 8 PSPICE

Fig. 8.4 Place part button

2. Place Part dialog box appears and one will have the option to add libraries.
3. There are extension.olb library files.
4. All the available libraries are selected: Left click on first library “abm,” then
press the “shift” key and simultaneously click on the last library “special.” All
the libraries can be selected as the one below. All the selected libraries will be in
blue shade. Then, click “open.”
The libraries used here are:
(a) Analog and analog_p libraries: Analog libraries are very similar to each
other which contain analog parts such as resistor R, capacitor C, inductance
L, etc. The resistors in the analog_p library use a 1 and 2 at each end of the
resistor to show the positive and negative ends of the resistor, i.e., 1 for
positive, 2 for negative.
(b) Breakout library: MOS transistor, bipolar transistor, etc. are included.
(c) Source library: Power sources, such as dc voltage Vdc, ac voltage Vac, Sine
wave voltage VSIN, etc. are included.
(d) A library to use grounds in the circuit needs to be added. Select the Ground
button from the icon bar on the right.
5. After choosing the Add Library… button, go to the same location as done to
add part libraries and add the source library.
Step III: Inserting Parts.
Parts are inserted to construct circuit. Circuit design is done in three subsets:
1. All the parts are inserted without considering their values.
2. The necessary rotation is made for the parts, and they are moved to appropriate
locations.
3. The necessary wire connections are made.
4. The values for all the parts set.
In the circuit, insertion of two dc voltage sources, one resistor, and one NMOS
are needed which is done as follows:
1. “Place part dialog box” is turned by using Place ! Part from the menu or using
the place part button on the icon bar.
2. In the libraries box, click on the source library. Scroll down to Vdc in the part
list and highlight it. The dialog box should look like as shown in Fig. 8.5
3. Clicking OK, leads to schematics screen, clicking schematics screen makes a dc
voltage insertion. Insert a second one by moving the mouse. Now, right click
8.3 Circuit Design and Analysis Using PSPICE 341

Fig. 8.5 Place part dialog box

Fig. 8.6 Addition of resistor

342 8 PSPICE

Fig. 8.7 Creation of NMOS

mouse and select “end mode” by left click. After finishing inserting the part of
“dc voltage source,” one can continue to insert other part.
4. To get to the place part dialog box again follow the procedure. ANALOG_P is
to be highlighted this time in libraries box and highlight R in the part list box.
The dialog box will look like as shown in Fig. 8.6.
5. In the place part dialog box click OK. Subsequently, click once on the
Schematics screen to insert a resistor.
6. Now, go to the place part dialog box one more time. Breakout in the libraries
box and also MbreakN3 in the part list box highlighted. The dialog box will
look like as shown in Fig. 8.7.
7. After clicking OK, click only once on the Schematics screen for insertion of
NMOS
8. From the icon bar, select the Place Ground button.
In the place ground dialog box, highlight CAPSYM under libraries by left click
to select. Also highlight GND under the symbol box. Subsequently, left click on
the “name” bar to change the name from “GND” to “0.” Now, change the name
“GND” to “0” to indicate that this is the reference ground voltage of the circuit.
This is “0” node in simulation.
9. Click OK and click once on the Schematics screen. Click “Select” icon in the
right icon bar. Schematics screen will have all of the parts as shown in Fig. 8.8.
8.3 Circuit Design and Analysis Using PSPICE 343

Fig. 8.8 Parts on the schematics screen

Fig. 8.9 Value insertion

Step IV: Wiring Circuit.

1. Rotate some parts if it is required. In the circuit one needs to rotate resistor R1.
Left click to select the resistor. A dashed line appears around the entire part in
“selecting” mode. It should look like as shown.
Right click on the resistor while it is highlighted and select rotate. Rotate the
resistor until it is vertical with 1 at the top and the 2 at the bottom.
2. Click “select” icon to enter “selecting” mode. Subsequently, left click on any
part one wants to move, and drag it to the right location and release the mouse
button. This can move the part to anywhere in the design.
344 8 PSPICE

Fig. 8.10 Positioned parts

3. Select the Place Wire button from the icon bar or go the place menu and select
wire. Left click the mouse on a point to start a wire in that point, then left click
the mouse on another point to draw a wire to connect both points. Right click
the mouse to select “end wire” if no more wire. Use wire to connect the resistor
and NMOS.
4. Once all the wire connections are over, select the numerical value of the resistor,
labeled 1 k as shown in Fig. 8.9. Double click on the numerical value (1 k).
Now, the display properties dialog box will open. Value box will display 1 k. In
the value box of the display properties dialog box, change the value of “1 k” to
“2 k” as shown.
5. To change the name of resistor R1 into “Rin,” one can double click on the name
“R1” region. This will pop up the “display properties” interface. One can change
the name from “R1” to “Rin” in the “Name: Part Reference” section. However,
the name as “R1” will be continued.
6. All the parts are positioned in a similar way as shown in Fig. All the parts are
positioned in a similar way as shown in Fig. 8.10.
7. The wire connections are done as shown in Fig. 8.10 and subsequently, follow
the diagram as shown in Fig. 8.11 for ground connection in the circuit.
8. Now, need is to set the values of the V1 and V2 voltage sources to values shown
in the circuit diagram. The value of V1 is 7 V and the value of V2 is 10 V.
Similar to change of the resistor values, change these values. Double click on
the voltage value and the “display properties” interface will pop up. Now, one
can change the voltage value. Make sure that the Vdc label is still after the
number in the value box before clicking OK in the display properties dialog box.
9. Now, some nodes can be named. To name the nodes of gate, drain and source of
transistor M1 as Gm1, Dm1, and Sm1, separately. The “Place Net Alias”
interface will pop up. Left click on the “place Net alias” icon bar. Input “Gm1”
in “Alias” line.
8.3 Circuit Design and Analysis Using PSPICE 345

Fig. 8.11 Ground connection

Fig. 8.12 Outcome of the

design

Subsequently “OK,” and left click the node of the gate of transistor M1, if this is
the node name. Now, the net alias of “Gm1” will be placed. Follow the similar
process to name other nodes. The outcome of the design will be as shown in
Fig. 8.12.
346 8 PSPICE

Step V: Setting the Parameters.

The MOSFET also has special parameters. The parameters to be set are SPICE
parameters for NMMOS and PMOS, also the width (W) and length (L) of each
transistor. To learn to set all of these parameters, consider to set the size of MOS
transistor M! as W = 10 micro m, and L = 1 micro m.
1. The width (W) and length (L) of the MOS transistor M1 will be set as first
step. Select highlight the NMOS to rotation of parts in step number 4. That
makes sure that the “select” button on right panel is clicked, the left click on
NMOS transistor to select. The color will change to red and a rectangle will
surround it. Subsequently, right click on NMOS transistor and select “edit
properties.”
2. Now, left click on the scrolling bar on the bottom and drag it to the right until L
is seen in the first row. Click in the box underneath it, corresponding to the row
labeled SCHEMATIC1:PAGE:M1. For 1 µm type 1e-6 in the box. Continue
scrolling to the right until W is seen in first row. For 10 µm type 10e-6 in the
box below.
Be sure to click apply before closing the property editor dialog box. This will
not close the dialog box, but it will ensure that the values you entered for the
NMOS length and width are saved. After clicking apply, one can use the X in
the upper right-hand corner to close the dialog box similar to closing a program.
3. To input the SPICE parameters for NMOS and PMOS transistor models,
highlight the NMOS transistor by left clicking to select it. Now, go to the edit
menu and select PSPICE model. The dialog box will open.
4. Model Mbreakn NMOS line is to be deleted and subsequently copy and paste
following SPICE NMOS model parameter:
* 1 um Level 3 models
*
* Don't forget the options scale=1u if using an Lmin of 1
* 1<Ldrawn<200 10<Wdrawn<10000 Vdd=5V
.MODEL Mbreakn NMOS LEVEL
+ TOX = 200E-10 =3
+ PHI = 0.7 NSUB = 1E17 GAMMA = 0.5
+ UO = 650 VTO = 0.8 DELTA = 3.0
+ KP = 120E-6 ETA = 3.0E-6 THETA = 0.1
+ RSH = 0 VMAX = 1E5 KAPPA = 0.3
+ XJ = 500E-9 NFS = 1E12 TPG = 1
+ CGDO = 200E-12 LD = 100E-9
+ CJ = 400E-6 CGSO = 200E-12
PB = 1
+ CJSW = 300E–12 MJSW = 0.5 CGBO = 1E-10
MJ = 0.5
8.3 Circuit Design and Analysis Using PSPICE 347

Fig. 8.13 Model editor dialog box

Now press menu “file-save” to save it. The asterisk after Mbreakn will disappear,
and the model editor dialog box will look like as shown in Fig. 8.13.
5. After saving, close the model editor box by choosing File ! Exit.
Step VI: Running the Analysis.
A new PSPICE simulation is created here, and subsequently, analysis is done.
1. Choose new simulation profile under the PSPICE menu. This opens the new
simulation dialog box. Type a name in this box for the simulation. Use of the
same name for the simulation is used.
2. The simulation setting dialog box will open after clicking create. Here, a time
domain (Transient) is to be done. All of the setting in the dialog box will be
correct as long as the type of analysis is correct. Setting of total simulation time
(TSTOP) to 10 ms, and the maximum step size as 0.01 ms is to be done in this
simulation.
3. For returning to schematic, click OK. To run the simulation, choose run from the
PSPICE menu or by choosing the play button from the icon bar at the top of the
screen.
4. Above opens the PSPICE analysis window. Now, for analysis of the output file,
to determine the I current and V voltage.
Step VII: Analyzing the Output File.
To observe the exact values of all the nodes voltages, one can return to the PSPICE
menu and select Bias Points _ > Enables Voltage Display or else, one can click on
the icon of “Enable Bias Voltage Display” on the top icon bar, as shown in
Fig. 8.14.
348 8 PSPICE

Fig. 8.14 Exact voltage of

the models

The V voltage is approximately equal to 1.501 V. This implies building the

circuit, running it and solving it. One can use different types of analyses to see when
the NMOS changes regions. More PSPICE can be learnt by trying out different
functions of PSPICE.

8.4 Simulation and Analysis of Common Emitter

Amplifier Using PSPICE

All schematics with the proper name is entered for title block. The schematic must
be drawn with proper layout and centered in the page. The part values for all
components are shown in the schematic.
.model Q2N2222 NPN(Is=15f Vaf=100 Bf=140 Ne=1.3 Ise=15f
+ Ikf=0.3 Xtb=1.5 Br=6 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=18p
+ Mjc=0.33 Vjc=0.70 Fc=0.5 Cje=22p Mje=0.33 Vje=0.70
+ Tr= 17.9p Tf=430p Itf=0.6 Vtf=1.7 Xtf=3 Rb=19)

Project name ce_amp is created. The single stage common emitter amplifier
schematic diagram is made as shown in Fig. 8.15.
After entry of Q2N2222:

CL on PSPICE Highlight Markers Highlight Advanced.

CR on the transistor.
CL on the transistor.
CR the CL on Edit the PSPICE Model.
The model values listed above are entered. The model editor is closed, and all
dialog box defaults are accepted.
8.4 Simulation and Analysis of Common Emitter Amplifier Using PSPICE 349

Fig. 8.15 Common emitter amplifier circuit

Simulation profile with name ce_amp is created. Selection is done out of ac

sweep/noise for the analysis type. Start frequency and end frequency are entered.
The screen is shown in Fig. 8.16.
CL on PSPICE Highlight Markers Highlight Advanced.
CL on db Magnitude of Voltage.
CL and place the marker at the node OUT Run the simulation.
In the Probe Window, CL on Plot.
CL on Axis Settings.
CL on Y Axis.
CL on User Defined in the Data Range section.
Change the range to 26 to 10.
CL on X Grid.
The check from Automatic is removed.
For Minor intervals between major select 10. CL on OK.
The output should be similar to as shown in Fig. 8.17.
The two critical frequencies are determined from the probe output. Probe output
is printed and probe is closed.
CL on the V and I buttons on the PSPICE toolbar.
The schematic will display the quiescent (dc) voltages and currents as shown in
Fig. 8.18
Calculation for verification purpose is done here. Figure 8.19 shows Thevenin
equivalent circuit.
350 8 PSPICE

Fig. 8.16 Simulation setting

Fig. 8.17 Frequency response

VTH = VCC[R2/(R1+ R2)]= 18V(10K/72K)= 2.5V RTH = R1|| R2= 86||r

b ¼ 140
V
BE = 0.7V
IE=[(VTH - VBE)/(RTH/(b+1))+ RE1A + RE1B] = (2.5V-0.7V)/(86.1/141+520)
IE= 3.097mA(3.061mA from PSPICE)
VB= 2.31V(2.264V from PSPICE) IC= 3.075mA (3.033mA from PSPICE)
VC= VCC-ICRC
VC= 9.697V(9.811V from PSPICE)
8.4 Simulation and Analysis of Common Emitter Amplifier Using PSPICE 351

Fig. 8.18 Quiescent (dc) voltage and (dc) Current

Fig. 8.19 Thevenin

equivalent circuit

Summary
1. SPICE stands for Simulation Program with Integrated Circuit Emphasis. SPICE
is a general-purpose, open-source analog electronics circuit simulator. It is used
in integrated circuit and board-level design. This is for checking the integrity of
circuit designs. This also helps to predict circuit behavior. Simulating the circuit
with SPICE is the industry-standard way to verify circuit operation at the
transistor level.
352 8 PSPICE

2. SPICE was developed at the Electronics Research Laboratory of the University

of California, Berkeley. Initially, SPICE was largely a derivative of the
CANCER program. CANCER was an acronym for “Computer Analysis of
Nonlinear Circuit Excluding Radiation.” SPICE inspired and served as a basis
for many other circuit simulation programs, in academia, in industry, and in
commercial products.
3. PSPICE stands for Personal Simulation Program with Integrated Circuit
Emphasis. It is a SPICE analog and digital logic simulation program for
Microsoft Windows. PSPICE belongs to Cadence Design Systems. PSPICE has
evolved into an analog mixed signal simulator and has developed toward more
complex industry requirements. It has features such as analysis of a circuit with
automatic optimization, encryption, a model editor, support for parameterized
models, auto-convergence and checkpoint restart, several internal solvers, a
magnetic part editor, etc.
Exercises Do simulation and analysis of the following circuits using PSPICE:
1. Low pass and high pass filter.
2. Half-wave and full-wave rectifier.
3. Frequency response of CS amplifier.
4. Frequency response of CC amplifier.
5. Verification of clippers.
6. Verification of clampers.
7. Design and verification of RC coupled amplifier.
8. Design and verification of voltage regulator.
9. Design and verification of attenuators.
10. Design and verification of differential amplifier.
11. Design and verification of logic gates.
Appendix A
Symbols, Abbreviations
and Diagrammatic Symbols

See Tables A.1, A.2, A.3, A.4, A.5, A.6 and A.7

Table A.1 Abbreviations for multiples and submultiples

Symbol Abbreviation Multiples
T tera 1012
G giga 109
M Mega or meg 106
k kilo 103
d deci 10–1
c centi 10–2
m milli 10–3
µ micro 10–6
n nano 10–9
p pico 10–12

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O. N. Pandey, Electronics Engineering,
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354 Appendix A: Symbols, Abbreviations and Diagrammatic Symbols

Table A.2 Miscellaneous symbols

Term Symbol
Approximately equal to ’
Proportional to /
Infinity ∞
Sum of R
Increment of finite difference operator Δ, d
Greater than >
Less than <
Much greater than 
Much less than 
Base of natural logarithms e
Common logarithm of x log x
Natural logarithm of x ln x
Complex operator (–1) j
Temperature h
Time constant T
Efficiency η
Per unit p.u.

Table A.3 Greek alphabet

Term Capital Lowercase
alpha A a
beta B b
gamma C c
delta Δ d
epsilon E e
zeta Z f
eta H η
theta H h
iota I i
kappa K j
lambda K k
mu M µ
nu N m
xi N n
omicron O o
pi P p
rho P q
sigma R r
tau T s
upsilon ! t
phi U u
chi X v
psi W w
omega Ω x
Appendix A: Symbols, Abbreviations and Diagrammatic Symbols 355

Table A.4 Electrical units

Quantity Quantity Unit Unit
symbol symbol
Admittance Y siemens S
Angular velocity x radian per second rad/s
Capacitance C farad F
microfarad µF
picofarad pF
Charge on quantity of Q coulomb C
electricity
Conductance G siemens S
Conductivity r siemens per meter S/m
Current
Steady or r.m.s. value I ampere A
milliampere mA
microampere µA
Instantaneous value i
Maximum value Im
Current density £ ampere per square meter A/m2
Difference of potential
steady or r.m.s. value V volt V
millivolt mV
kilovolt kV
Instantaneous value v
Maximum value Vm
Electric field strength E volt per meter V/m
Electric flux W coulomb C
Electric flux density D coulomb per square C/m2
meter
Electromotive force
Steady or r.m.s. value E volt V
Instantaneous value e
Maximum value Em
Energy W joule j
kilojoule kJ
megajoule MJ
watt hour Wh
kilowatt hour kwh
electronvolt eV
Force F newton N
Frequency f hertz Hz
kilohertz kHz
(continued)
356 Appendix A: Symbols, Abbreviations and Diagrammatic Symbols

Table A.4 (continued)

Quantity Quantity Unit Unit
symbol symbol
megahertz MHz
Impedance Z ohm Ω
Inductance, self L henry (plural, henrys) H
Inductance, mutual M henry (plural, henrys) H
Magnetic field strength H ampere per meter A/m
ampere turns per At.m
Magnetic flux U weber Wb
Magnetic flux density B tesla T

Table A.5 Magnetic units

Quantity Quantity symbol Unit Unit symbol
Magnetic flux linkage w Weber Wb
Magnetomotive force F ampere A
ampere turns At
permeability of free space or µ0 henry per meter H/m
Magnetic constant
Permeability, relative µr
Permeability, absolute µ
Permittivity of free space e0 farad per meter F/m
of Electric constant
Permittivity, relative er
Permittivity, absolute e
Power P Watt W
kilowatt kW
megawatt MW
Power, apparent S volt-ampere VA
Power, reactive Q var var
Reactance X ohm Ω
Reactive volt-ampere Q
Reluctance S ampere per weber A/Wb
Resistance R ohm Ω
microohm µΩ
megaohm MΩ
Resistivity q ohm meter Ωm
Speed, linear u meters per second m/s
Speed, rotational x radians per second rad/s
n revolutions per second rev/sec
(continued)
Appendix A: Symbols, Abbreviations and Diagrammatic Symbols 357

Table A.5 (continued)

Quantity Quantity symbol Unit Unit symbol
N revolutions per minute rev/min
microohm meter µΩ m
Susceptance B siemens S
Torque T Newton meter Nm
Volt-ampere – volt-ampere VA
kilovolt-ampere KVA
Wavelength k meter m
micrometer lm

Table A.6 Light units

Quantity Quantity Unit Unit
symbol symbol
Illuminance E lux lx
Luminance (objective L candela per square cd/m2
brightness) meter
Luminous flux U lumen lm
Luminous intensity I candela cd
luminous efficacy – lumen per watt lm/W

Table A.7 Section of graphical symbols from BS 3939

Description Symbol Description Symbol
Direct current or steady — Alternating
voltage
Positive polarity + Negative polarity —
Primary or secondary Battery of primary or
cell secondary cells
Fixed resistor Variable resistor

Resistor with moving contact

Filament lamp Crossing of conductor

Junction of conductors symbols on a diagram
(no electrical connection)
Double junction of Earth
conductors
Capacitor general Polarized capacitor
symbol
Winding Inductor and core
Transformer Ammeter

(continued)
358 Appendix A: Symbols, Abbreviations and Diagrammatic Symbols

Table A.7 (continued)

Description Symbol Description Symbol
Voltmeter Wattmeter

Galvanometer Motor

Generator Make contact (Normally open)

Break contact Rectifier

(normally closed)
Zener diode P-N-P transistor

N-P-N transistor N-channel JUGFET

P-channel JUGFET N-channel IGFET

P-channel IGFET Amplifier

Thyristor MOSFET

IGBT GTO

Binary logic units

AND OR
NOT NAND
NOR
Appendix B
Units and Conversion Factors

See Tables B.1, B.2

Table B.1 .
Quantity Symbol Unit of unit Dimension
Fundamental
Length l, L meter L
Mass m, M kilogram M
Time t second T
Current i, I ampere I
Mechanical
Force F newton MLT–3
Torque T newton-meter ML2T–2
Angular displacement h radian —
Velocity v meter/second LT–1
Angular velocity x radian/second T–1
Acceleration a meter/second2 LT–2
Angular acceleration a radian/second 2
T–2
Spring constant (translation) K newton/meter MT–2
Spring constant (rotational) K newton/meter 3
MT2T–2
Damping coefficient (translational) D, F newton-second/meter MT–1
Damping coefficient (rotational) D, F newton-second/meter MT2T–1
2
Moment of inertia J kilogram-meter ML2
Energy W Joule (watt-second) MT2T–2
Power P Watt MT2T–3
Electrical
Charge q, Q coulomb TI
Electric potential v, V, E volt ML2T–3I–1
Electric field intensity f volt/meter (or newton/coulomb) MLT–3I–1
Electric flux density D coulomb/meter 2
L–2TI
Electric flux w, Q coulomb TI
(continued)

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https://doi.org/10.1007/978-3-030-78995-4
360 Appendix B: Units and Conversion Factors

Table B.1 (continued)

Quantity Symbol Unit of unit Dimension
Resistance R ohm ML2T–3I–2
Resistivity q ohm meter ML3T–3I–2
Capacitance C farad M–1L–2T4I2
Permittivity e farad/meter M–1L–3T4I2
Susceptance S siemens (ampere/volt) M–1L–2T3I2
Magnetic
Magnetomotive force £ ampere(–turn) I
Magnetic field intensity H ampere(–turn)/meter L–1I
Magnetic flux / weber ML2T–2I–1
Magnetic flux density B tesla MT–2I–1
Magnetic flux linkages k weber-turn ML1T–1I–1
Inductance L henry ML2T–2I–2
Permeability µ henry/meter MLT–2I–2
Reluctance R ampere/weber M–1L–2T2I4

Table B.2 Conversion factors

Quantity Multiply number of: By: To obtain
Length meters 100 centimeters
meters 39.37 inches
meters 3.281 feet
inches 0.0254 meters
inches 2.54 centimeters
feet 0.3048 meters
Force newtons 0.2248 pounds
newtons 105 dynes
pounds 4.45 newtons
pounds 4.45  105 dynes
dynes 10–5 newtons
dynes 2.248  10–5 pounds
Torque newton-meters 0.7376 pound-feet
newton-meters 107 dyne-centimeters
pound-feet 1.356 newton-meters
dyne-centimeters 10–7 newton-meters
Energy joules (watt-seconds) 0.7376 foot-pounds
joules 2.778  10–7 kilowatt-hours
joules 107 ergs
joules 9.480  10–4 British thermal units
foot-pounds 1.356 joules
electron-volts 1.6  10–19 joules
Power watts 0.7376 foot-pounds/second
watts 1.341  10–3 horsepower
horsepower 745.7 watts
horsepower 0.7457 kilowatts
foot-pounds/second 1.356 watts
Appendix C
Periodic Table of the Elements

I II III IV V VI VII VIII

1 H1 He 2
1.0081 4.002
2 Li 3 Be 4 B5 C6 N7 O8 F9 Ne 10
6.940 9.02 10.82 12.01 14.008 16.000 19.00 20.183
3 Na 11 Mg 12 Al 13 Si 14 P 15 S 16 Cl 17 Ar 18
22.997 24.32 26.97 28.06 31.02 32.06 35.457 39.994
4 K 19 Ca 20 Sc 21 Ti 22 V 23 Cr 24 Mn 25 Fe 26 Co 27 Ni 28
39.096 40.08 45.10 47.90 50.95 52.01 54.93 55.84 58.94 58.69
Ca 29 Zn 30 Ga 31 Ge 32 As 33 Se 34 Br 35 Kr 36
63.57 65.38 69.72 72.6 74.91 78.96 79.916 83.7
5 Rb 37 Sr 38 Y 39 Zr 40 Cb 41 Mo 42 Te 43 Ru Rh 45 Pd 46
44
85.48 87.63 88.92 91.22 92.91 96.0 101.7 102.91 106.7
Ag 47 Cd 48 In 49 Sn 50 Sb 51 Te 52 I 53 Xe 54
107.880 112.41 114.76 118.70 121.76 127.61 126.92 131.3
6 Ce 55 Ba 56 La 57 Hf 72 Ta 73 W 74 Re 75 Os Ir 77 Pt 78
76
132.91 137.36 138.92 178.6 180.88 184.0 186.31 191.5 193.1 195.23
Au 79 Hg 80 Ti 81 Pb 82 Bi 83 Po 84 At 85 Rn 86
197.2 200.61 204.39 207.21 209.00 - - 222
7 Fr 87 Ra 88 Ac 89 Th 90 Pa91 U92
- 226.05 - 232.12 231 238.07
Note The number to the right of the symbol for the element gives the atomic number. The number below the symbol for the element
gives the atomic weight. This table does not include the rare earths and the synthetically produced elements above 92

© The Editor(s) (if applicable) and The Author(s), under exclusive license to 361
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https://doi.org/10.1007/978-3-030-78995-4
Appendix D
Conduction Properties of Common Metals

See Tables D.1, D.2, D.3 and D.4

Table D.1 Resistivity and resistance temperature coefficient

Material Resistivity, q Resistance
microohm-cm at ohm-cir. mils per foot at temp.coefficient
20ºC 20ºC at 20ºC,
a
Aluminum 2.828 – 0.0039
Brass – 40 0.0017
Copper (std. 1.724 10.37 0.00393
annealed)
Nichrome 100 – 0.0004
Silver 1.63 – 0.0038
Tungsten – 33.2 0.0045

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364 Appendix D: Conduction Properties of Common Metals

Table D.2 Round copper-wire DATA

AWG Area Resistance Weight Allowable current* (A)
number (cir.mils) (Ω/1000 ft) (ib/100 ft)
0000 212,000 0.0490 640 358
000 168,000 0.0618 508 310
00 133,000 0.0779 402 267
0 106,000 0.0983 319 230
1 83,700 0.1240 253 196
2 66,400 0.156 201 170
3 52,600 0.197 159 146
4 41,700 0.248 126 125
5 33,100 0.313 100 110
6 26,300 0.395 79.5 94
8 16,500 0.628 50 69
10 10,400 0.999 31.4 50
12 6,530 1.59 19.8 37
14 4,110 2.52 12.4 29
* For type RH insulation—National Electrical Code*

Table D.3 Standard values of commercially available resistors

Ohms (Ω) Kiloohms (kΩ) Megaohms
(MΩ)
0.10 1.0 10 100 1000 10 100 1.0 10.0
0.11 1.1 11 110 1100 11 110 1.1 11.0
0.12 1.2 12 120 1200 12 120 1.2 12.0
0.13 1.3 13 130 1300 13 130 1.3 13.0
0.15 1.5 15 150 1500 15 150 1.5 15.0
0.16 1.6 16 160 1600 16 160 1.6 16.0
0.18 1.8 18 180 1800 18 180 1.8 18.0
0.20 2.0 20 200 2000 20 200 2.0 20.0
0.22 2.2 22 220 2200 22 220 2.2 22.0
0.24 2.4 24 240 2400 24 240 2.4
0.27 2.7 27 270 2700 27 270 2.7
0.30 3.0 30 300 3000 30 300 3.0
0.33 3.3 33 330 3300 33 330 3.3
0.36 3.6 36 360 3600 36 360 3.6
0.39 3.9 39 390 3900 39 390 3.9
0.43 4.3 43 430 4300 43 430 4.3
0.47 4.7 47 470 4700 47 470 4.7
0.51 5.1 51 510 5100 51 510 5.1
(continued)
Appendix D: Conduction Properties of Common Metals 365

Table D.3 (continued)

Ohms (Ω) Kiloohms (kΩ) Megaohms
(MΩ)
0.56 5.6 56 560 5600 56 560 5.6
0.62 6.2 62 620 6200 62 620 6.2
0.68 6.8 68 680 6800 68 680 6.8
0.75 7.5 75 750 7500 75 750 7.5
0.82 8.2 82 820 8200 82 820 8.2
0.91 9.1 91 910 9100 91 910 9.1

Table D.4 Typical capacitor values

pF µF
10 100 1000 10,000 0.10 1.0 10 100 1000
12 120 1200
15 150 1500 15,000 0.15 1.5 18 180 1800
22 220 2200 20,000 0.22 2.2 22 220 2200
27 270 2700
33 330 3300 33,000 0.33 3.3 33 330 3300
39 390 3900
47 470 4700 47,000 0.47 4.7 47 470 4700
56 560 5600
68 680 6800 68,000 0.68 6.8
82 820 8200
Appendix E
Ripple Factor and Voltage Calculation

E.1 Ripple Factor of Rectifier

The ripple factor of a voltage is defined by

rms value of ac component of signal

r¼
average value of signal

which can be expressed as

Vr ðrmsÞ
r¼
Vdc

Since the ac voltage component of a signal containing a dc level is

vac ¼ v  Vdc

the rms value of the ac component is

 Z 1=2
1 2p 2
Vr ðrmsÞ ¼ vac dh
2p 0
 Z 2p 1=2
1
¼ ðv  Vdc Þ2 dh
2p 0
 Z 2p 1=2
1  2 
2 2
¼ v  2vVdc þ Vdc dh
2p 0
 2 
2 1=2
¼ V ðrmsÞ  2Vdc 2
þ Vdc
 
2 1=2
¼ V 2 ðrmsÞ  Vdc

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368 Appendix E: Ripple Factor and Voltage Calculation

where V(rms) is the rms value of the total voltage. For the half-wave rectified signal,
 
2 1=2
Vr ðrmsÞ ¼ V 2 ðrmsÞ  Vdc
"  #1=2
Vm 2 Vm 2
¼ 
2 p
"  #1=2
1 2 1 2
¼ Vm 
2 p

Vr ðrmsÞ ¼ 0:385Vm (half - wave) ðE:1Þ

For the full-wave rectified signal,

 
2 1=2
Vr ðrmsÞ ¼ V 2 ðrmsÞ  Vdc
"  #1=2
Vm 2 2Vm 2
¼ pffiffiffi 
2 p

1 4 1=2
¼ Vm  2
2 p

Vr ð rmsÞ ¼ 0:308Vm ðFullwaveÞ ðE:2Þ

E.2 Ripple Voltage of Capacitor Filter

Assuming a triangular ripple waveform approximation as shown in Fig. E.1, we can

write (see Fig. E.2).

Vr ðp  pÞ
Vdc ¼ Vm  ðE:3Þ
2

During capacitor discharge, the voltage change across C is.

Idc T2
Vr ðp  pÞ ¼ ðE:4Þ
C

From the triangular waveform in Fig. E.1

Appendix E: Ripple Factor and Voltage Calculation 369

Fig. E.1 Approximate triangular ripple voltage for capacitor filter

Fig. E.2 Ripple voltage

Vr ðrmsÞ
Fig. E.3 Plot of Vm as a function of % r
370 Appendix E: Ripple Factor and Voltage Calculation

Vr ðp  pÞ
Vr ðrmsÞ ¼ pffiffiffi ðE:5Þ
2 3

(Obtained by calculations not shown). (Fig. E.3)

Appendix F
Hybrid Parameters—Graphical
Determinations and Conversion Equations
(Exact and Approximate)

F.1 Graphical Determination

of the h-Parameters

Using partial derivatives (calculus), it can be shown that the magnitude of the h-
parameters for the small-signal transistor equivalent circuit in the region of operation
for the common-emitter configuration can be found using the following equations.*

@vi @vbe Dvbe 
hie ¼ ¼ ffi (ohms) ðF:1Þ
@ii @ib Dib VCE¼constant

@vi @vbe Dvbe 
hre ¼ ¼ ffi ðunitlessÞ ðF:2Þ
@v0 @vce Dvce IB ¼constant

@io @ic Dic 
hfe ¼ ¼ ffi ðunitlessÞ ðF:3Þ
@ii @ib Dib VCE ¼constant

@io @ic Dic 
hoe ¼ ¼ ffi ðsiemensÞ ðF:4Þ
@vo @vce Dvce IB ¼constant

In each case, the symbol Δ refers to a small change in that quantity around the
quiescent point of operation. In other words, the h-parameters are determined in the
region of operation for the applied signal so that the equivalent circuit will be the
most accurate available. The constant values of VCE and IB in each case refer to a
condition that must be met when the parameters are determined from the charac-
teristics of the transistor. For the common-base and common-collector configura-
tions, the proper equation can be obtained by simply substituting the proper values
of vi, vo, ii and io.

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372 Appendix F: Hybrid Parameters—Graphical Determinations and Conversion …

The parameters hie and hre are determined from the input or base characteristics,
whereas the parameters hfe and hoe are obtained from the output or collector
characteristics. Since hfe is usually the parameter of greatest interest, we shall
discuss the operations involved with equations, such as Eqs. (F.1) through (F.4), for
this parameter first. The first step in determining any of the four hybrid parameters
is to find the quiescent point of operations as indicated in Fig. F.1. In Eq. (F.3) the
condition VCE = constant requires that the changes in base current and collector
current be taken along a vertical straight line drawn through the Q-point repre-
senting a fixed collector-to-emitter voltage. Equation (F.3) then requires that a small
change in collector current be divided by the corresponding change in base current.
For the greatest accuracy, these changes should be made as small as possible.
In Fig. F.1, the change in ib is chosen to extend from IB1 to IB2 along the
perpendicular straight line at VCE. The corresponding change in ic is then found by
drawing the horizontal lines from the intersections of IB1 and IB2 with
VCE = constant to the vertical axis. All that remains is to substitute the resultant
changes of ib and into Eq. (F.3). That is,
 
Dic  ð2:7  1:7ÞmA
jhfe j ¼ ¼
Dib VCE ¼constant ð20  10ÞlA VCE¼8:4V
103
¼ ¼ 100
10  106

In Fig. F.2, a straight line is drawn tangent to the curve IB through the Q-point to
establish a line IB = constant as required by Eq. (F.4) for hoe. A change in VCE was

Fig. F.1 hfe determination

Appendix F: Hybrid Parameters—Graphical Determinations and Conversion … 373

Fig. F.2 hoe determination

then chosen and the corresponding change in iC determined by drawing the hori-
zontal lines to the vertical axis at the intersections on the IB = constant line.
Substituting into Eq. (F.4), we get.
 
Dic  ð2:2  2:1ÞmA
jhoe j ¼ ¼
Dvce IB ¼constant ð10  7ÞV IB ¼ þ 15lA
0:1  103
¼ 33lA=V ¼ 33  106 S ¼ 33lS:
3

To determine the parameters hie and hre the Q-point must first be found on the
input or base characteristics as indicated in Fig. F.3. For hie, a line is drawn tangent
to the curve VCE = 8.4 V through the Q-point to establish a line VCE = constant as
required by Eq (F.1). A small change in Vbe is then chosen, resulting in a corre-
sponding change in ib. Substituting into Eq. (F.1), we get
 
Dvbe  ð733  718ÞmV
jhie j ¼ ¼
Dib VCE ¼constant ð20  10ÞlA VCE¼8:4V
15  103
¼ ¼ 1:5kX
10  106

The last parameter, hre, can be found by first drawing a horizontal line through
the Q-point at IB = 15 µA. The natural choice then is to pick a change in VCE and
find the resulting change in VBE as shown in Fig. F.4.
Substituting into Eq. 2, we get
374 Appendix F: Hybrid Parameters—Graphical Determinations and Conversion …

Fig. F.3 hfe determination

Fig. F.4 hre determination

Appendix F: Hybrid Parameters—Graphical Determinations and Conversion … 375

Fig. F.5 Complete hybrid equivalent circuit for a transistor having the characteristics that ap-
pear in Figs. F.1 through F.4


Dvbe  ð733  725ÞmV 8  103
jhre j ¼  ¼ ¼ ¼ 4  104
Dvce IB ¼constant ð20  0Þ 20

For the transistor whose characteristics appear in Figs F.1 through F.4, the
resulting hybrid small-signal equivalent circuit is shown in Fig F.5.

Table F.1 Typical parameter values for the CE, CC and CB transistor configurations
Parameter CE CC CB
hi 1 kX 1 kX 20 X
hr 2.5  10–4 =1 3.0  10–4
hf 50 –50 –0.98
h0 25 lA/V 25 lA/V 0.5 lA/V
1/h0 40 kX 40 kX 2 MX

As mentioned earlier, the hybrid parameters for the common-base and

common-collector configuration can be found using the same basic equations with
the proper variable and characteristics.
Table F.1 lists typical parameter values in each of the three configurations for the broad
range of transistors available. The minus sign indicates that in Eq. (F3) as one quantity
increases in magnitude within the change chosen, the other decreases in magnitude.

F.2 Exact Conversion Equations

Common-Emitter Configuration

hib
hie ¼ ¼ hic
ð1 þ hfb Þð1  hrb Þ þ hob hib
376 Appendix F: Hybrid Parameters—Graphical Determinations and Conversion …

hib hob  hrb ð1 þ hfb Þ

hre ¼ ¼ 1  hre
ð1 þ hfb Þð1  hib Þ þ hob hib

hfb ð1  hrb Þ  hob hib

hfe ¼ ¼ ð1 þ hfc Þ
ð1 þ hfb Þð1  hrb Þ þ hob hib

hob
hoe ¼ ¼ hoc
ð1 þ hfb Þð1  hrb Þ þ hob hib

Common-Base Configuration

hie hic
hi ¼ ¼
ð1 þ hfe Þð1  hre Þ þ hie hoe hic hoc  hfc hrc

hie hoe  hre ð1 þ hfe Þ hfc ð1  hrc Þ þ hic hoc

hrb ¼ ¼
ð1 þ hfe Þð1  hre Þ þ hie hoe hic hoc  hfc hrc

hfe ð1  hre Þ  hie hoe hrc ð1 þ hfc Þ  hic hoc

hfb ¼ ¼
ð1 þ hfe Þð1  hre Þ þ hie hoe hic hoc  hfc hrc

hoe hoc
hob ¼ ¼
ð1 þ hfe Þð1  hre Þ þ hie hoe hic hoc  hfc hrc

Common-Collector Configuration

hib
hic ¼ ¼ hie
ð1 þ hfb Þð1  hrb Þ þ hob hib

1 þ hfb
hrc ¼ ¼ 1  hre
ð1 þ hfb Þð1  hrb Þ þ hob hib

hrb  1
hfc ¼ ¼ ð1 þ hfe Þ
ð1 þ hfb Þð1  hrb Þ þ hob hib

hob
hob ¼ ¼ hoe
ð1 þ hfb Þð1  hrb Þ þ hob hib
Appendix F: Hybrid Parameters—Graphical Determinations and Conversion … 377

F.3 Approximate Conversion Equations

Common-Emitter Configuration

hib
hie ffi ffi bre
1 þ hfb

hib hob
hre ffi  hrb
1 þ hfb

hfb
hfe ffi ffib
1 þ hfb

hob
hoe ffi
1 þ hfb

Common-Base Configuration

hie hic
hie ffi ffi ffi re
1 þ hfe hfc

hie hoe hic hoc

hrb ffi  hre ffi hre ffi 1 
1 þ hfe hfc

hfe ð1 þ hfc Þ
hfb ffi ffi ffi a
1 þ hfe hfc

hoe hoc
hob ffi ffi
1 þ hfe hfc

Common-Collector Configuration

hib
hic ffi ffi bre
1 þ hfb

hrc ffi 1

1
hfc ffi ffi b
1 þ hfb

hob
hoc ffi
1 þ hfb
Appendix G
Selected Transistor

Characteristics (Figs. G.1, G.2, G.3, G.4, G.5, G.6 and G.7).

Fig. G.1 Average collector characteristics of RCA transistor 2N104 in common-emitter mode

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380 Appendix G: Selected Transistor

Fig. G.2 Average collector characteristics of RCA transistor 2N104 in common-emitter mode,
high current

Fig. G.3 Average collector characteristics, common-emitter connection, RCA transistor 2N139
Appendix G: Selected Transistor 381

Fig. G.4 Average collector characteristics, common-emitter connection, RCA transistor 2N139

Fig. G.5 Average collector characteristics, common-emitter mode, RCA transistor 2N175
382 Appendix G: Selected Transistor

Fig. G.6 Average collector characteristics, common-emitter mode, RCA transistor 2N270

Fig. G.7 Average collector characteristics of RCA transistor 2N410 in common-emitter mode
Appendix H
Hybrid-p Model

The hybrid-p model is for a CE configuration as shown in Fig. H.1. The parameters
gm and rp depend upon the value of dc quiescent current ICQ; therefore, they
provide more accurate analysis of the transistor for both pnp and npn without
change of polarities.
Here, transistor is represented as a voltage-controlled current source. Various
elements in this model are:
rb = is the base spreading resistance in ohms which is between 40 and 400Ω. The
resistance of the emitter/collector is normally of the order of 10Ω which is
negligible.

rp = is the incremental resistance of the emitter base diode which is forward

biased in the active region of operation.

Fig. H.1 Hybrid-p model of a transistor in CE configuration at low frequencies

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384 Appendix H: Hybrid-p Model

rl = is the resistance on account of the feedback from out to input due to early
effect. The value is normally very high in several megaohms which means
open circuit.

ro = is output resistance which is also due to early effect. Its value is VA /ICQ
where VA is the early voltage and ICQ is the collector dc quiescent current. This
output resistance is normally in tens of kiloohms to hundreds of kiloohms.

gm v p = is a signal collector current gm vp when collector is shorted to emitter for

any small-signal voltage vp at the emitter junction. A voltage-controlled
current source represents BJT. gmvp is the controlling current for vp
controlling voltage and gm transconductance of the transistor. Another
hybrid-p model is developed by taking the controlled current source gm vp
in terms of the input base current ib as shown in Fig. H.2.

vp ¼ i b r p ðH:1Þ

vce = 0, under short-circuit conditions at the output, the current ic is:

i c ¼ gm v p
ðH:2Þ
¼ gm r p i b

ic =ib ¼ gm rp ðH:3Þ

A forward short-circuit current gain which is an ac common-emitter parameter

termed as b0 is as follows:

b0 ¼ Dic =Dib for VCE ¼ constant ¼ VCEQ ðH:4Þ

¼ i=ib ðvce ¼ 0 þ Þ ðH:5Þ

Fig. H.2 An alternate hybrid-p model as a current-controlled source

Appendix H: Hybrid-p Model 385

Hence,

ic =ib ¼ rp gm and ic ¼ b0 ib

b0 is same as hfe in CE h-parameter model. The alternate hybrid p model is a

current-controlled source, where controlling current is ib and the controlled current
is b0ib. The feedback resistance rl is very high which means an open circuit.
Transconductance gm: This parameter gives the incremental change in collector
current ic about the operating point which is produced by incremental change in the
base-emitter voltage vBE. Hence, gm can be written as:

gm ¼ Dic =DVBE ðat vce ¼ 0Þ ¼ i=vbe ðH:6Þ

An ac signal vbe is applied at the input of an npn transistor base in an active

region of operation as shown in Fig. H.3.
Then, the total instantaneous base-emitter voltage vbe is:

vBE ¼ VBE þ vbe

The collector current is:

V
i C ¼ I s eV
BE =T
ðH:7Þ
¼ Is eðBE =T Þ evbe =V
V V
T

In this case, dc collector current ICQ is:

=V
ICQ ¼ IC þ Is ev BET ðH:8Þ

Fig. H.3 An NPN transis-

tor amplifier for computa-
tion of gm, transconductance
386 Appendix H: Hybrid-p Model

Therefore, ic becomes:

=v
iC ¼ ICQ evbe t ðH:9Þ

If vbe  VT then:

iC  ICQ ð1 þ ðvbe =VT ÞÞ ðH:10Þ

Here, only the first two terms of the exponential expansion have been retained.
Thus,

iC ¼ ICQ þ ðICQ  vbe =VT Þ ðH:11Þ

There are two components of collector current namely dc bias current ICQ and
the signal component with ic as:

ic ¼ ICQ  vbe =VT ðH:12Þ

The value of the transconductance is given by:

gm ¼ ICQ =VT ðH:13Þ

This is at room temperature T = 293 K, VT = T/11,600 = 25 mV, therefore,

gm ¼ ICQ ðmAÞ=25 ðH:14Þ

Appendix I
Binary Multiplication, Binary Division
and Negative Number

I.1 Binary Multiplication

Multiplication is done by adding a list of shifted multiplicands computed according

to the digits of the multiplier. The product of two unsigned binary numbers is
obtained by the same method. Forming the shifted multiplicands is trivial in binary
multiplication. An example is given below which has the only possible values of the
multiplier digits are 0 and 1:

I.2 Binary Division

The simplest binary division algorithm gives rise to the shift-and-subtract method.
This method for unsigned decimal and binary numbers is compared in the following
example:

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388 Appendix I: Binary Multiplication, Binary Division and Negative Number

I.3 Binary Negative Numbers

There are many ways to represent negative numbers. The signed-magnitude system
is used in everyday business. However, most computers use one of the complement
number systems.

I.3.1 Signed Magnitude

A number in the signed-magnitude system consists of a magnitude and a symbol

indicating whether the magnitude is positive or negative. Decimal numbers + 98, –
57, + 123.5, and –13 are interpreted in the usual way. It also assumes that the sign
is “ + ” if no sign symbol is written. “ + 0” and “–0” are the two possible repre-
sentations of zero, however, both have the same value.
By using an extra bit position to represent the sign (the sign bit), the
signed-magnitude system is applied to binary numbers. Normally, the most sig-
nificant bit (MSB) of a bit string is used as the sign bit (0 = plus, 1 = minus), and
the lower-order bits contain the magnitude. Consequently several 8-bit
signed-magnitude integers and their decimal equivalents can be written as follows:

01010101 ¼ þ 8510 01111111 ¼ þ 12710

11010101 ¼ 8510 11111111 ¼ 12710

An equal number of positive and negative integers exist in the signed-magnitude

system. An n-bit signed-magnitude integer lies within the range –(2n−1 – 1)
through + (2n–1 – 1), and two possible representations of zero exist.
Appendix I: Binary Multiplication, Binary Division and Negative Number 389

I.3.2 Complement Number Systems

A number by changing its sign is negated by the signed-magnitude system, but a

complement number system negates a number by taking its complement as defined
by the system. Changing the sign is easier than taking the complement. However,
two numbers in a complement number system can be added or subtracted directly
without the sign and magnitude checks required by the signed-magnitude system.
Two complement number systems, known as the “radix complement” and the
“diminished radix complement.” A fixed number of digits, say n is dealt with in any
complement number system.
□□□
Solved

B. Tech.
First Semester Examination, 2008–09
Electronics Engineering
Time: 3 Hours Total Marks: 100

Section A

Note: Attempt all questions. 2  10 = 20

Attempt all parts of this question. All parts of this question carry equal marks.
1. This question contains 10 objective type/Fill in the blank type/True or false type
questions.
(i) In Avalanche multiplication, pick up the correct answer.
(a) Disruption of covalent bond occurs by collision
(b) Direct rupture of bonds
(c) (a) and (b) both
(d) None of above
Answer: (a)

(ii) Which one of the following has the ability to act as open circuit for dc and
a short circuit for ac of high frequency?
(a) An inductor
(b) A capacitor

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392 Solved

(c) A resistor
(d) None of above
Answer: (b)

(iii) The alpha (a) and beta (b) of a transistor are related to each other as
(a) a ¼ b þb 1
(b) b ¼ 1 þa b
(c) b ¼ 1 þa a
(d) a ¼ 1 þb b

Answer: (a)

(iv) Read the following statement

(a) ICO in a transistor consists of majority carriers True/False
(b) Bias stabilization is used to prevent thermal run away?
True/False
Answer: (b)

(v) An N-type channel FET is superior to P-type channel FET because

…………… of electrons is greater than that of holes.
Answer: Number

(vi) Which one of the following has the highest input resistance?
(a) npn transistor in CB configuration
(b) pnp transistor in CE configuration
(c) n-type channel JFET
(d) p-type channel MOSFET
Answer: (d)

(vii) For the circuit shown in Fig. 1, the output voltage V0 is given by
Rt
(a) V0 ¼ RC1
0 Vi ðtÞdt
Rt
(b) V0 ¼ RC 0 Vi ðtÞdt
(c) V0 ¼ RC ddt Vi ðtÞ
1 d
(d) V0 ¼ RC dt Vi ðtÞ
Answer: (a)
Solved 393

Fig. 1 .

(viii) The Boolean expression Y ¼ AB þ ðA þ BÞðA þ BÞ may be simplified as

(a) Y = A
(b) Y = A
(c) Y = B
(d) Y = B
Answer: (c)
Note that:
y ¼ AB þ ðA þ BÞðA þ BÞ
¼ AB þ AA þ AB þ AB þ BB
¼ AB þ 0 þ AB þ AB þ B
¼ AB þ AB þ B
¼ Bð1 þ A þ AÞ
¼ Bð1Þ
y¼B

(ix) The time base of an oscilloscope is developed by

(a) A sine wave voltage
(b) A square wave voltage
(c) A sawtooth voltage
(d) The pulse from a built-in clock
Answer: (c)

(x) “If we give negative potential to the upper vertical deflection plate with
respect to the lower one of the CRT, the spot on the screen is upward”. The
above statement is:
(a) True
(b) False
Answer: (a)
394 Solved

Section B

2. Attempt any three parts of this question. All questions carry equal
marks. 10  3 = 30
(a) (i) Sketch typical forward and reverse characteristics for germanium diode and
for a silicon diode. Compare the characteristics and explain why the reverse
saturation current in silicon diode is much smaller than that in comparable
germanium diode.
Answer: See Art. (2.3)

(ii) Determine V0, I1, ID1 and ID2 for the parallel diode configuration of
Fig. 2

Fig. 2 .

Answer: Diodes D1and D2 are connected in parallel and these diodes are in ‘‘on”
state for the voltage E > 0.7. The diode can be replaced as an equivalent of 0.7 V
battery as shown in Fig. 3.

Fig. 3 .

As the voltage across parallel elements is always same, hence.

The output voltage, V0 = 0.7 V
and the current,

E  VD E  V0
I1 ¼ ¼
R R
Solved 395

10  0:7
I1 ¼ ¼ 28:18 mA
330

Note that: I1 ¼ ID1 þ ID2

Considering diodes of similar characteristics we get:

I1
ID1 ¼ ID2 ¼
2
28:18
¼ mA
2

or

ID1 ¼ ID2 ¼ 14:09 mA

(b) (i) Explain why in the active operation, the base current IB is much smaller than
IC or IE? What is the relation among the three currents?
Answer: See Art. (3.2)

(ii) Define a and b with respect to BJT and derive the relationship between
them.
Answer: See Arts. (3.3 and 3.5)
(c) (i) How is an FET used as a voltage-variable resistor? Explain why?
Answer: See Art. (4.4)

(ii) What are the characteristics of an ideal operational amplifier? Explain an

inverting amplifier.
Answer: See Arts. (5.4 and 5.5)
(d) (i) State and prove De Morgan's theorem. How is it helpful in minimizing a
given Boolean expression?
Answer: See Arts. (6.8 and 6.10)

(ii) What is Karnaugh map? Explain how it helps in simplifying in minimizing

a given Boolean expression?
Answer: See Art. (6.11)
(e) Sketch the cathode Ray Tube used in CRO. What are its main parts? Give the
functions of each part. How is current measured by CRO?
396 Solved

Section C

Note: Attempt all questions. All questions carry equal

marks. 10  5 = 50
3. Attempt any two parts of the following:
(a) Discuss the different types of junction breakdown that can occur in a
reverse-biased diode. Explain the shape of the breakdown diode charac-
teristics. What will be their thermal coefficient?
Answer: See Arts (2.14 and 2.15)

(b) Draw circuit diagram to show two methods of producing a negative output
voltage from a half-wave rectifier. Explain briefly the circuit operation.
Answer: The negative output voltage of half-wave rectifier is produced by two
methods:
Method 1: By reversing the diode direction. The circuit and waveforms are
shown in Fig. 4.
The diode is reverse biased during the positive half cycle, hence, has a high
resistance to the current. This makes the load voltage almost equal to zero. The diode
is forward biased during the negative half cycle, hence, offers low resistance to the
current. This load voltage almost equal to instantaneous input i.e., supply voltage.
Method 2: By reversing both supply and diode direction. The circuit and
waveforms are shown in Fig. 5.
Diode D is off during negative half cycle of input; hence, the output is zero volt.
The diode is forward biased during positive half cycle, hence, very less voltage.
This makes the output voltage equal to the input voltage.
(c) What is clipper circuit? Sketch the output voltage waveform from the circuit
shown in Fig. 6.
Answer: Clipper circuit:

Fig. 4 .
Solved 397

Fig. 5 .

Fig. 6 .

A circuit having the ability to clip off or remove a portion of the input signal
without distorting the remaining part of the wave form, is known as clipper circuit.
Output voltage of the given clipper circuit is shown in Fig. 7.

Fig. 7 .
398 Solved

During the positive half cycle if vi < 5 V, diode D1 will be forward biased,
whereas D2 is reverse biased. When vi becomes higher than 5.7 V (5 V voltage
from supply and 0.7 V from diode drop). Diode D1 turns ‘‘on” and the output
voltage is equal to 5.7 V. During negative half cycle, diode D1 is Off and the diode
D2 turn ON when v > 7.7 V. As the diode D2 is conducting, the output voltage is
equal to –7.7 V.
4. Attempt any one of the following:
(a) Sketch a voltage divider bias circuit using NPN transistor. Show all the
polarities and current directions. Explain the operation of the circuit and
write the approximate equation for VB, IE, IC and VCE
Answer: See Art (3.6.3)

(b) For CE amplifier circuit with h-parameters.

hre = 2 kΩ, hre = 6  10–4, hfe = 50, hoe = 25 µAV and load resistance RL = 4 k
Ω, Source resistance RS = 10 kΩ, Compute AV, AI, Ri and R0.
CE Configuration circuit diagram is shown in Fig. 8

Fig. 8 .

Answer:
h-parameter's based equivalent ckt. is shown in Fig. 9
Current gain, AI ¼ 1 þhhoefeR ¼ 1 þ ð2510
50
6 4103 Þ ¼ 45:45
L

Ri ¼ hie þ hre AI RL
   
Input resistance, ¼ 2  103 þ 6  104  45:45  4  103
¼ 2000  109:08 ¼ 1:89kX
AI RL 45:45  4  103
Voltage gain, AV ¼ ¼
Ri 1:89
¼ 96:19
Solved 399

Fig. 9 .

hfe hre 50  6  104

Output admittance, Y0 ¼ h0e  ¼ 25  106 
hie þ Rs 2  103 þ 10  103
5
¼ 2:25  10 X
Output resistance, R0 ¼ y10 ¼ 2:2510
1
5 ¼ 44:44kX

5. Attempt any one of the following:

(a) Sketch the structure of a P-type channel depletion type MOSFET and
explain its principle of operation with neat diagrams. Also sketch its VI
characteristics and circuit symbol.
Answer: See Arts. (4.9 and 4.10)

(b) (i) Define and explain the terms common-mode rejection ratio and virtual
ground in an op-amp.
Answer: See Art. (5.13.5)

(ii) Find the output voltage of the following Op-amp circuit shown in
Fig. 10

Answer: Given: R1 = 33 kΩ, R2 = 22 kΩ, R3 = 12kΩ, RF = 68 kΩ,

V1 = + 0.2 V, V2 = –0.5 V, V3 = 0.8 V
The Op-amp circuit in the figure is the three input summer circuit. The output
expression can be written as:
400 Solved

Fig. 10 .

RF RF RF
V0 ¼ V1  V2  V3
RI R2 R3
     
68  103 68  103 68  103
¼  0:2   0:5   0:8
33  103 22  103 12  103
¼ 0:41 þ 1:55  4:53
¼ 3:39 volts

6. Attempt any two of the following:

(a) (i) Add and subtract the following hexadecimal numbers A4FB and 3FDC.
Answer: The details are as follows:

Addition Subtraction
1 1 1 9 20 E 27
A 4 F B A 4 F B
3 F D C 3 F D C
+ E 4 D 7 – 6 5 1 F

(i) Convert the following numbers as indicated.

(I) (6089.25)10 = (……………………..)8
(II) (A6BF.5)16 = (…………………….)2
(III) (25.26)8 = (……………………..)2
Answer: (i) (6089.25)10 = (..........................)8
Solved 401

Conversion for integer part: Conversion for fractional part

8 6089 0.25 × 8 = 2.00 = 2
8 761 1 0.00 × 2 = 0.00 = 0
8 95  1
8 11  7
8 1 3
0 1

Thus, (6089)10= (13711)8 and (0.25)10= (0.2)8

(ii) (A6BF.5)16 = (…………………….)2

Hexadecimal number A 6 B F  5
Equivalent Binary number zffl}|ffl{ zffl}|ffl{ zffl}|ffl{ zffl}|ffl{ zffl}|ffl{
1010 0110 1011 1111  0101

Hence, (A6BF.5)16 = (1010011010111111.0101)2

(iii) (25.26)8 = (…………………..)2

Octal number 2 5  2 6
Equivalent binary number z}|{ z}|{ z}|{ z}|{
010 101  010 110

Hence, (25.26)8 = (01010.010110)

(b) (i) What is/are universal gate (s). Implement two input XOR gate using only
4 NAND gate.
Answer: It is possible to implement any Boolean expression with the help of
only NAND or only NOR gates, hence, the NAND and NOR gates are called as
``universal gates''. X-OR gate implementation using NAND gate only is as follows:
402 Solved

(ii) Express the Boolean function F ¼ AB þ AC þ AD in a sum of min-

terms form.
Answer: The Boolean function is given by:

F ¼ AB þ AC þ AD
¼ ABðC þ CÞ þ ACðB þ BÞ þ ADðB þ BÞðC þ CÞðD þ DÞðD þ DÞ
¼ ðABC þ ABCÞðD þ DÞ þ ðABC þ ABCÞ þ ðD þ DÞ
þ ðABD þ ABDÞðC þ CÞ
¼ ABCD þ ABCD þ ABCD þ ABCD þ ABCD þ ABCD
þ ABCD þ ABCD þ ABCD þ ABCD þ ABCD þ ABCD
¼ ABCD þ ABCD þ ABCD þ ABCD þ ABCD
þ ABCD þ ABCD

(c) Minimize the given Boolean function using K-map and implement the
simplified function using NOR gates only.
F(w, x, y, z) = Rm(o, 1, 9, 11, 15) + d(8, 10, 14)
Answer: K-map is as follows:
Solved 403

Hence, Fðw; x; y; zÞ ¼ wx þ wy þ xy þ xy.

Express the Boolean function using Demorgan's theorems:

F ¼ wx þ wy þ xy þ xy
¼ wx:wy  xy  xy
F ¼ ðw þ xÞ  ðw þ yÞ  ðx þ zÞ  ðx þ yÞ

OR and AND gate are used to draw a logic circuit which is as follows:

OR gate is replaced by NOR gate and AND gate is replaced by inverted AND
gate, the result and circuit is as follows:
404 Solved

Inverted AND gate is replaced by NOR gate to get final logic circuit using NOR
gate only is as follows:

7. Attempt any one of the following:

(a) Explain briefly the working principle of a digital multimeter with the aid of
a block diagram. What are characteristics of digital voltmeter used in a
typical digital multimeter.
Answer: See Art. (7.3)

(b) State the main applications of a CRO. Briefly explain one of them.
Explain how you will quickly measure the frequency of waveform displaced on
CO.
Answer: See Art. (7.4)
Solved 405

Solved

B. Tech.
Second Semester Examination, 2008-09
Electronics Engineering
Time : 3 Hours Total Marks : 100
Section-A
Note : Attempt all questions. 2  10 = 20
1. Attempt all the parts of this question. All parts of this question carry equal
marks. This question contains 20 objective/fill in the blanks type/true false type
questions.
(i) Diffused impurities with five valence electrons are called ……………..
Answer: Pentavalent impurities.

(ii) In an N-type material the electron is called the ……………. and hole is
................ .
Answer: Majority carrier, minority carrier.

(iii) In the reverse-biased region the reverse saturation current of a silicon

diode doubles for every ……………. rise in temperature.
Answer: 10ºC

(iv) The wavelength and frequency of light of a specific color are directly
related to the ................ of the material.
Answer: Refractive index

(v) In the dc mode the levels of IC and IB are related by a quantity

called……………..
Answer: Emitter current (IE = IB++ IC)

(vi) The quantity Beta provides an important relationship between the base and
collector currents, and is usually between ……………..
Answer: b ¼ IICB
406 Solved

(vii) For CE configuration, typical value of Zi is in the range of ……………..

Answer: 1.1 kΩ

(viii) Given b = 150 and IE = 3.2 mA for a common-emitter configuration

with r0 = ∞Ω, the value of Zi is ……………..
Answer: hie

(ix) The input controlling variable for a BJT transistor is ……………..

Answer: Current

(x) The input impedance of all commercially available FET is …………….

Answer: About 1MW

(xi) A semiconductor has a …………….

(a) Negative temperature coefficient of resistance
(b) Positive temperature coefficient of resistance
(c) Constant temperature coefficient of resistance
(d) None of these
Answer: (a)

(xii) To obtain N-type semiconductor, the impurity added to a pure semi-

conductor is
(a) Trivalent
(b) Tetravalent
(c) Pentavalent
(d) None of these
Answer: (c)

(xiii) For a germanium, PN junction the maximum value of barrier potential is

(a) 0.3 V
(b) 0.7 V
(c) 1.3 V
(d) 1.7 V
Answer: (a)
Solved 407

(xiv) For current ICBO flows in the

(a) Emitter and base leads
(b) Collector and base leads
(c) Emitter and collector leads
(d) None of these
Answer: (b)

(xv) A biasing circuit has a stability factor of 40. If due to temperature change,
Ico change by 1 µA, then Ic will change by
(a) 20 µA
(b) 40 µA
(c) 80 µA
(d) None of these
Answer: (b)
Explanation:
The stability factor is defined SðICO Þ ¼ DI
DIC
CO
.
Change in collector current DIC ¼ SðICO Þ  DICO ¼ 40  1lA ¼ 40lA.

(xvi) A zener diode has a sharp breakdown voltage at low reverse voltage.
The above statement is

(a) True
(b) False
Answer: (b)

(xvii) A varactor diode is optimized for its variable capacitance. Above

statement is
(a) True
(b) False
Answer: (a)

(xviii) The most commonly used transistor circuit arrangement is common

collector. The above statement is
(a) True
(b) False
Answer: (b)
408 Solved

(xix) The emitter of a transistor is doped moderately. The above statement is

(a) True
(b) False
Answer: (b)

(xx) The ideal value of stability factor is 10. The above statement is
(a) True
(b) False
Answer: (b)

Section B
2. Attempt any three parts of this question. All parts of this question carry
equal marks. 10  3 = 30
(a) Explain the working of Half-wave and Full-wave bridge rectifier. What are
the advantages of full-wave rectifier?
Answer: See Art. (2.7)

(b) A half-wave rectifier is used to supply to 10 V dc to a resistive load of

400 W. If the crystal diode has a forward resistance of 20 W, determine the
value of ac voltage supplied to the circuit.
Answer: The load voltage, Vdc ¼ Idc  RL .
Or Vdc ¼ pðRfVþm RL Þ  RI .
The ac voltage supplied to the circuit is obtained from the above equation.
AC supplied voltage Vm ¼ Vdc pRðRL f RL Þ
þ 400Þ
or Vm ¼ 102pð20
400 ¼ 32:98 ¼ 33 V.

(c) Explain the potential divider biasing circuit.

Answer: See Art. (3.6.3)

(d) Explain the CE and CC configuration of BJT.

Answer: See Arts. (3.3.2 and 3.3.3)

(e) What is an OPAMP? How it is used as an integrator and summer?

Answer: See Arts. (5.1 to 5.4, 5.12 and 5.8)
Solved 409

Section C

Note: Attempt all the questions. All questions carry equal marks.
10 5 = 50
3. Attempt any one part of the following:
(a) Explain the construction and characteristics of JFET.
Answer: See Arts. (4.2 to 4.5)

(b) Explain the basic construction, operation and characteristics of MOSFET.

Answer: See Arts. (4.2 to 4.5)
4. Attempt any one part of following:
(a) (i) Convert the (725.25)10 to its equivalent in Base-2. Base-8 and Base-16)
Answer: Equivalent 2n base-2 number:
Conversion for integer part Conversion for fractional part
2 735 0.025 × 2 = 0.5 = 0
2 362 — 1 0.05 × 2 = 1.0 = 1
2 181 — 0 0.0 × 2 = 0.0 = 0
2 90 —1
2 45 —0 (0.25)10 = (0.010)2
2 22 —1
2 11 —0
2 5 —0
2 2 —1
1 —0
(725)10 = (1011010101)2

By combining the integer part and fractional part, we get the equivalent number.

ð725:25Þ10 ¼ ð1011010101Þ2
410 Solved

Equivalent base-8 number:

Conversion for integer part Conversion for fractional part

8 725 0.025 × 8 = 0.2 = 2
8 90 —5 0.00 × 8 = 0.00 = 0
8 11 —2
1 —3
(725)10 = (1325.20)8

By combining the integer part and fractional part, we get the equivalent number.
(725.25)10 = (1325.20)8.
Equivalent base-16 number:
Conversion for integer part Conversion for fractional part
16 725 0.025 × 16 = 4.00 = 4
16 45 —5 0.00 × 16 = 0.00 = 0
2 — 13 (D)
(725)10 = (2D5)16 (0.25)10 = (0.4)16

By combining the integer part and fractional part, we get the equivalent number.
(725.25)10 = (2D5.40)16.

(ii) Perform M – N and M + N if M = 10,101 and N = 1111

M ¼ 10101
N ¼ 1111
M  N ¼ 0110
M  N ¼ 10101  1111 ¼ 0110
M ¼ 10101
N ¼ 1111
M þ N ¼ 100100
M þ N ¼ 10101 þ 1111 ¼ 100100

(b) Discuss the postulates of Boolean algebra. How it is different from ordinary
algebra? What are universal gates?
Implement the expression of XOR gate with the help of NAND gates only.
Solved 411

5. Attempt any one part of the following:

(a) Simplify the Boolean function F in sum of products using don't care con-
ditions (using K-map)
F ¼ Y þ XZ
(i)
d ¼ YZ þ XY
F ¼ BCD þ BCD þ ABCD
(ii)
d ¼ BCD þ ABCD
Answer: Conversion of function into standard conical form and use of K-map
for simplification is essential as the given Boolean function F and Don't care
condition is not a standard canonical form.
F ¼ Y þ XZ
(i)
d ¼ YZ þ XY
The above Boolean function has three variables. The standard canonical form is:
This term has one missing variable (Y)

F ¼ Y þ XZ

This term has two variables missing (X and Z)

F ¼ YðX þ XÞðZ þ ZÞ þ XZðY þ YÞ

¼ XY þ XYðZ  ZÞ þ XYZ þ XYZ
¼ XYZ þ XYZ þ XYZ þ XYZ þ XYZ þ XXZ

Thus, the standard canonical form is:

FðX; Y; ZÞ ¼ Rmð0; 1; 2; 4; 5Þ

Similarly, the don't care function is converted to standard canonical form as:

d ¼ YZ þ XY
¼ YZðX þ XÞ þ XYðZ þ ZÞ
¼ XYZ þ XYZ þ XYZ þ XYZ
¼ XYZ þ XYZ  XYZ
P
or dðX; Y; ZÞ ¼ mð3; 6; 7Þ.
By use of three variables K-map and simplification, we get
412 Solved

Thus, the simplified Boolean function is:

FðX; Y; ZÞ ¼ 1

F ¼ BCD þ BCD þ ABCD

(ii)
d ¼ BCD þ ABCD
The conversion into standard canonical form gives:

F ¼ BCDðA þ AÞ þ BCDðA þ AÞ þ ABCD

¼ ABCD þ ABCD þ ABCD þ ABCD þ ABCD
¼ 1000 þ 0000 þ 1110 þ 0110 þ 1110

Thus, the standard canonical form is:

FðA; B; C; DÞ ¼ Rmð0; 6; 8; 14Þ

Similarly the don't case function is converted to standard canonical form as:

d ¼ BCDðA þ AÞ þ ABCD
¼ ABCD þ ABCD þ ABCD
¼ 1010  0010 þ 0101

Thus, the standard canonical form is :

dðA; B; C; DÞ ¼ Rmð2; 5; 10Þ

By using the 4-variable K-map simplification we get

Solved 413

Hence, the simplified Boolean expression is given by:

FðA; B; C; DÞ ¼ BD þ CD

(b) How zener diode is used as shunt regulator? Explain it.

Answer: The zener diodes are widely used to regulate the voltage across a
circuit, zener diode offers a constant voltage after reaching the breakdown voltage
when it is reverse biased. See Art (?)
6. Attempt any one part of the following:
(a) Explain the working of digital multimeter. What are its applications?
Answer: See Art. (7.2)

(b) Discuss in detail CRO. How is it used for measurement of frequency?

Answer: See Arts. (7.2 and 7.4.4)
7. Attempt any one part of the following:
(a) Explain the working of positive clipper and negative clamper circuits.
Answer: See Art. (2.12)

(b) The input voltage vi to the two clippers shown in figure varies linearly from
0 to 150 V. Sketch and determine the output voltage vo to the same time
scale as the input voltage. Assume ideal diodes.
414 Solved

Answer: Take vi such that D1 and D2 conduct to find vi, we must have I1 and I2
+ve. If and D1 and D2 both conduct as shown in figure.

When D1 and D2 both ON:

If the Diode D1 conducts, we get:

V1  25 ¼ 100ðI1 þ I2 Þ ðiÞ

If the diode D2 conducts, we get:

100  25 ¼ 200I2 þ 100ðI1 þ I2 Þ ðiiÞ

From equation (ii) we get:

75 ¼ 200I2 þ 100I1 þ 100I2

Or 75 ¼ 300xI2 þ 100I1 .
Or 300I2 ¼ 75  100I1 .
By dividing the above equation by 3 on both sides

100I2 ¼ 25 100
3 I1 ðiiiÞ
Solved 415

By substituting equation (iii) in equation (i) we get:

vi  25 ¼ 100I1 þ 100I2
100
¼ 100I1 þ 25  I1
3
  
Or vi  50 ¼ 100I1 1  13 ¼ 100I1 23

200
vi  50 ¼ I1 ðivÞ
3
3
I1 ¼ ðvi  50Þ ðvÞ
200

By substituting equation (v) in equation (iii) we get

 
1 100
I2 ¼ 25  I1
100 3
 
1 100 3
¼ 25   ðvi  50Þ
100 3 200
 
1 vi  50
¼ 25 
100 2
1 h vi i
¼ 25  þ 25
100 2
1 h vi i
¼ 50 
100 2
1
¼ ½100  vi
200

For I1 to be positive we find that, vi must exceed 50 V to D1 conduct therefore

vi < 50, D1 Off, D2 On.
When D1 OFF and D2 ON:
If the diode D1, OFF and D2 ON, the current I1 is 0 and current I2 only flows in
the loop. Hence, current I2 is given as:

100  25
I2 ¼ ¼ 0:25mA
3x

Thus, the output voltage,

vo ¼ 100  ð0:25mA  200kXÞ ¼ 100  50

or vo ¼ 50V.
If the input voltage exceeds 50 V, the diode D1 is ON and D2 is also ON.
If 50 < vi < 100, D1 is ON, D2 is ON.
416 Solved

Hence output voltage, v0 = vi.

If vi > 100 V, diode D1 conducts, D2 OFF.
Hence, output voltage v0 = 100 V.
The input and the output voltage are shown in figure.

Unsolved

B. Tech.
First Semester Examination, 2009-10
Electronics Engineering
Time : 3 Hours Total Marks : 100

Section A

Note: Attempt all questions. 2  10 = 20

1. Attempt all parts of this question. All parts of this question carry equal
marks.
This question contains TEN objective/Fill in the blank type/True False type
questions:

(i) When PN-junction is biased in the forward direction …….. in each region
are injected into the other region.
(ii) In a center-tap full-wave rectifier, Vm is the peak voltage between the
center tap and one end of the secondary. The PIV of the non-conducting
diode is ........ when the filter is not connected.
(iii) Which of the following statement is best suited for a zener diode?
Solved 417

(a) It is rectifier diode.

(b) It works in the forward bias region.
(c) It is a constant voltage device.
(d) It is mostly used in clipping circuit.
(iv) An ordinary transistor is called ‘bipolar junction transistor’ because it has
two poles: one positive and other negative. (True/False)
(v) A common-emitter transistor amplifier has a gain of 150. The output
voltage is measured as 2 V ac, the input voltage will be ……...
(vi) The operation of a JFET involves:
(a) a flow of minority carriers.
(b) A flow of majority carriers.
(c) Recombination.
(d) Negative resistance.
(vii) An ideal operational amplifier is used to make an inverting amplifier.
There are two input terminals of the operational amplifier and are at the same
potential because:

(a) the two inputs are directly short-circuited internally.

(b) the inputs resistance of the operational amplifier is infinity.
(c) the open loop gain of the operational amplifier is infinity.
(d) all the above except option (a).

(viii) The a and b of a transistor are 0.99 and 99 respectively. If its ICBO 0.1 A,
then its ICEO will be ………
(ix) A basic meter can be converted into an ohmmeter by connecting:
(a) a variable resistance in series.
(b) a battery in series.
(c) Both (a) and (b).
(d) None of the above.

(x) (i) A þ A0 B ¼
(ii) A:ðA0 þ BÞ ¼
418 Solved

Section B
2. Attempt any three parts of this question. 10  3 = 30
(a) (i) Differentiate between static and dynamic resistance of a diode.
(ii) Explain the two breakdown mechanisms of a reverse-biased diode.
(iii) Determine v0 and I for the following circuit.

(b) (i) Which of the transistor currents is always the largest? Which one is the
smallest? Which two are relatively close in magnitude?
(ii) Draw the small-signal equivalent circuit of a BJT and explain each
component.

(c) Define the following:

(1) Drain to source saturation current of JFET.
(2) Pinch-off voltage of JFET.
(3) Voltage-controlled resistance of JFET.
(4) Virtual ground in an op-amp.
(5) Voltage gain of a non-inverting amplifier.
(d) (i) Prove the following identity:
   0
ðx1 þ x2 Þ  x01  x03 þ x3  x02 x1  x3 ¼ x01  x2

(ii) Define:
(1) Canonical form
(2) Standard form
(3) Sum of the products
(4) Product of the sums
(5) Don’t care terms.
(e) Explain, how do we measure the voltage, current and the phase of a wave
form using the CRO?
Solved 419

Section C

Note: Attempt all questions. All questions carry equal marks.

10  5 = 50
3. Attempt any two parts of the following:
(a) Sketch vo for the following circuit and determine the dc value of output
voltage. Input to the circuit is 100 V peak to peak sine wave:

Diodes are ideal. All resistances are 2.2 kΩ.

(b) Sketch iR and vo for the following circuit:

(c) Determine VL, IL, IZ nd IR for the following circuit.

420 Solved

4. Attempt any one of the following:

(a) Determine IC, VE, VB, VB and IB for the following circuit.

(b) Determine VCC for the following circuit if the voltage gain AV – 200.
Solved 421

5. Attempt any one of the following:

(a) Determine VGS, ID, VDS, VD, VG and VS for the following circuit:

(b) (i) Enlist the characteristics of an ideal operational amplifier (op-amp).

(ii) Draw the circuit of a subtractor using op-amp and explain its
working.
(iii) Determine the vo for the following circuit:

6. Attempt any two of the following:

(a) Convert the following numbers:

ð2CCDÞ16 ¼ ð Þ8 ¼ ð Þ5
ð7841Þ9 ¼ ð Þ10 ¼ ð Þ4 ¼ ð Þ2
422 Solved

(b) Realize the following expression using Ex-OR/Ex-NOR gates and basic
gates if required

f ðA; B; C; DÞ ¼ A0 BC 0 þ A0 B0 C þ AC 0 D þ ACD0

(c) Minimize the given function using K-map and convert the minimized
function into POS form

f ðA; B; C; DÞ ¼ Rð1; 3; 5; 7; 9; 10; 12; 13Þ

7. Attempt any one part of the following:

(a) Explain the working of digital voltmeter with help of a block diagram.
(b) Explain the working of CRO with the help of a block diagram.

Unsolved

B. Tech.
Second Semester Examination, 2009-10
Electronics Engineering
Time : 3 Hours Total Marks : 100

Section A

Note: Attempt all questions. 10  2 = 20

1. Attempt all parts of this question. All parts of this question carry equal marks.
This question contains 10 objective/Fill in the blank type/True False type questions:

(a) When we apply reverse bias to a junction diode, it:

(i) lowers the potential barrier.

(ii) raises the potential barrier.
Solved 423

(iii) greatly decreases the minority-carrier current.

(iv) greatly increases the majority-carrier current.
(b) Ripple frequency of the output wave form of a full-wave rectifier when fed
with a 50 Hz sine wave is:

(i) 25 Hz
(ii) 50 Hz
(iii) 100 Hz
(iv) 200 Hz
(c) ‘‘An ordinary transistor is called ‘Bipolar Junction Transistor’ because it has
two poles–one positive and the other negative’’. The statement is:

(i) True
(ii) False
(d) The transistor configuration which provides highest output impedance is:

(i) Common Base

(ii) Common Emitter
(iii) Common Collector
(iv) None of the above
(e) In a Field Effect Transistor (FET) the gate to source voltage that gives zero
drain current is called_______voltage.
(f) When the positive voltage on the gate of a p-channel JEET is increased, its
drain current:

(i) increases
(ii) decreases
(iii) remains the same
(iv) none of the above
(g) For the circuit shown in Fig. 1, the output voltage v0 is given by:

1 dvi ðtÞ
(i) v0 ¼  RC dt
R t
(ii) v0 ¼  RC
1
0 vi ðtÞdt
424 Solved

Fig. 1 .

(iii) v0 ¼ RC dvdi ðtÞ

t
Rt
(iv) v0 ¼ RC 0 vi ðtÞdt
(h) Three Boolean operators are:

(i) NOT, OR, AND

(ii) NOT, NAND, OR
(iii) NOR, OR, NOT
(vi) NOR, NAND, NOT
(i) Lissajous pattern obtained on the screen of a CRO can be used to determine:

(i) Phase shift

(ii) Amplitude distortion
(iii) Voltage amplitude
(iv) None of the above
(j) ‘‘A digital voltmeter has negligible loading effect on the circuit under test
because its input resistance is very high”. The above statement is:

(i) True
(ii) False
Solved 425

Section B
2. Attempt any three parts of this question. 10  3 = 30
(a) (i) Describe the conditions established by forward and reverse-biased con-
ditions on a p–n junction diode and how the resulting current is affected.
(ii) Calculate forward current IF for the silicon diode with dynamic
resistance rd = 0.25Ω used in the following circuit of Fig. 2.

Fig. 2 .

(b) (i) What is the major difference between a bipolar and a unipolar device?
Explain with example.
(ii) Draw and explain the input and output characteristics of common-base
configuration using npn bipolar junction transistor. Indicate all the
region of operations.
(c) (i) What are the advantage of FET over BJT. Explain.
(ii) Derive expressions for voltage gain of inverting and non-inverting
ideal operational amplifier configurations.
(d) (i) What are universal gates? Why they are called so? Justify your answer.
(ii) What do you understand by don't care conditions? Is it an advantage or
disadvantage to include them in a map. Explain with reasons.
(e) Draw the block diagram of a CRO and briefly explain the function of each
block.

Section C

Attempt all questions. All questions carry equal marks. 10  5 = 50

3. Attempt any two parts of the following: 2  5 = 10
(a) Describe the physical mechanism of zener breakdown. For the circuit shown
in Fig. 3, find the voltage drop across the 5 kΩ resistance.
426 Solved

Fig. 3 .

(b) Sketch a two-diode full-wave rectifier circuit for producing a positive output
voltage. Sketch the input and output waveforms and explain the circuit
operation.
(c) Draw a voltage doubler circuit. Sketch input and output waveforms and
explain the circuit operation.

4. Attempt any one of the following: 1  10 = 10

(a) Derive the expressions for voltage gain, current gain and input impedance in
terms of h-parameters for common-emitter amplifier.
(b) Determine the following for the voltage divider bias circuit shown in Fig. 4.
(i) IC
(ii) VE
(iii) VB
(iv) VCE and
(v) Ri

Fig. 4 .
Solved 427

5. Attempt any one of the following: 10  1 = 10

(a) Describe the construction and operation of a MOSFET in enhancement
mode. Draw its characteristics and equivalent circuit of the device.
(b) (i) Draw the circuit diagram for unity gain amplifier. Where is its used and
why?
(ii) Find the output voltage of the following op-amp circuit shown in
Fig. 5.

Fig. 5 .

6. Attempt any two parts of the following: 5  2 = 10

(a) (i) Add and subtract without converting the following two octal numbers
7461 and 3465.
(ii) Convert the following numbers as indicated:
(a) (62.7)8 = (__________)16
(b) (BC 64)16 = (__________)10
(c) (111,011)2 = (__________)5
(b) (i) Represent the unsigned decimal number 965 and 672 in BCD and then
show the steps necessary to form their sum.
(ii) Express the Boolean function F = xy + z in a product of max term
form.
(c) Given the Boolean function

FðA; B; C; DÞ ¼ ABC þ ACD þ AB þ ABCD þ ABC

(i) Express it in sum of minterms.

(ii) Find the minimal sum of products expression using K-map and
implement the output using NAND gates only.
428 Solved

7. Attempt any one of the following: 10  1 = 10

(a) Draw the Lissajous pattern you expect when the ratio of the frequency of the
vertical input to that of the horizontal input is 1: 2. Explain with the help of
a neat diagram, why you get this pattern.
(b) Explain briefly the working principle of a digital voltmeter. What are the
advantages obtained by numeric read out?

Unsolved

B. Tech.
First Semester Examination, 2010-11
Electronics Engineering
Time : 3 Hours Total Marks : 100
Note: Attempt all questions. 4  5 = 20

1. Attempt any four parts of the following:

(a) Explain the classification of solids into conductors, semiconductors and

insulators on the basis of band theory.
(b) Define Intrinsic and extrinsic semiconductors.
(c) Define the Fermi levels, Drift current and diffusion current.
(d) Draw and explain the I-V characteristics of p–n junction diode.
(e) Discuss the ac and dc resistance of P–n junction diode.
(f) Determine V0 and ID for the following series circuit:

2. Attempt any four parts of the following:

(a) Determine V0 and required PIV rating of each diode for the configuration of
figure. Assume all diodes are ideal.
Solved 429

(b) Draw the circuit diagram of full-wave voltage doubler and explain its
working.
(c) For the given network, sketch the output waveform V0 and also calculate
time constant.

(d) Discuss the zener and avalanche breakdown mechanisms.

(e) Sketch V0 for the network shown in figure.

(f) For the circuit shown in figure find out the output voltage V0, voltage drop
across series resistance RS and current through zener diode.
430 Solved

3. Attempt any two parts of the following: 2  10 = 20

(a) What do you mean by transistor? Draw and explain the Input and Output
characteristics of n-p-n transistor in common-base configuration.
(b) Determine VC, IB and stability factor S(IC0) for the given circuit:

(c) Derive the formula for voltage gain AV and Input impedance for the
following circuit with the help of h-parameters.
(Where AV ¼ VV0i and Input impedance = Ri)

4. Attempt any two parts of the following: 2  10 = 20

(a) What is JFET ? Draw and explain the characteristics of n-channel and
p-channel JFET.
(b) Draw the circuit diagram of common gate amplifier and determine voltage
gain, Input impedance and Output impedance of the amplifier.
(c) Discuss the different biasing techniques for depletion type MOSFET.
Solved 431

5. Attempt any two parts of the following: 2  10 = 20

(a) (i) Convert (457)8 into decimal number.
(ii) Convert (101,110.0101)2 into decimal number.
(iii) If m = 101,010 and n = 110,110 find out m–n by 2′s compliments
method.
(iv) Convert the following other canonical form f(x, y, z) = R(1, 3, 7).
(v) Draw the circuit diagram of AND gate using diodes.
(b) Obtain the simplified expression in sum of products for the following
boolean function using k-map.
(i) f ¼ xyz þ xyz þ xyz þ xyz
(ii) f ðx; y; zÞ ¼ Rð0; 2; 4; 5; 6Þ

(c) (i) Define the terms slew rate, and maximum signal frequency.
(ii) Calculate the output voltage for the circuit.

Unsolved

B. Tech.
Second Semester Examination, 2010-11
Electronics Engineering
Time : 3 Hours Total Marks : 100
Note: Attempt all questions. 4  5 = 20

1. Attempt any four parts of the following:

(a) What is the difference between an intrinsic and an extrinsic semiconductor?

Define a hole in a semiconductor.
432 Solved

(b) Define:

(1) Donor and acceptor impurities

(2) Mobility and conductivity
(c) Estimate the relative concentration of germanium atoms and electron hole
pairs at 300 K (room temperature).
Also predict the intrinsic resistivity. Given atomic weight of germanium, 72.60
g/g-atom, e = 1.6  10–19 coulombs, intrinsic concentration (at 300 K) 2.4 
1019 electron-hole pairs/m3. Density for germanium = 5.32  106 g/m3. Electron
mobility = 0.39, hole mobility = 0.19.

(d) Determine the number of atoms of aluminum (Al) in cubic meter. Then find
the average drift velocity in an A1 conductor with a cross-sectional area of 1
cm2 carrying a current of 1A.
Given: Atomic weight of A1 = 26.98 g/g-atom, density of A1 = 2.7  106 g/m3.

(e) Explain (i) How does the reverse saturation current of a p-n diode vary with
temperature? (ii) How does the diode voltage (at constant current) vary with
temperature ?
(f) Sketch the piece wise linear characteristics of a diode.
What are the approximate cut in voltages for silicon and germanium?
2. Attempt any two parts of the following:
(a) Sketch the circuit for a full-wave rectifier using two diodes only. Derive the
expression for (i) the dc current, (ii) the dc load voltage, (iii) the dc diode
voltage, (iv) the rms current.
(b) A full-wave rectifier with a center-tapped transformer supplies a dc current
of 100 mA to a load resistance of R = 20Ω. The secondary resistance of
transformer is 1Ω. Each diode has forward resistance of 0.5 Ω.
Determine the following:

(1) rms value of the signal voltage across each half of the secondary
(2) dc power supplied to the load
(3) PIV rating for each diode
(4) ac power input to the rectifier
(5) conversion efficiency
(c) Explain clipping and clamping circuits in detail. For the zener regulator
circuits of Fig. 1 determine the range of input voltage (VS ) for the zener
diode to remain in ‘‘ON’’ state. Given: zener diode;
Solved 433

Fig. 1 .

Vz ¼ 20V; IZ ðmaxÞ ¼ 50mA; Rz ¼ 0:

3. Attempt any two parts of the following:

(a) Draw the circuit of transistor in the CE configuration. Sketch the output
characteristics. Indicate the active, saturation and cut off region. Explain
each region in detail.
(b) How BJT works as a switch? Consider the transistor circuit of Fig. 2 which
has a resistance included between emitter and ground. Show that the tran-
sistor is operating in active mode. Calculate IC, IE and IB.

Fig. 2 .

Given: b = 50

(c) Using the approximate h-parameter model, obtain the expression for a CE
circuit for
(1) Ai
(2) Ri
(3) Av
(4) R0
434 Solved

4. Attempt any two parts of the following:

(a) How is a FET used as a voltage-variable resistance?
Define: (1) transconductance gm ; (2) drain resistance rd; (3) amplification factor
µ of an FET.

(b) An n-channel JFET, having VP = –4 V and IDSS = 10 mA, is used in the

circuit of Fig. 3. The parameter values are VDD = 18 V, RS = 2 kΩ, RD = 2
kΩ, R1 = 450 kΩ and R2 = 90 kΩ.

Fig. 3 .

Determine ID and VDS

(c) Consider the n-channel enhancement MOSFET shown in Fig. 4.

Fig. 4 .

If VT = 4 V and ID = 1.28 mA at VGS = 12 V, determine the value of RD for

operation at VDS = 8 V.
Explain concept of pinch off.
Solved 435

5. Attempt any two parts of the following:

(a) List characteristics of the ideal opamp. For the opamp circuit shown in
Fig. 5, find the values of R1 and R2 for the output to be

Fig. 5 .

v0 ¼ 5va þ 3vb

(b) Write short notes:

(1) Investing and non-investing OPAMA
(2) CMRR
(3) Minterms and maxterms
(4) BCD code and excess-3 code
(c) (1) Given the boolean function 4

Y ¼ ðA þ BCÞðC þ ABÞ

Design circuit using AND and OR gates to realize the above function.

(2) Convert the following: 2

ð1010:101Þ10 ! ð Þ2 ! ð Þ4

ðC3A:47ÞH ! ð Þ8 ! ð Þ2

(3) Minimize the following using K-map: 4

f ða; b; c; dÞ ¼ Rmð0; 1; 3; 4; 7; 9; 10; 14; 15Þ

436 Solved

Unsolved

B. Tech.
Special Theory Examination, 2010-11
Electronics Engineering
Time : 3 Hours Total Marks : 100
Note: Attempt questions from each Section as per instructions.

Section A

Attempt all parts of this question. Each part carries 2 marks.

10  2 = 20
1. (a) Define A.C. resistance rd of a diode. Derive its value in terms of η, VT and IDQ.
(b) Explain the difference between avalanche and zener breakdown in a
p–n junction diode.
(c) Define the pinch-off voltage Vp.
(d) What do you understand by thermal runaway in BJT circuits.
(e) Draw the A.C. equivalent of OP-AMP circuit (i) practical (ii) ideal.
(f) Realize an Exclusive-OR gate using 2-input four NAND gates.
(g) Define a and b of a transistor and derive the relationship between them.
(h) Differentiate between:
(i) Positive and Negative logic systems
(ii) Analog and Digital Signals.
(i) What is the purpose of aquadag coating on the inside of the glass tube in a
C.R.T.?
(j) State the working principle of digital multimeter.

Section B

Attempt any three parts of this question. Each part carries

10 marks. 10  3 = 30
2. (a) (i) Derive the expression for ripple factor and rectification efficiency of
half-wave and full-wave rectifiers.
(ii) Find the maximum and minimum current flowing through the zener diode
in Fig. 1.
Solved 437

Fig. 1 .

(b) (i) What is self-bias? Draw the circuit showing self-bias of an NPN tran-
sistor in CE mode. Explain how self-bias improves stability.
(ii) Consider the circuit shown in Fig. 2. Find the value of RC required to
obtain VC = 5 V.

(iii) Explain the phenomenon of ‘‘early effect’’ in a transistor.

Fig. 2 .

(c) (i) Draw the structure of an n-channel depletion type MOSFET. Explain its
working with the help of output drain characteristics and transfer
characteristics.
(ii) By using an OPAMP, explain the operation of an integrator. What
modifications are done to make it a practical integrator?

(d) (i) Given that A ¼ B  C þ B  C, then show that:

438 Solved

A ¼ B  C þ B  C and

C ¼ A BþA B 5

(ii) Convert the given expression into canonical POS form: 3

Y ¼ AðA þ BÞðA þ B þ CÞ

(iii) ‘‘Excess-3 code is a self-complementary code.’’ Explain. 2

(e) Sketch a CRT with electric focusing and deflection system. What are the
main parts? Give the function of each part.

Section C

Attempt all questions of this Section. 10  5 = 50

3. Attempt any two parts:
(a) In the centre-tap circuit shown in Fig. 3 calculate:
(i) Average current
(ii) DC output voltage
(iii) DC output power
(iv) AC input power
(v) Rectifier efficiency.

Fig. 3 .
Solved 439

(b) Determine V0 for the network shown and input indicated in Figs. 4
and 5. 5

Fig. 4 .

Fig. 5 .

(c) Explain the switching behavior of a p–n junction diode when the input voltage
changes from + VF to –VR. Discuss how storage time can be reduced. 5

4. Attempt any two parts:

(a) Draw the h parameter equivalent circuit of the amplifier shown in Fig. 6.
Calculate input impedance, current gain, voltage gain if hie = 1kΩ and
hfe = 100.

Fig. 6 .
440 Solved

(b) For an emitter follower, derive expressions for A1, AV, Ri and R0, Compete
these for RE = 5 kΩ, RS = 1 kΩ. Assume transistor parameters as:

hie ¼ 1kW; hie ¼ 100; hie ¼ 20m and

hie ¼ 20lAV:

(c) For a transistor in CE information:

(i) Derive an expression between IC, IB and ICD
(ii) Explain why …… of the output …….. is ……. than in CB
configuration
(iii) Cutoff ……..

5. Attempt any two parts:

(a) For Fig. 7, given that the a -channel JFET has ………….:
(i) Compute the Q point (IDQ, VDSQ), when VGS = 1.5. Assume that it is
biased in the pinch-off region.
(ii) Draw D.C. load line. 7

Fig. 7 .

(b) Define the following terms: 3

(i) CMRR
(ii) Slew Rate

OR
(a) An n-channel JFET has Vp = –5 V and IDSS = 12 mA and is used in circuit
shown in Fig. 8. Find the operating point for the circuit. 4
Solved 441

Fig. 8 .

(b) Explain:
(i) Ideal voltage transfer curve of OP-AMP.
(ii) Open-loop OP-AMP configuration.
(iii) Closed-loop OP-AMP configuration.

6. Attempt any one part:

(a) Use ……… map to minimize following Boolean expression and express the
result in (i) SOP form (ii) POS form:

Y ¼ f ðA; B; C; DÞ
¼ Rð0; 1; 2; 6; 7; 10; 12; 15Þ þ Rdð3; 8; 13; 14Þ:

Implement each expression using:

(i) NAND gates only

(ii) NOR gates only 8
442 Solved

(b) Reduce the following Boolean expression using Laws of Boolean

Algebra: 2

F ¼ AB þ AðB þ CÞ þ BðB þ CÞ:

OR

(a) Reduce the following Boolean expression: 5

 0   0
ðABÞ0 þ A0 þ AB ðABÞ0 þ ABC ðAB0 C Þ :

(b) Find the value of x: 3

ð786Þ10 ¼ ðxÞ16:

(c) Convert (82)10 to base 4 number system. 2

7. Write short notes on any two:

(a) Measurement of phase angle and frequency by a CRO 5

(b) Working Principle of CRO 5
(c) Basic control present in CRO. 5
Solved 443

Unsolved

B. Tech.
First Semester Theory Examination, 2012-13
Electronics Engineering
Time : 3 Hours Total Marks : 100
Note: Attempt questions from each Section as per instructions.

Section A

Attempt all parts of this question. Each part carries 2 marks.

10  2 = 20
1. (a) If a pure silicon crystal has 1 million free electrons inside it, how many holes
does it have? What happens to the number of free electrons and holes, if the
ambient temperature increases?
(b) Define the use of Surge resistor.
(c) Draw the schematic of Peak-to-Peak detector.
(d) How is Varactor used?
(e) Calculate the output voltage appearing across Rload (in Fig. 1).
(f) Find resistance Rb in Fig. 2 to bring transistor to threshold of saturation
VCB ¼ 0; VBE ¼ 0:7V; a ¼ 0:96.
(g) MOSFET
(h) List the primary differences between JFET and MOSFET.
(i) How to test probe using CRO?
(j) List the four specifications of dc power supply.

Fig. 1 .
444 Solved

Fig. 2 .

Section B

Attempt any three parts of this question. Each part carries 10 marks. 10
 3 = 30
2. (a) (i) Sketch and explain the circuits of a combination clipper which limit the
output between ± 10 V. Assume the diode voltage as 0.7 V.
(ii) With neat diagram and waveforms explain the working of a negative
clamper and also write the condition for stiff clamper.
(b) Given b = 50 for the transistor circuit shown in Fig. 3, find the transistor
currents IC, IE and IB. In which region is the transistor operating? Justify.

(c) Describe the drain curves and transconductance curve of enhancement mode
and depletion mode MOSFET. Derive an expression for gm of JFET
configuration.
(d) Draw the block diagrams of four types of Negative Feedback Amplifiers.
Also calculate VCVS voltage gain, input impedance and output impedance.

Fig. 3 .
Solved 445

(e) (i) Explain, how you would measure phase of signal from C.R.O.
(ii) Describe the working of digital multimeter with neat block diagram.

Section C

Attempt any three question of this Section. Each question carries 10 marks.
10  5 = 50.
3. Attempt any two parts:
(a) Sketch the ………….. output Fout in the circuit of Fig. 4. ……….. the
values of maximum question and negative output voltages.

(b) Explain the working of voltage multiplier.

(c) Explain the working of …………. diode.

Fig. 4 .

4. Attempt any two parts:

(a) Explain the working of …………follower circuit with ………………….
(b) Draw the schematic of direct couple output stage and explain its working.
(c) Compare different types of biasing methods.

5. Attempt any two parts:

(a) Define Ohmic region, gate cutoff voltage and transconductance in JFET.
(b) Draw the schematic of CS JFET amplifier and determine AV.
(c) Explain the active load switching circuit using the MOSFET.
446 Solved

6. Attempt any one part:

(a) Explain:
(i) Input bias current compensation in OPAMP.
(ii) Integrator using OPAMP.
(iii) Zero crossing detector using OPAMP.

(b) (i) Obtain an expression for the closed loop gain of a non-inverting
amplifier.
(ii) Describe the method of measuring and calculating CMMR of an
OPAMP.

7. Attempt any two parts:

(a) Compare the design issues of analog meters and digital meters.
(b) Draw the basic block diagram of a function generator and explain the
function of each block.
(c) Explain the procedure to obtain the Lissajous pattern on the screen of a CRO
and also explain how the phase of an unknown signal can be determined from it.

Unsolved

B. Tech.
Second Semester Theory Examination, 2012-13
Electronics Engineering
Time : 3 Hours Total Marks : 100
Note: Attempt questions from each Section as per instructions.

Section-A

Attempt all parts of this question. Each part carries

2 marks. 10  2 = 20
1. (a) Compare the properties of Si and Ge semiconductors.
(b) Define depletion payer in a diode.
(c) Define bulk resistance of the diode.
(d) Draw the double ended diode clipper circuit.
(e) Draw the output waveform appear across RL for the Fig. 1.
Solved 447

Fig. 1 .

(f) A constant voltage source with 10 V and series internal resistance of 100Ω.
Calculate its equivalent current source.
(g) Define Ohmic region in Fet.
(h) If a of a transistor changes from 0.981 to 0.987, find the percentage change
in b?
(i) Why triggering circuit is needed in CRO?
(j) List the four specifications of unregulated power supply.

Section B

Attempt any three parts of this question. Each part carries 10 marks.
10  3 = 30.
2. (a) (i) For a half-wave rectifier derive an expression for ripple factor.
(ii) Explain the function of the circuit of Fig. 2 and draw the output waveform.

(b) Draw the CE configuration circuit of BJT and explain its input and output
characteristics.
(c) Describe the working operation of enhancement mode and depletion mode
MOSFET. Also derive an expression for gm of JFET configuration.
(d) Draw the block diagram and equivalent circuit of an Op-Amp. Explain ideal
characteristics of an Op-Amp.
(e) Explain briefly functions of the following blocks in CRO:
(i) Deflection Amplifier
(ii) Cathode Ray Tube.

Fig. 2 .
448 Solved

Section C

Attempt all questions of this Section. Each question carries 10 marks.

10  5 = 50.
3. Explain input and output characteristics of any two of the following:
(a) Schottky Diode
(b) Zener Diode
(c) Varactor Diode
4. Attempt any two parts:
(a) Explain the working of a common-base circuit with its circuit diagram.
(b) What is a well-designed voltage divider biasing (VDB) circuit? Explain.
(c) Explain, how the input impedance of an amplifier can load down the a.c.
source.
5. Attempt any two parts:
(a) Explain the transconductance curve of a JFET.
(b) Draw the schematic of Self-Biasing JFET amplifier.
(c) Explain the CMOS inverter circuit working operation.
6. Attempt any one part:
(a) Explain:
(i) Integrator circuit using OP-AMP.
(ii) Summing amplifier using OP-AMP
(iii) Zero crossing detector using OP-AMP.
(b) Explain and calculate the Voltage Gain, Input Impedance and Bandwidth
for an Inverting Negative Feedback Amplifier.
7. Attempt any two parts:
(a) Explain the characteristics of Digital Voltmeter Systems
(b) Explain all Oscilloscope Controls with one example.
(c) How do you measure power supply performance? Explain.
□□□
Glossary of Electric Terms

AC Alternating current. In a time/voltage diagram, ac voltage represents a sine

function (usually), or just any periodically alternating function. The mains
voltage is ac voltage, for example.
Active high/low Normally, signals are active high, which means a voltage level of
0 V represents a logical 0 (LOW) and a voltage of above 5 V represents a logical
1 (HIGH). If, for example, an IC pin is named “CS” (chip select), the chip is
usually selected by pulling this line to HIGH (5 V for TTL), and it gets dese-
lected by pulling it to LOW (OV).
ADC Analog-Digital Converter.
Ammeter Device for measuring electric current. Usually part of a multimeter.
AND Logical function which is TRUE if all inputs are TRUE.
A B A AND B
0 0 0
0 0 0
1 0 0
1 1 1

Examples:7408: 4 AND gates with 2 inputs each7409: 4 AND with 2 inputs each, open collec-
tor4081: 4 CMOS and gates with 2 inputs each.

BGA Ball Grid Array. A type of chip package where the fixing method consists of
a number of solder balls mounted under the chip and directly soldered onto a
PCB.
Bread board Board made of Pertinax or other insulating material for building
prototype circuits. It contains a matrix of holes. There are also types with sol-
dering pads around the holes; these cost more but are easier to work with.

© The Editor(s) (if applicable) and The Author(s), under exclusive license to 449
Springer Nature Switzerland AG 2022
O. N. Pandey, Electronics Engineering,
https://doi.org/10.1007/978-3-030-78995-4
450 Glossary of Electric Terms

Buffer Same as driver.

Bus The name of a set of lines/signals fulfilling a common function, e.g. the
address bus and the data bus. Examples include the PCI bus, H.100 and H.110
buses.
BASE The input terminal of a bipolar transistor.
BETA The Greek letter that designates the current gain of a bipolar transistor. It is
the ratio of the transistor's output current (IC) to its input current (IB).
BIAS Voltage The dc voltage applied across the terminals of a PN junction,
whether the device is a diode, bipolar transistor, or JFET. A PN junction is
forward biased when a positive voltage is applied to the P-region with respect to
the N-region, and reverse biased when the voltage polarity is reversed.
Bipolar Transistor A three-terminal semiconductor component with a three-layer
structure of alternate negative- and positive-type materials (NPN or PNP). It
provides current gain and voltage amplification in a circuit.
Bridge Rectifier Four semiconductor diodes configured as a bridge that acts to
change ac to full-wave pulsating dc.
Cathode One of the two terminals of a diode (negative type material) or the
terminal (also negative type material) that is common to both input and output
sections of an SCR.
Chips Unpackaged diodes, bipolar transistors, SCRs, TRIACs and field-effect
transistors (FETs)—also called DICE.
CMOS (Complementary MOSFET) A combination of an N-channel and a
P-channel MOSFET in a single switching circuit. This circuit features very low
power dissipation and the effective elimination of an external load resistor. The
device responds to a digital pulse at its input by turning one section of the device
ON and the other OFF, causing the turned OFF section to act as its
high-resistance load. When the input pulse reverts to zero, the state of the two
sections of the device is reversed.
Collector The output terminal of a bipolar transistor.
Complementary Bipolar transistors An arrangement of NPN and PNP bipolar
transistors in which the polarity of the supply voltage applied to one device is the
reverse of the other. The two transistors normally have identical electrical
characteristics and are used as a matched pair.
Capacitance Electrical entity which describes the amount of charge a capacitor
can store unit farad (F). A capacitor is an electrical element which is capable of
storing small amount of electrical energy, just like an accumulator. The five most
common capacitor types are:Styroflex: High quality, little tolerance. Mainly
employed in high-end audio.capacitor: applications. Irrelevant for computer
applications. Un-polarized.electrolytic: High capacities, polarized, bigger
Glossary of Electric Terms 451

tolerances. Typical application:capacitor: filtering capacitor in power supplies.

Typical capacity greater than 1µF.Ceramic: Un-polarized. Typical capacity
smaller than 1µF. The Dielectric.capacitor: consists of ceramic layers. Widely
used for all applications.Film capacitor: Like ceramic, self-healing, usually
smaller tolerance range, as ceramic, this type is widely used in all applications.
Un-polarized. Available for high voltages also (up to 1000 V).Tantalum (elec-
trolytic) capacitor: Like electrolytic, smaller tolerance range, particularly used in
digital electronics. Polarized. Typical application: stabilizing. Rarely available
for higher voltages (>10 V) and higher capacities (>100 µf) or at least very
expensive then.Since a simple capacitor only consists of two plates facing other,
you can imagine that even two wires lying in parallel have a certain capacitance.
When you charge a capacitor by applying voltage to it, it first behaves like a
shortcut, then its resistance increases until no current flows through it anymore.
This shortcut period is also present in parallel wires (e.g. a cable), it drains lots of
power from the chip the wires are connected to and the longer the cable, the
higher its capacitance, the longer the shortcut period, the higher the current
which the chip has to endure, and the shorter the chip's lifetime.
Chip Generic Term. An IC in a housing or package. Package types may be
Thru-Hole (THT), Surface Mount (SMT/SMD), Ball Grid Array (BGA) or
Wafer level Chip-scale Packaging (WLCSP).
Thru-hole SMT/SMD BGA

Dimensions and sizes for chips are defined by JEDEC.The following types are some examples:
DIL/DIP: Dual In Line (DIL). This is the most widely used IC housing. The pins come out on both
sides of the chip. When the notch on the case points to the top, pin 1 is in the upper left corner, the
other pin numbers are counted counter-clockwise. Also used in ‘‘DIP switch”, a set of small
switches in a chip like case.SIL/SIP: Single In Line (SIL). They have pins on only one side of the
case. SILs are used on SIMMs (Single In Line Memory Module) and SIPs (single In line
Peripheral package).SOP, SOT, SOIC, TSOP etc.: Examples of surface mount package
(SMT) types. May be Dual-in-line or have pins on all four sides.BGA, FBGA etc.: Examples of
Ball Grid Array types etc.

CMOS Complementary Mental Oxide Semiconductor. TTL uses bipolar transis-

tors, while CMOS chips use unipolar transistors (FETs) which are connected
complementarily (one p-mos, one n-mos) thus consuming virtually no power
and staying much cooler than appropriate TTL chips. Alas, CMOS chips are not
suitable for very high frequencies: when the input level changes, the supply
voltage pin and GROUND get quickly short-circuited. The higher the switch
frequencies, the higher the shortcut time. If you run CMOS chips at high fre-
quency, most of the switching time there is a shortcut, resulting in high power
consumption and heat generation.The switching thresholds are less than 30%
(LOW) and greater than 70% (HIGH) of the supply voltage.As opposed to the
TTL series (74xx), CMOS family chips are not bound to 5 V supply voltage. Vcc
ranges from 3 to 18 V (for the 4000 family). There are also TTL compatible
452 Glossary of Electric Terms

CMOS families available, e.g. the widely used 74 HCxx series (voltage range 4–
6 V), where HC stands for high speed Cmos.
Composite video Video signal which comprises of color and brightness infor-
mation as well as horizontal and vertical synchronization information. Since the
video chip's output signals are mixed into one signal (the composite video
signal) and then must be split again in the monitor, losses occur and deteriorate
the display quality, often resulting in color streaks. If possible, use the com-
puter's Chroma/ Luma output, which carries brightness and sync information on
one line, but color information on another line, which eliminates the color
streaking. The best result is achieved by using an RGB output.
Conductor A material is called a conductor if electrons can move through it, in
other words, if it allows flow of electrical current. How well current can flow
through the conductor is determined by its resistance. If the resistance is very
high, the material is called an insulator.
Connector Many types of connectors are used–the following list indicates some of
the most common:BNC: Bayonet Nut Connector (you may also see it spelled as
Bayonett if you are German, Bayonette if you are French or Bayonett if you are
Spanish—so now you know). Used for video connections, Ethernet (10 base2)/
arcnet, and for high frequencies e.g. measuring equipment (oscilloscope, etc. and
RF applications).DB-xx: Used for: RS232 C (DB9 or DB25 male), parallel port
(DB25 female). For some pinouts.DIN: Deutsches Institute fur Normung. Used
for AT style PC keyboards (5-Pin), PS/2 mice (6-Pin mini-DIN) ATX style
keyboards (6-pin mini- DIN) and for MIDI connections. For pinouts here.RCA
[Cinch]: Radio Company of America. Used for audio and video connections. In
Germany and probably other countries, too, this connector is also known as
‘‘cinch”.SMA/SMB: RF Co-ax connector.TNC: RF Co-ax connector. May have
standard or reverse polarity (mandated by FCC for use with ISM band radios e.g.
Jack Plug
802.11).TNC connector polarity Standard female male N-Type:
Reverse  Polarity male female
RF Co-ax connector.
Continuity A cable (or other conducting material) has continuity when it has a low
resistance, when it therefore constitutes a shortcut.
Continuity tester Device for checking for continuity. It reacts to a resistance
below * 100 Ω, normally acoustically; some devices have a selectable
threshold. Usually part of a multimeter.
Counter Counters are elements counting the number of clock signals and out-
putting them as binary or decimal representation on the output pins.
Examples:4060: 14-step CMOS binary counter with internal oscillator circuit
7468: 2 asynchronous decimal counters.
Glossary of Electric Terms 453

Current Electrical entity which is defined by the amount of charge flow in

Coulomb per second. Unit: = Ampere (A). 1 A = 1C / 1 s. Symbol: = I in
electrical equations.
DC Direct current. dc voltage is linear and constant, and either positive or negative.
The same applies to direct current. See also ac.
DAC Digital-Analog Converter.
Diode Semiconductor element which lets current flow in only one direction (for-
ward direction). Current flows if a positive voltage greater than the forward
voltage is applied to the anode of the diode (the other end is called cathode and is
usually marked with a black ring on the case), otherwise, the diode has a very
high resistance. If the applied voltage is below the avalanche/ blocking voltage
(which is always negative), the diode breaks down and constitutes a shortcut.The
rarely used germanium diodes have a forward voltage of 0.3 V, while the
standard silicon diode has a forward voltage of 0.6 V. (Graphic symbol)Schottky
diode: Diode with a P–N junction consisting of metal and silicon [?]. It is used
for applications requiring fast switching, for instance ECL circuits.Zener diode
[z-Diode]: As opposed to all other diodes, the Z diode is used in reverse
direction. It has a defined avalanche voltage and is often used for voltage sta-
bilizing.Z diodes often have a blue, yellow or red base color. Common series are
BZXxx, ZPDxx, and BZYxx, where xx is the avalanche voltage, e.g. ZPD4.7 or
BZY9.1.Tunnel diode: Only for very high-frequency applications. Its function is
not based on the avalanche effect, but on the tunnel effect.
DRAM Dynamic RAM. DRAM needs a continuous refresh (through the use of
CAS and RAS signals), as the information in it is stored by very small
capacitors.
Driver Sometimes called a Buffer. A driver's output level follows the input level if
it is a non-inverting type, and it implements a NOT function, if it is an inverting
type. Drivers are employed for
• increasing the maximum output current of logical signals.
• signal shaping–turn a noisy signal into a clean signal
• protecting expensive chips
Examples:7404: hex inverter (6 inverters)7414: hex inverter with
Schmitt trigger inputs.7405: hex inverter with O.C. outputs7406:
Inverting driver with O.C. outputs (30 V)7416: inverting driver with
O.C. outputs (15 V)7407: non-inverting driver with O.C. outputs
(30 V)4069: inverting CMOS driver4049: inverting CMOS driver,
buffered4050: CMOS driver
ECL Emitter-Coupled Logic. Very fast logic family and used in some processor
designs such as the AMD2900 range.
EEPROM Electrically Erasable PROM. In contrast to EPROMs, EEPROMs don't
need exposure to UV light to be erased, but can be erased electrically. A big
454 Glossary of Electric Terms

advantage is that it is accessed like an SRAM. Write accesses perform an

automatic clear before write and thus make writing EEPROMs as easy as writing
to SRAMs. Series designator: 28xx, where xx is the number of bits stored.Serial
EEPROMs are labeled 24Cxx (8 bit) or 93Cxx (16 bit). Low-voltage eproms
(PLCC): 3.3 V are labeled 27Vxx.
Electron To be supplied.
EPROM Erasable PROM. EPROMs allow the contents to be erased by exposing
its built-in window to UV light. After this process, all memory cells contain $ff
and the EPROM can be written again. Series designator: 27xx, where xx is the
number of K bits stored.
EXOR (XOR) Exclusive OR. Logical function which is TRUE, if and only if,
exactly one input is TRUE. Frequently called XOR.
A B A XOR B
0 0 0
0 1 1
1 0 1
1 1 0
Examples:7486: 4 XOR gates with 2 inputs each74136: 4 XOR gates with 2 inputs each, open
collector4070: 4 CMOS XOR gates with 2 inputs each

FET Field Effect Transistor. As opposed to normal bipolar transistors, these

unipolar transistors have a negligible flow of current through their gate (bipolar:
base), they consume virtually no power. NMOS-FETs and PMOS-FETs can be
coupled to form CMOS circuits.
FLASH An EEPROM which can be written (and erased) in whole banks or sec-
tors. Typically comes in Uniform sectored or Bootstrap Sectored designs. Series
designator: 28Fxxx (12 V prg. voltage), 29Fxxx (5 V prg. voltage), and
29LVxxx/29SLxxx (3 V and below), where xxx is the memory capacity: 010–1
Mbit, 020–2 Mbit, etc. If the Flash supports 16 bit organization, xxx is: 100–1
Mbit, 200–2 Mbit, etc. Early Flash (before 1998) had a limit on the number of
erase cycles (typically 100,000) but most modern FLASH has essentially no
erase limits.
Flip-flop This edge-triggered element has two stable states, which are toggled on
different events, depending on the type:D flip-flop: Delay flip-flop. The input is
copied to the output delayed by one clock cycle. D-type flip-flops are normally
positive (rising) edge triggered but both edge types are available.T flip-flop:
Toggle flip-flop. The output alternates with each input signal change. To sim-
ulate a T flip-flop, you can simply connect a D flip-flop's complementary output
Q with its input.JK flip-flop: This type combines characteristics of RS flip- flop
and T flip-flop. It has two inputs J and K and a clock input C. If different signals
are applied to J and K, the JK flip-flop acts like an RS flip-flop. If J = K, it acts
Glossary of Electric Terms 455

like a T flip-flop.Viewed technically, a JK flip-flop comprises of two coupled

flip-flops (called Master and Slave), where one outputs the input signals on the
rising edge, the other one on the falling edge of the clock signal. Therefore, it is
sometimes called master slave flip-flop. Main applications of the JK flip-flop are
counters and shift registers. J-K flip-flops are normally negative (falling) edge
triggered but both edge types are available.RS flip-flop: Reset-Set flip-flop. These
have a reset input and a set input and a set input. If reset is high, the output goes
low, if set is high, the output goes high. Setting both reset and set to high is
forbidden, as the results are indetermined.Examples:7470: JK flip-flop with 3
inputs each, preset and reset.74L71: RS master slave flip-flop with 3 inputs each,
preset and reset.74,171: 4 D flip-flops with clear input.
Float An Electronic signal is said to ``float'' when its value is not defined under all
conditions. Floating is generally a ``bad thing'' since random effects (e.g.,
induction) could easily change the value with unexpected or unpleasant results.
Signals that would otherwise ‘float’ are typically ``pulled-up'' (high) or
``pulled-down'' (low) with a weak resistor such that they can be easily changed
when driven.
Fuse A device designed to break a circuit when too much voltage or current is
applied. The idea being that its cheaper to replace a fuse than a device.Electronic
fuses:Domestic fuses: Historically little glass tubes with a wire of defined
maximum voltage and current which melts when its capacity is exceeded. There
are two common formats: 5  20 mm (German) and 6  30 mm (American).
Modern wiring typically uses circuit-breakers which can be reset rather than
replaced.
Gate A gate is a circuit on a chip, which implements a logical function. A 7406, for
example, contains 6 gates (non-inverting drivers).
IC Generic Term. Integrated Circuit. A set of gates etched on a silicon wafer. As
ICs are very sensitive, they are enclosed or packaged in a plastic or ceramic
case/carrier, with their inputs and outputs connected to metal pins or balls. An IC
in a package is commonly referred to as a CHIP. Chips are also called ICs!
Impedance Expressed in ohms is vector sum of all opposition to the flow of
current in a (typically ac) circuit which includes resistance, capacitance and
inductance.
Inductance Measured in Henries. The ability of a component to store energy in the
form of a magnetic field.
Inductor A passive device that stores electrical energy in the form of a magnetic
field. Normally consists of a wire loop or coil. Inductors are typically used to
smoothen out voltage fluctuations in power supply circuits.
Insulator A martial which doesn't conduct electrical current. The opposite in a
conductor.
456 Glossary of Electric Terms

Inverter Gate inverting a logical signal, thus implementing a NOT function. For
examples, see drivers.
Latch A set of flip-flops with a common clock signal. In each cycle, they take the
logical input signals over to their outputs. Usually used to form multiplex
address busses. As opposed to flip-flops, latches are level-triggered.
LED An LED (Light-Emitting Diode) is a diode emitting light when operated in a
forward direction. Since it is a diode, it has a nearly negligible resistance and
must be operated with a series resistor.The forward voltages depend on the type:
Red 1.6–2.1 V Series resistor for 5 V: 330 ΩGreen 2.2–2.7 V. Series resistor for
5 V: 270 ΩYellow 2.7–3.2 V. Series resistor for 5 V: 140 ΩWhite 3.3–4.2 V.
Series resistor for 5 V: 75 ΩBlue 3.3–4.2 V. Series resistor for 5 V: 75 Ω.While
normal LEDs consume about 20 mA, high-efficiency LEDs require only currents
from 2–4 mA (depending on type and color), which means that you can directly
connect them to standard logical output (74LS xx or CMOS 4000 series) without
the need for a driver. Nevertheless you still need an appropriate series resistor.
Resistor calculation = voltage drop  current required in amps.
Logic Tester/Probe Detects and indicates logic TTL (and/or) CMOs voltage
levels. It usually contains a pulse memory (comprising a flip-flop) that memo-
rizes pulses too short to be noticed otherwise.
Mains voltage The voltage at the wall outlet.Australia: 240 V @ 50 HzUK: 230 V
@ 50 HzGermany: 230 V / 400 V @ 50 Hz (formerly 220 V/ 380 V)Japan:
100 V @ 75 HzUSA: 120 V/125 V @ 60 HzNote that since 1989, the standard
European voltage is 230 V @ 50 Hz.s
Monoflop Also known as one-shot multivibrator. Flip-flop with only one stable
state. It remains in the unstable state for a certain time determined by capacitors.
Examples:74,121: Monoflop with Schmitt trigger input 74,221: 2 monoflops
with Schmitt trigger input and reset 74,122: Retriggerable monoflop with reset
74,123: 2 retriggerable monoflops with reset.
MOS Metal Oxide Semiconductor.
Multimeter An all-in-one measuring device. It combines a volt meter, an amp
meter and an ohm meter which usually can also act as continuity tester. Often it
contains a transistor tester and measures capacities and inductivities (in a small
range). There are both analog and digital types; the latter is the preferred choice.
NAND Logical function which is TRUE if and only if not all of the inputs are
TRUE.
Glossary of Electric Terms 457

A B A NAND B
0 0 1
0 1 1
1 0 1
1 1 0
Examples:7400: 4 NAND gates with 2 inputs each7401: 4 NAND gates with 2 inputs each, open
collector4012: 2 CMOS NAND gates with 4 inputs each4093: 4 CMOS NAND gates with 2 inputs
each and Schmitt trigger.

Negative logic Negative logic means that the signals are negative low.
NMOS N-doped MOS
NOR Logical function which is TRUE if and only if all inputs are FALSE.
A B A NOR B
0 0 1
0 1 0
1 0 0
1 1 0
Examples:7402: 4 NOR gates with 2 inputs each7423: 4 NOR gates with 4 inputs each, open
strobe4001: 4 CMOS NOR gates with 2 inputs each4002: 2 CMOS NOR gates with 4 inputs each

NOT Logical function which is TRUE if the input is FALSE.

A NOT A
0 1
1 0

Ohm’s Law Defines the relationship between voltage (E) current (I) and
Resistance (R) in a circuit. For dc circuits, Ohms law is:I = E / R
(amps = volts/resistance in ohms)OrE = I  R (volts = amps  resistance in
ohms)Additional equations.
Ohmmeter Device for measuring resistance. Usually part of a multimeter.
Open collector A possible output connection of a TTL circuit. The output is
formed by a single transistor, which is not connected to the supply voltage;
therefore an external connection to the supply voltage (via a pull-up resistor) is
required. Multiple open collector outputs can be connected together, the output
carrying a 0 signal will override all other outputs.
Oscilloscope A test device which displays voltage curves graphically.
458 Glossary of Electric Terms

OR Logical function which is TRUE if at least one input is TRUE.

A B A OR B
0 0 0
0 1 1
1 0 1
1 1 1
Examples:7432: 4 OR gates with 2 inputs each74,832: 6 OR drives with 2 inputs each4071: 4
CMOS OR gates with 2 inputs each4072: 2 CMOS OR gates with 4 inputs each

PAL This acronym has two meanings:1. Phase-Alternation Lines. Video encoding
standard used in European countries. PAL has 50 pictures/sec interlaced and a
resolution of 625 lines [?].2. Programmable Array Logic. A chip which imple-
ments a sum-of-products logic equation. A PAL can be programmed only once.
Type designator: xxyzz, where xx is the number of inputs, y is either L for active
low outputs or H for active high outputs, and zz is the number of outputs;
example: 16L8. A derivate [?] is the PLA.
PCB Printed Circuit Board. The circuit tracks or traces are etched photographically
onto a media. PCBs may be single-sided (tracks on one side only), double-sided
(both top and bottom surfaces are used) or multilayer where tracks are placed on
a number of separate layers which are then bonded together. Tracks are con-
nected on multilayer boards using VIAs (small holes). Holes are drilled in the
board for thru-hole technology or solder pads provided for SMT or BGA
devices. Components may be placed on the top or increasing on both the top and
bottom of a PCB.
Photo diode Diode which is controlled by light.
Photo transistor Transistor which is controlled by light.
PLA Programmable Logic Array. The same as a PAL, but with a programmable
OR matrix.
PMOS P-doped MOS
P–n Junction .
Positive logic Positive logic means that the signals are active HIGH. Negative
logic means that signals are active LOW (Most commonly in RS 232 circuits)
Potentiometer A variable resistor the value of which is determined by the position
of a slider or a knob.
PROM Programmable ROM. This memory type can be written once, then it
behaves like a ROM. Series designator: 25xx, where xx is the number of kbits
stored.
Glossary of Electric Terms 459

Pull-up/pull down resistor Pull-ups (or pull-downs) have two primary purposes
both of which are variations on a fundamental theme which is to prevent a
short-circuit by adding a resistor in the path between Vcc and GND for a par-
ticular signal.Configuration: Many ICs have pins which must be set to a HIGH
or LOW to configure the chip. Unless an IC is defined to have an internal pull-up
or pull-down you typically use a pull-up (the resistor is between the signal pin
and Vcc) to set a HIGH (1) or a pull-down (the resistor is between the signal pin
and GND) to set a LOW (0).Floating Signals: If a signal is not being actively
driven all the time it will float (i.e. take an arbitrary and maybe changing value).
To prevent this it may be pulled-up (HIGH) or pulled- down (LOW) into a
default state. Pull-ups or pull-downs are usually weak (i.e. high-value resistors of
4.7 K, 10 K (most common) or 47 K) since in the case of floating signals this
allows the ‘‘driven” level to overcome the resistance with a modest current. For
minimum power loss especially in configuration function use the highest value
(47 K). Since higher resistance values take longer to overcome than lower values
if the signal needs to be stable very quickly you may need to go as low as 1 K
for the pull-up (pull-down.)
RAM Random Access Memory. Information can be read and written in any order,
the number of read or write accesses is not limited. RAM comes in different
flavors: DRAM, SRAM, SDRAM, EDO-RAM, VRAM and many more.
Rectifier Circuitry transforming ac into dc, usually consisting of 4 diodes (aka
bridge rectifier)
Resistance The resistance of a conductor (or an insulator) is how easily current can
flow through it. Unit: ohm (capital omega) Symbol = R.
Resistor Electrical element with a defined resistance. It is used as voltage divider,
current limiter or for ensuring that signals do not float. For small through-hole
resistors, their value is not printed on the case, but encoded with color rings.
Radio Frequency Generic term defines equipment which works in the radio fre-
quency range typically.
RGB Red-Green–Blue. These three colors are additively mixed in color TVs and
monitors and so give a picture which ranges from black over all rainbow colors
to white. The number of colors displayed depends on the technology: TTL or
ECL supply digital signals and thus a limited color resolution, usually 4 bits,
which results in 16 colors; analog signals, however, make the color resolution
practically infinite, the number of colors only depends on the graphics card's
memory and on its RAMDAC or VRAM.
RMS Root Mean Square. The real peak value of an ac voltage, which is U* square
root of 2, abbreviation Vrms.
460 Glossary of Electric Terms

ROM Read only memory. Unlike RAM, this type of electronic memory can only
be read. The ROM's content is determined during the manufacturing process
(mask programming). Derivatives are PROM, EPROM, EEPROM and
Flash-EPROM.
SDRAM Synchronous DRAM. Differs from conventional DRAM in that it
internally gates (synchronizes) all access using a single clock rather than separate
column and row clock (driven by CAS & RAS).
Schmitt trigger A logical device that outputs 0 if the input voltage is below a
given threshold voltage and 1 otherwise. Used to clean up the edges of digital
signals. Often comes with a built-in inverter.
Semiconductor Pure semiconductor materials like silicon are insulators. But
doping these materials with a very small amount of e.g. Bor makes them less
insulating and, under certain circumstances, conduct electrical current. Common
semiconductors are diodes and transistors, which are also etched into the silicon
wafers of ICs.
SMD or SMT Surface-mounted device (Surface-mounted technology). A chip
packaging technique. SMD technique means soldering elements (which have
specially designed, very short pins) directly onto pads on the PCB surface
without drilling holes. Other packaging techniques are ‘‘Thru-hole” and Ball
Grid Array (BGA).
Solder Solder is made of tin (Sn) and lead (Pb) and contains a resin core, which
makes the solder flow more easily.
Soldering iron A tool for soldering electrical conducting connections.
SRAM Static RAM. As opposed to DRAM, this type of memory does not need a
continuous refresh, as the information in it stored by flip-flops.
Three-state See tristate.
Thru-hole (THT) A chip packaging technology and requires holes in the PCB
through which component pins were inserted and soldered on the reverse side.
Through-hole is still widely use for connectors and other components that also
have a physical use since the through hole provides a mechanical anchoring
function (e.g. DB25, RJ45, etc.). Surface mount versions of these components
exist but almost always use one or more mechanical locating holes or pins.
Alternate packaging technologies are surface Mount (SMT/SMD) and Ball Grid
Array (BGA).
Thyristor Sometimes called a semiconductor-controlled rectifier. It has 3 pins
(anode, cathode and gate). When powered and gate is ON (high) forward current
only will flow from the anode to cathode (irrespective of state of the gate) until it
drops below a certain level (called the Holding Current). It can be used to rectify
current.
Glossary of Electric Terms 461

Totem pole A possible output connection of a circuit. A totem pole consists of two
transistors, which are driven complementary. Depending on the desired output,
only one of the two transistors is conducting. If two totem pole outputs are
connected, a shortcut occurs if they different digital signals (0/1 or 1/0).
Transformer A transformer changes one ac voltage into another ac voltage. It
consists of two coils (actually not separate coils, but windings) with a different
number of turns, where one coil (transformer primary winding) encloses the
other (transformer secondary winding). The current flowing through the trans-
former primary (the one where the input voltage is applied) invokes a magnetic
field which in turn induces a voltage in the transformer secondary, the amount of
which is determined by the ratio of the number of turns of the windings.A
transformer can have more than one secondary, resulting in more than one
output voltage.
Transistor “Transfer Resistor``. Invented in 1948 by John Bardeen and Walter
Houser Brattain. In principle, this element is an electrically controllable semi-
conductor resistor. It has three terminals C (Collector), E (Emitter), and B
(Base). Basically, when there is no voltage applied to the base, the transistor acts
as an insulator and blocks current flow between C and E.It is used both as an
amplifier and an electronic switch.
Triac Provides similar functionality to a thyristor but supports bi-directional cur-
rent flow.
Tristate or three-state The output lines of tristate circuits can have three states:
HIGH, LOW and HIGH IMPEDANCE (HI-Z), where the latter is equivalent to
not being connected.
Voltage Electrical entity which is the cause for current flow. When talking about ac
voltages, peak-to-peak voltage means as the name suggests—the absolute
amount of voltage between the upper and the lower bound; abbreviation: VCC.
Unit Volt (s)
Voltmeter Device for measuring electrical voltage. Usually part of a multimeter.
VRAM Video RAM, VRAM is dual-ported, so that you can read and write
simultaneously, resulting in a much smaller access time. As the name.
□□□
Index

A Common Gate JFET configuration, 196

Acceptor, 14 Common Source JFET configuration, 199
Active components, 2 Comparison of biasing circuits, 99
AND, 279 Concept of ideal op-amp, 235
Approximate analysis, 96 Concept of Pinch-Off and Maximum Drain
Saturation, 189
B Conductance, 3
Bias current, 245 Conversion of bases, 274
Binary addition, 278 Current gainA, 106
Binary Coded Decimal (BCD) numbers, 278
Binary subtraction, 279 D
Binary system, 272 DC bias with voltage feedback or collector
Binary to decimal, 274 bias, 98
Binary to octal, 276 Decimal system, 271
Block diagram of a CRO, 332 Decimal to binary, 274
Block diagram of a digital multimeter, 331 Decimal to hexadecimal, 277
Block diagram of a ramp-type DVM, 330 Decimal to octal, 276
Boolean algebra, 279 Depletion layer, 15
Boolean algebra theorems table, 280 Depletion mode operation, 208
Dielectric, 4
C Differential amplifier circuit, 240
Cadence design systems, 338 Differentiator, 242
CANCER, 337 Digital Voltmeters (DVMs), 327
Canonical forms, 282 Diode equivalent circuit, 29
Capacitors, 4 Diode ratings, 30
Cathode Ray Oscilloscope (CRO), 332 Diode resistance, 25
Circuit configurations, 82 Donor, 14
Collector to base bias, 100
Colour coding of resistors, 4 E
Common Base (CB) configuration, 82 Electronic charge and current, 2
Common Collector (CC) configuration, 84 Electronic circuit components, 2
Common drain JFET configuration, 203 Electronics instruments, 327
Common Emitter (CE) configuration, 83 Emitter bias, 92
Common Gate (CG), Common Source Emitter bias circuit, 100
(CS) and Common Drain (CD), 195 Emitter follower circuit, 84

© The Editor(s) (if applicable) and The Author(s), under exclusive license to 463
Springer Nature Switzerland AG 2022
O. N. Pandey, Electronics Engineering,
https://doi.org/10.1007/978-3-030-78995-4
464 Index

Energy levels, 10 Measurement of phase difference, 334

Enhancement mode operation, 209 Measurement of voltage, 333
Exact analysis, 95 Measurements Using CRO, 333
Extrinsic semiconductors, 13 Metal Oxide Semiconductor Field Effect
Transistor (MOSFET), 206
F
Fixed-bias, 91 N
Fixed bias circuit, 99 NMMOS, 346
Fixed-biasing of JFET, 193 NMOS, 342
Forward biased, 21 Non-inverting amplifier, 237
Forward biasing, 16 NOT, 279
Forward resistance, 26 N-type semiconductor, 14
Fractional binary to decimal, 275 Number system, 271
Fractional decimal number to binary, 275
O
G Octal system, 273
Graphical analysis of CE amplifier, 100 Octal to binary, 276
Octal to decimal, 275
H Op-amp, 233
Hexadecimal system, 273 Op-amp integrated circuit, 233
Hexadecimal to octal, 278 Op-amp parameters, 244
Hole, 13 Open loop gain, 235
Hybrid Equivalent Circuit for Common Base OR, 279
(CB), 109 Output resistance, 108
Overall voltage gain, 112
I
Ideal and practical V-I characteristics, 24 P
Inductors, 4 Parameter model, 104
Input offset current, 244 Passive components, 2
Input offset voltage, 244 Personal Simulation Program with Integrated
Input resistance, 106 Circuit Emphasis (PSPICE), 337, 338
Insulated Gate Field Effect Transistor (IGFET), Place part, 340
206 PMOS, 346
Integrator, 243 P-N junction, 15
Intrinsic semiconductors, 13 P-N junction and depletion layer, 15
Inverting amplifier, 236 Potential barrier, 15
Potential-divider Method of Biasing JFET, 194
J Product of Sums (POS), 282
JFET biasing, 192 PSPICE project, 338
JFET Connections, 195 P-type of semiconductor, 14
Junction Field Effect Transistor (JFET), 185
R
K Resistors, 3
Kinetic energy, 6 Reverse biased, 21
K-map, 283 Reverse biasing, 17
Reverse resistance, 28
L
Logic gates and universal gates, 281 S
Saturation level, 94
M Self-biasing of JFET, 193
Measurement of current, 334 Semiconductor diode, 21
Measurement of frequency, 335 Semiconductor materials, 10
Index 465

Simplification in sum of product, 285 V

Simplification of Boolean Expression UsingK- Valence electrons, 10
map, 284 V-ICharacteristics, 22
Simulation Program with Integrated Circuit Voltage and current relationships, 5
Emphasis (SPICE), 337 Voltage divider bias, 95, 100
Slew rate, 245 Voltage gainA, 107
SI units, 7
Staircase-ramp DVMs, 329 W
Subtractor, 241 Working of NPN transistor, 81
Sum of Products (SOPs), 282 Working of PNP transistor, 80
Working principle of JFET, 187
T Work, Power and Energy, 6
Transistor action, 80
Transition and diffusion capacitance, 28 X
XOR, 279
U
Unity gain, 238