COMPUTER ARCHITECTURE (EC208)
ASSIGNMENT 2
1. A bus-organized CPU has 16 registers with 32 bits in each, an ALU and a destination
decoder. (CO1, CO5)
a. How many multiplexers are there in the A bus, and what is the size of each
multiplexer?
b. How many selection inputs are needed for MUX A and MUX B?
c. How many inputs and outputs are there in the decoder?
d. How many inputs and outputs are there in the ALU for data, including input and
output carries?
e. Formulate a control word for the system assuming that the ALU has 35
operations.
2. Convert the following arithmetic expressions from infix to reverse Polish notation.
(CO1)
a. A+B*[C*D+E*(F+G)]
𝐴∗[𝐵+𝐶∗(𝐷+𝐸)]
b.
𝐹∗(𝐺+𝐻)
c. Write the program for above two using zero address instructions.
3. An instruction is stored at location 300 with its address field at location 301. The
address field has the value 400. A processor register R1 contains the number 200.
Evaluate the effective address if the addressing mode of the instruction is: (CO1, CO5)
a. Direct
b. Immediate
c. Relative
d. Register indirect
e. Index with R1 as the index register
4. The program in a computer compares two signed numbers A and B by performing the
subtraction A-B and updating the status bits. Let A = 01000001 and B = 10000100.
(CO1)
a. Evaluate the difference and interpret the binary result.
b. Determine the value of status bits S, Z and V.
c. List the conditional branch instructions that will have a true condition.
5. A computer responds to an interrupt request signal by pushing onto the stack the
contents of PC and the current PSW (Program Status Word). It then reads a new PSW
from memory from a location given by an interrupt address symbolized by IAD. The
first address of the service program is taken from memory from at location IAD + 1.
(CO1)
a. List the sequence of microoperations for the interrupt cycle.
b. List the sequence of microoperations for the return from interrupt instruction
6. The following is a symbolic microprogram for an instruction in the computer (CO1)
ORG 40
NOP S JMP FETCH
NOP Z JMP FETCH
NOP I CALL INDRCT
ARTPC U JMP FETCH
a. Specify the operation performed when the instruction i s executed.
b. Convert the four microinstructions into their equivalent binary form
7. Write the symbolic microprogram for each routine. (CO1)
8. Assume that the input logic of the microprogram sequencer which has four inputs, I2,
I1, I0, T(test), and three outputs, S0, S1, and L. The operations that are performed ln
the unit are listed in the following table. Design the input logic circuit using a
minimum number of gates. (CO1, CO5)
9. How many characters per second can be transmitted over a 1200-baud line in each of
the following modes? (Assume a character code of eight bits.) (CO3)
a. Synchronous serial transmission.
b. Asynchronous serial transmission with two stop bits.
c. Asynchronous serial transmission with one stop bit.
10. A DMA controller transfers 164-bit words to memory using cycle stealing. The words
are assembled from a device that transmits characters at a rate of 2400 characters per
second. The CPU is fetching and executing instructions at an average rate of 1 million
instructions per second. By how much will the CPU will be slowed down because of
the DMA transfer? (CO3)
