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Project 1 (100 PTS) Due 10/01/2022: CSCI 6461 Computer Architecture II Fall 2022

This project involves using the SMPCache simulation tool to analyze cache performance for different cache configurations and replacement policies. You are asked to: 1) Simulate a sample memory access sequence and calculate compulsory and conflict misses for various cache sizes and set associativity. 2) Define the different types of cache misses. 3) Explain how to reduce conflict misses. 4) Determine which set blocks will map to for given cache configurations. 5) Analyze average memory access times for write-back and write-through caches under different write policies.

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Ashish Beerelli
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75 views3 pages

Project 1 (100 PTS) Due 10/01/2022: CSCI 6461 Computer Architecture II Fall 2022

This project involves using the SMPCache simulation tool to analyze cache performance for different cache configurations and replacement policies. You are asked to: 1) Simulate a sample memory access sequence and calculate compulsory and conflict misses for various cache sizes and set associativity. 2) Define the different types of cache misses. 3) Explain how to reduce conflict misses. 4) Determine which set blocks will map to for given cache configurations. 5) Analyze average memory access times for write-back and write-through caches under different write policies.

Uploaded by

Ashish Beerelli
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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CSCI 6461 Computer Architecture II Fall 2022

Project 1 (100 pts) 09/17/22

Due 10/01/2022
This project is to help you get familiar with the software SMPCache
(http://arco.unex.es/smpcache/). The following interactive simulations provide a powerful
tool for understanding the complex design features of a modern computer system.

1. Cache simulator: Emulates small sized caches based on a user-input cache model
and displays the cache contents at the end of the simulation cycle based on an
input sequence, which is entered by the user, or randomly generated if so selected.

In an N-way set-associative cache, blocks are mapped to different sets when N


changes. Also, for a particular sequence, the number of compulsory and conflict
misses change with the cache type. Consider the following sequence 4 0 9 7 8 11
7 5 2 1 12 6 8.
(a) List the compulsory and conflict misses for different replacement techniques
for the caches below.

LRU FIFO Random


Misses
Comp Conflict Comp Conflict Comp Conflict

4 blocks
2 sets

8 blocks
2 sets

16 blocks
2 sets

(b) Define compulsory, capacity and conflict misses. Explain the difference
between them.

(c) What is the best way to reduce conflict misses? Can it be used?

(d) List which set in the given cache will the following blocks be mapped
Block Cache #Set

0 8 blocks
2 sets
9

11

2 8 blocks
4 sets
9

10

7 16 blocks
2 sets
1

12

2. Cache time analysis: Demonstrates Average Memory Access Time analysis for
the cache parameters you specify.
Consider a 4-way set associative cache of size 4KB and block size of 64bytes.
Consider 25% writes, miss penalty of 40 cycles, hit time of 1 cycle and mem
write time of 6 cycles. How can the following happen under the condition that the
memory miss penalty, % write and hit time remain the same for both the cases?
Reason your findings in a few sentences.
(a) Avg. Memory access for Write Back cache > Write through cache - No write
allocate
(b) Avg. Memory access for Write Back cache > Write through cache - Write
allocate

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