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Interview Questions

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1. What Is Callback ?

In computer programming, a callback is executable code that

is passed as an argument to other code. It allows a lower-level 
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software layer to call a subroutine (or function) defined in a

higher-level layer.

2. What Is Factory Pattern ?

Factory Pattern Concept : 

Methodologies like OVM and VMM make heavy use of the

factory concept. The factory method pattern is an object-
oriented design pattern. Like other creational patterns, it
deals with the problem of creating objects (products) without
specifying the exact class of object that will be created. The
factory method design pattern handles this problem by
defining a separate method for creating the objects, whose
subclasses can then override to specify the derived type of
product that will be created. More generally, the term factory
method is often used to refer to any method whose main
purpose is creation of objects.

Or in simple terms factory pattern help in creation of the

object when you dont know the exact type of the object. the
normal way of creating the object is :

01.// Normal Type based object creation

02. 

03.// Class object

04.class my_class;

05.int i;

06.endclass

07. 
08.program main;

09.// Create object type my_class

10.my_class obj1;

11.obj1 = new

12.endprogram

13. 

14.// Using Factory I should be able to do the following

15. 


16.program main;

17.base_class my_class_object;

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18. 

19.base_class = factory.create_object(“my_class”); // See

here the type of the object to be created is passed as a string
so we dont know the exact type of the object

20.endprogram

Perl Scripting Interview Questions

3. Explain The Difference Between Data Types Logic

And Reg And Wire ?

Wire are Reg are present in the verilog and system verilog
adds one more data type called logic. 

Wire :

 Wire data type is used in the continuous assignments or ports

list. It is treated as a wire So it can not hold a value. It can be
driven and read. Wires are used for connecting different
modules. 

Reg :

 Reg is a date storage element in system verilog. Its not a

actual hardware register but it can store values. Register
retain there value until next assignment statement. 

Logic :

 System verilog added this additional datatype  extends the

rand eg type so it can be driven by a single driver such as gate
or module. The main difference between logic dataype and
reg/wire is that a logic can be driven by both continuous
assignment or blocking/non blocking assignment.

4. What Is The Need Of Clocking Blocks ?

It is used to specify synchronization characteristics of

the design
It Offers a clean way to drive and sample signals
Provides race-free operation if input skew > 0
Helps in testbench driving the signals at the right time
 Features 
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                  – Clock specification

                  – Input skew,output skew

                  – Cycle delay (##)

Can be declared inside interface,module or program

Example :

01.Module M1(ck, enin, din, enout, dout);

02.input         ck,enin;

03.input  [31:0] din    ;

04.output        enout  ;

05.output [31:0] dout   ;

06. 

07.clocking sd @(posedge ck);

08.input  #2ns ein,din    ;

09.output #3ns enout, dout;

10.endclocking:sd

11. 

12.reg [7:0] sab ;

13.initial begin

14.sab = sd.din[7:0];

15.end

16.endmodule:M1

Perl Scripting Tutorial

5. What Are The Ways To Avoid Race Condition

Between Testbench And Rtl Using Systemverilog?

There are mainly following ways to avoid the race condition

between testbench and RTL using system verilog 

1. Program Block
2. Clocking Block
3. Using non blocking assignments.

Shell Scripting

6. What Are The Types Of Coverages Available In Sv

? 
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Using covergroup :

variables, expression, and their cross

Using cover keyword :

properties

7. What Is Oops?

Here are some nice OOP links on SystemVerilog OOP which

can be used as a good starting point/reference.

1. Object Oriented Programming for Hardware Verification

2. Improve Your SystemVerilog OOP Skills by Learning
Principles and Patterns
3. SystemVerilog OOP OVM Feature Summary
4. Enhancing SystemVerilog with AOP Concepts (On how
to mimic AOP features in OOP, good for guyz coming
from e background)
5. Testbench.in OOP Tutorial

Shell Scripting Tutorial

8. What Is The Need Of Virtual Interfaces ?

An interface encapsulate a group of inter-related wires, along

with their directions (via modports) and synchronization
details (via clocking block). The major usage of interface is to
simplify the connection between modules.

But Interface can’t be instantiated inside program block, class

(or similar non-module entity in SystemVerilog). But they
needed to be driven from verification environment like class.
To solve this issue virtual interface concept was introduced in
SV.

Virtual interface is a data type (that implies it can be

instantiated in a class) which hold reference to an interface


(that implies the class can drive the interface using the virtual
interface). It provides a mechanism for separating abstract

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models and test programs from the actual signals that make
up the design. Another big advantage of virtual interface is
that class can dynamically connect to different physical
interfaces in run time.

9. What Is The Difference Between Mailbox And

Queue?

A queue is a variable-size, ordered collection of homogeneous

elements. A Queue is analogous to one dimensional unpacked
array that grows and shrinks automatically. Queues can be
used to model a last in, first out buffer or first in, first out
buffer.

// Other data type as reference

// int q[]; dynamic array

// int q[5]; fixed array

// int q[string]; associate array 

// include <

// List#(integer) List1;    //

int q[$] = { 2, 4, 8 };

int p[$];

int e, pos;

e = q[0]; // read the first (leftmost) item

e = q[$]; // read the last (rightmost) item

q[0] = e; // write the first item

p = q; // read and write entire queue (copy)

A mailbox is a communication mechanism that allows

messages to be exchanged between processes. Data can be
sent to a mailbox by one process and retrieved by another.

VHDL

10. What Data Structure You Used To Build

Scoreboard?

In SV, we use mailbox to get data from different modules and

compare the result. 
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class Scoreboard;

mailbox drvr2sb;

mailbox rcvr2sb;

function new(mailbox drvr2sb,mailbox rcvr2sb);

  this.drvr2sb = drvr2sb;

  this.rcvr2sb = rcvr2sb;

endfunction:new

task start();

  packet pkt_rcv,pkt_exp;

  forever

  begin

    rcvr2sb.get(pkt_rcv);

    $display(” %0d : Scorebooard : Scoreboard received a

packet from receiver “,$time);

    drvr2sb.get(pkt_exp);

    if(pkt_rcv.compare(pkt_exp)) 

    $display(” %0d : Scoreboardd :Packet Matched “,$time);

    else

      $root.error++;

  end

endtask : start

endclass

In VMM, we use channels to connect all the modules and

compare the result.

class Scoreboard extends vmm_xactor;

   Packet_channel   drvr2sb_chan;

   Packet_channel   rcvr2sb_chan;

function new(string inst = “class”,

             int unsigned stream_id = -1,

             Packet_channel   drvr2sb_chan = null,

             Packet_channel   rcvr2sb_chan = null);

      super.new(“sb”,inst,stream_id);

          if(drvr2sb_chan == null)


           `vmm_fatal(this.log,”drvr2sb_channel is not
constructed”);

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      else

           this.drvr2sb_chan = drvr2sb_chan;

            if(rcvr2sb_chan == null)

           `vmm_fatal(this.log,”rcvr2sb_channel is not
constructed”);

      else

           this.rcvr2sb_chan = rcvr2sb_chan;

          `vmm_note(log,”Scoreboard created “);

endfunction:new

task main();

  Packet pkt_rcv,pkt_exp;

  string msg;

  super.main(); 

  forever

  begin

    rcvr2sb_chan.get(pkt_rcv);

    $display(” %0d : Scoreboard : Scoreboard received a packet

from receiver “,$time);

    drvr2sb_chan.get(pkt_exp);

    if(pkt_rcv.compare(pkt_exp,msg)) 

    $display(” %0d : Scoreboard :Packet Matched “,$time);

    else

    `vmm_error(this.log,$psprintf(” Packet MissMatched n %s

“,msg));

  end

endtask : main

endclass

C Tutorial

11. What Is The Difference Between $random() And

$urandom()?

1. $random system function returns a 32-bit signed

random number each time it is called
2. $urandom system function returns a 32-bit unsigned
random number each time it is called. (newly added in
SV, not present in verilog)
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VLSI

12. What Is Scope Randomization?

Scope randomization ins SystemVerilog allows assignment of

unconstrained or constrained random value to the variable
within current scope

01.module MyModule;

02.integer var, MIN;     

03. 

04.initial begin

05.MIN = 50;         

06.for ( int i = 0;i begin             

07.if( randomize(var) with { var < 100 ; var > MIN ;})

 08.$display(” Randomization sucsessfull : var = %0d Min =

%0d”,var,MIN);

09.else            

10.$display(“Randomization failed”);

11.end

12. 

13.$finish;    

14.end

15.endmodule

Perl Scripting Interview Questions

13. List The Predefined Randomization Methods.

1. randomize
2. pre_randomize
3. post_randomize

VLSI Design Tutorial

14. What Is The Dfference Between Always_combo

And Always@(*)?

From SystemVerilog LRM 3.1a:-

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1. always_comb get executed once at time 0, always @*

waits till a change occurs on a signal in the inferred
sensitivity list
2. Statement within always_comb can’t have blocking
timing, event control, or fork-join statement. No such
restriction of always @*
3. Optionally EDA tool might perform additional checks to
warn if the behavior within always_comb procedure
doesn’t represent combinatorial logic
4. Variables on the left-hand side of assignments within an
always_comb procedure, including variables from the
contents of a called function, shall not be written to by
any other processes, whereas always @* permits
multiple processes to write to the same variable.
5. always_comb is sensitive to changes within content of a
function, whereas always @* is only sensitive to changes
to the arguments to the function.
A small SystemVerilog code snippet to illustrate #5

01.module dummy;

02.logic a, b, c, x, y;

03. 

04.// Example void function

05.function void my_xor;

06.input a;         // b and c are hidden input here

07.x = a ^ b ^ c;

08.endfunction : my_xor

09. 

10.function void my_or;

11.input a;         // b and c are hidden input here

12.y = a | b | c;

13.endfunction : my_xor

14. 

15.always_comb          // equivalent to always(a,b,c)

16.my_xor(a);       // Hidden inputs are also added to

sensitivity list

17. 

18.always @*          // equivalent to always(a)

19.my_or(a);     // b and c are not added to sensitivity list

20.endmodule 
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15. What Is The Use Of Packages?

In Verilog declaration of data/task/function within modules

are specific to the module only. They can’t be shared between
two modules. Agreed, we can achieve the same via cross
module referencing or by including the files, both of which are
known to be not a great solution.

The package construct of SystemVerilog aims in solving the

above issue. It allows having global data/task/function
declaration which can be used across modules. It can contain
module/class/function/task/constraints/covergroup and
many more declarations (for complete list please refer section
18.2 of SV LRM 3.1a)

The content inside the package can be accessed using either

scope resolution operator (::), or using import (with option of
referencing particular or all content of the package). 

01.package ABC;

02.// Some typedef

03.typedef enum {RED, GREEN, YELLOW} Color;

04. 

05.// Some function

06.void function do_nothing()

07….

08.endfunction : do_nothing

09. 

10.// You can have many different declarations here

11.endpackage : ABC

12. 

13.// How to use them

14.import ABC::Color;   // Just import Color

15.import ABC::*;     // Import everything inside the package

Semiconductor

16. What Is The Use Of $cast?

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Type casting in SV can be done either via static casting (‘, ‘, ‘)

or dynamic casting via $cast task/function. $cast is very
similar to dynamic_cast of C++. It checks whether the casting
is possible or not in run-time and errors-out if casting is not
possible.

17. How To Call The Task Which Is Defined In Parent

Object Into Derived Class ?

super.task_name();

Advanced Linux

18. What Is The Difference Between Rand And

Randc?

rand – Random Variable, same value might come before all

the the possible value have been returned. Analogous to
throwing a dice.

randc – Random Cyclic Variable, same value doesn’t get

returned until all possible value have been returned.
Analogous to picking of card from a deck of card without
replacing. Resource intensive, use sparingly/judiciously

Shell Scripting

19. What Is $root?

$root refers to the top level instance in SystemVerilog

1.package ABC;

2.$root.A;     // top level instance A

3.$root.A.B.C; // item C within instance B within top level

instance A

20. What Are Bi-directional Constraints?

Constraints by-default in SystemVerilog are bi-directional.

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sequence in which the constraints are specified. All the

variables are looked simultaneously. Even the procedural
looking constrains like if … else … and -> constrains, both if
and else part are tried to solve concurrently. For example
(a==0) -> (b==1) shall be solved as all the possible solution of
(!(a==0) || (b==1)).

ASIC

21. What Is Solve And Before Constraint ?

In the case where the user want to specify the order in which
the constraints solver shall solve the constraints, the user can
specify the order via solve before construct. i.e.

1….

2.constraint XYZ  {

3.a inside {[0:100]|;

4.b < 20;

5.a + b > 30;

6.solve a before b;

7.}

The solution of the constraint doesn’t change with solve

before construct. But the probability of choosing a particular
solution change by it.

22. Without Using Randomize Method Or

Rand,generate An Array Of Unique Values?

1….

2.int UniqVal[10];

3.foreach(UniqVal[i]) UniqVal[i] = i;

4.UniqVal.shuffle();

5….

23. Explain About Pass By Ref And Pass By Value?

Pass by value is the default method through which arguments

are passed into functions and tasks. Each subroutine retains a 
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local copy of the argument. If the arguments are changed

within the subroutine declaration, the changes do not affect
the caller.

In pass by reference functions and tasks directly access the

specified variables passed as arguments.Its like passing
pointer of the variable.

example:

task pass(int i)    //  task pass(var int i) pass by reference 

delay(10);

i = 1;

printf(” i is changed to %d at %dn”,i,get_time(LO) );

delay(10);

i = 2;

printf(” i is changed to %d at %dn”,i,get_time(LO) );

Universal Verification Methodology (UVM)

24. What Is The Difference Between Byte And Bit

[7:0]?

byte is signed whereas bit [7:0] is unsigned. 

25. What Is The Difference Between Program Block

And Module ?

Program block is newly added in SystemVerilog. It serves

these purposes

1. It separates testbench from DUT

2. It helps in ensuring that testbench doesn’t have any race
condition with DUT
3. It provides an entry point for execution of testbench
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4. It provides syntactic context (via program …

endprogram) that specifies scheduling in the Reactive
Region.
Having said this the major difference between module and
program blocks are

1. Program blocks can’t have always block inside them,

modules can have.
2. Program blocks can’t contain UDP, modules, or other
instance of program block inside them. Modules don’t
have any such restrictions.
3. Inside a program block, program variable can only be
assigned using blocking assignment and non-program
variables can only be assigned using non-blocking
assignments. No such restrictions on module 
4. Program blocks get executed in the re-active region of
scheduling queue, module blocks get executed in the
active region
5. A program can call a task or function in modules or other
programs. But a module can not call a task or function in
a program.

26. What Is The Use Of Modports ?

Modports are part of Interface. Modports are used for

specifing the direction of the signals with respect to various
modules the interface connects to.

1. …
2. interface my_intf;
3. wire x, y, z;
4. modport master (input x, y, output z);
5. modport slave  (output x, y, input z);

VLSI Design

27. Write A Clock Generator Without Using Always

Block.

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Use of forever begin end. If it is a complex always block

statement like always (@ posedge clk or negedge reset_)

always @(posedge clk or negedge reset_) begin

   if(!reset_) begin

       data <= '0;

   end else begin

       data <= data_next;

   end

end

// Using forever : slightly complex but doable

forever begin
   fork

   begin : reset_logic

       @ (negedge reset_);

       data <= '0;

   end : reset_logic

   begin : clk_logic

       @ (posedge clk);

       if(!reset_)    data <= '0;

       else           data <= data_next;

   end : clk_logic

   join_any

   disable fork

end

VHDL

28. What Is Circular Dependency And How To Avoid

This Problem ?

Over specifying the solving order might result in circular

dependency, for which there is no solution, and the constraint
solver might give error/warning or no constraining. Example

1….

2.int x, y, z;
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3.constraint XYZ  {

4.solve x before y;

5.solve y before z;

6.solve z before x;

7…..

8.}

29. What Is Cross Coverage ?

Queue has a certain order. It’s hard to insert the data within
the queue. But Linkedlist can easily insert the data in any
location.

30. How To Randomize Dynamic Arrays Of Objects?

class ABC;

// Dynamic array

rand bit [7:0] data [];

// Constraints

constraint cc {

// Constraining size

data.size inside {[1:10]};

// Constraining individual entry

data[0] > 5;

// All elements

foreach(data[i])

if(i > 0)

data[i] > data[i-1];|

endclass : ABC

31. What Is The Need Of Alias In Sv?

The Verilog has one-way assign statement is a unidirectional

assignment and can contain delay and strength change. To
have bidirectional short-circuit connection SystemVerilog has
added alias statement.

32. What Is “this”?

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“this” pointer refers to current instance.

33. What Is Tagged Union ?

An union is used to stored multiple different kind/size of data

in the same storage location.

1.typedef union{

2.bit [31:0]  a;

3.int         b;

4.} data_u;

Now here XYZ union can contain either bit [31:0] data or an
int data. It can be written with a bit [31:0] data and read-back
with a int data. There is no type-checking done.

In the case where we want to enforce that the read-back data-

type is same as the written data-type we can use tagged union
which is declared using the qualifier tagged. Whenever an
union is defined as tagged, it stores the tag information along
with the value (in expense of few extra bits). The tag and
values can only be updated together using a statically type-
checked tagged union expression. The data member value can
be read with a type that is consistent with current tag value,
making it impossible to write one type and read another type
of value in tagged union. (the details of which can be found in
section 3.10 and 7.15 of SV LRM 3.1a).

01.typedef union tagged{

02.bit [31:0]  a;

03.int         b;

04.} data_tagged_u;

05. 

06.// Tagged union expression

07.data_tagged_u data1 = tagged a 32’h0;

08.data_tagged_u data2 = tagged b 5;

09. 

10.// Reading back the value


11.int xyz = data2.b;

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VLSI

34. What Is “scope Resolution Operator”?

extern keyword allows out-of-body method declaration in

classes. Scope resolution operator ( :: ) links method
declaration to class declaration.

class XYZ;

// SayHello() will be declared outside the body 

// of the class

extern void task SayHello();

endclass : XYZ

void task XYZ :: SayHello();

$Message(“Hello !!!n”);

endtask : SayHello

35. What Is The Difference Between Bits And Logic?

bits is 2-valued (1/0) and logic is 4-valued (0/1/x/z)

36. What Is The Difference Between $rose And

Posedge?

posedge return an event, whereas $rose returns a Boolean

value. Therefore they are not interchangeable.

Semiconductor

37. What Is Layered Architecture ?

In SystemVerilog based constrained random verification

environment, the test environment is divided into multiple
layered as shown in the figure. It allows verification
component re-use across verification projects.

38. What Is The Difference Between Initial Block

And Final Block?

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There are many difference between initial and final block. I

am listing the few differences that is coming to mind now.

1. The most obvious one : Initial blocks get executed at the

beginning of the simulation, final block at the end of
simulation
2. Final block has to be executed in zero time, which
implies it can’t have any delay, wait, or non-blocking
assignments. Initial block doesn’t have any such
restrictions of execution in zero time (and can have
delay, wait and non-blocking statements)
Final block can be used to display statistical/genaral
information regarding the status of the execution like this:-

1.final begin

2.$display(“Simulation Passed”);

3.$display(“Final value of xyz = %h”,xyz);

4.$display(“Bye :: So long, and Thanks for all the fishes”);

5.end

39. How To Check Weather A Handles Is Holding

Object Or Not ?

It is basically checking if the object is initialized or not. In

SystemVerilog all uninitialized object handles have a special
value of null, and therefore whether it is holding an object or
not can be found out by comparing the object handle to null.
So the code will look like:-

01.usb_packet My_usb_packet;

02….

03.if(My_usb_packet == null) begin

04.// This loop will get exited if the handle is not holding any
object

05…..

06.end else begin

07.// Hurray … the handle is holding an object

08….


09.end

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