Department of Electrical and Computer Engineering

Academic Block I Park Road, Chak Shahzad Campus Islamabad

CPE343 Computer Organization and Architecture

Chapter 4
Performance

Dr. Syed Saud Naqvi

Email: saud_naqvi@comsats.edu.pk
What is Performance?
 How can we make intelligent choices about computers?

 Why some computer hardware performs better at some programs, but

performs less at other programs?

 How do we measure the performance of a computer?

 What factors are hardware related? software related?

 How does machine’s instruction set affect performance?

 Understanding performance is key to understanding underlying

organizational motivation
Response Time and Throughput
 Response Time
o Time between start and completion of a task, as observed by end user
o Response Time = CPU Time + Waiting Time (I/O, OS scheduling, etc.)
 Throughput
o Number of tasks the machine can run in a given period of time
 Decreasing execution time improves throughput
o Example: using a faster version of a processor
o Less time to run a task  more tasks can be executed
 Increasing throughput can also improve response time
o Example: increasing number of processors in a multiprocessor
o More tasks can be executed in parallel
o Execution time of individual sequential tasks is not changed
o But less waiting time in scheduling queue reduces response time
Book’s Definition of Performance
 For some program running on machine X

1
PerformanceX =
Execution timeX

 X is n times faster than Y

PerformanceX Execution timeY

= =n
PerformanceY Execution timeX
 Problem:
o Machine X runs a program in 20 seconds
o Machine Y runs the same program in 25 seconds
o How much faster is A than B?
What do we mean by Execution Time?
 Real Elapsed Time
o Counts everything:
• Waiting time, Input/output, disk access, OS scheduling, … etc.
o Useful number, but often not good for comparison purposes

 Our Focus: CPU Execution Time

o Time spent while executing the program instructions
o Doesn't count the waiting time for I/O or OS scheduling
o Can be measured in seconds, or
o Can be related to number of CPU clock cycles
CPU Execution Time = CPU cycles × cycle time = CPU Cycles /Clock rate
Clock Cycles
 Clock cycle = Clock period = 1 / Clock rate

Cycle 1 Cycle 2 Cycle 3

 Clock rate = Clock frequency = 1 / Clock cycle

o 1 Hz = 1 cycle/sec 1 KHz = 103 cycles/sec
o 1 MHz = 106 cycles/sec 1 GHz = 109 cycles/sec
o 2 GHz clock has a cycle time = 1/(2×109) = 0.5 nanosecond (ns)

 We often use clock cycles to report CPU execution time

Improving Performance
 To improve performance, we need to
o Reduce number of clock cycles required by a program, or
o Reduce clock cycle time (increase the clock rate)
 Example:
o A program runs in 10 seconds on computer X with 2 GHz clock
o What is the number of CPU cycles on computer X ?
o We want to design computer Y to run same program in 6 seconds
o But computer Y requires 10% more cycles to execute program
o What is the clock rate for computer Y ?
 Solution:
o CPU cycles on computer X = 10 sec × 2 × 109 cycles/s = 20 × 109
o CPU cycles on computer Y = 1.1 × 20 × 109 = 22 × 109 cycles
o Clock rate for computer Y = 22 × 109 cycles / 6 sec = 3.67 GHz
 Clock Cycles Per Instruction (CPI)
 Instructions take different number of cycles to execute
o Multiplication takes more time than addition
o Floating point operations take longer than integer ones
o Accessing memory takes more time than accessing registers
 CPI is an average number of clock cycles per instruction
I1 I2 I3 I4 I5 I6 I7 CPI = 14/7 = 2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 cycles

 Important point
Changing the cycle time often changes the number of cycles required for
various instructions (more later)
Performance Equation
 To execute a given program, it will require …
o Some number of machine instructions
o Some number of clock cycles
o Some number of seconds
 We can relate CPU clock cycles to instruction count

CPU clock cycles = Instruction Count × CPI

 Performance Equation: (related to instruction count)

CPU Time = Instruction Count × CPI × cycle time

Factors Impacting Performance
CPU Time = Instruction Count × CPI × cycle time

I-Count CPI Cycle

Program X X

Compiler X X

ISA X X X

Organization X X

Technology X
Using the Performance Equation
 Suppose we have two implementations of the same ISA
 For a given program
o Machine A has a clock cycle time of 250 ps and a CPI of 2.2
o Machine B has a clock cycle time of 500 ps and a CPI of 1.0
o Which machine is faster for this program, and by how much?

 Solution:
o Both computers execute same count of instructions = I
o CPU execution time (A) = I × 2.2 × 250 ps = 550 × I ps
o CPU execution time (B) = I × 1.0 × 500 ps = 500 × I ps

550 × I
o Computer B is faster than A by a factor = = 1.1
500 × I
 Determining the CPI
 Different types of instructions have different CPI
Let CPIi = clocks per instruction for class i of instructions
Let Ci = instruction count for class i of instructions
n

n
∑ (CPI × C )i i

CPU cycles = ∑(CPI × C )

i i
CPI =
i=1
n
i=1
∑C i
i=1

 Designers often obtain CPI by a detailed simulation

 Hardware counters are also used for operational CPUs
Example on Determining the CPI
 Problem
A compiler designer is trying to decide between two code sequences for a particular
machine. Based on the hardware implementation, there are three different classes of
instructions: class A, class B, and class C, and they require one, two, and three cycles
per instruction, respectively.
The first code sequence has 5 instructions: 2 of A, 1 of B, and 2 of C
The second sequence has 6 instructions: 4 of A, 1 of B, and 1 of C
Compute the CPU cycles for each sequence. Which sequence is faster?
What is the CPI for each sequence?
 Solution
CPU cycles (1st sequence) = (2×1) + (1×2) + (2×3) = 2+2+6 = 10 cycles
CPU cycles (2nd sequence) = (4×1) + (1×2) + (1×3) = 4+2+3 = 9 cycles
Second sequence is faster, even though it executes one extra instruction
CPI (1st sequence) = 10/5 = 2 CPI (2nd sequence) = 9/6 = 1.5
Second Example on CPI
Given: instruction mix of a program on a RISC processor
What is average CPI?
What is the percent of time used by each instruction class?
Classi Freqi CPIi CPIi × Freqi %Time
ALU 50% 1 0.5×1 = 0.5 0.5/2.2 = 23%
Load 20% 5 0.2×5 = 1.0 1.0/2.2 = 45%
Store 10% 3 0.1×3 = 0.3 0.3/2.2 = 14%
Branch 20% 2 0.2×2 = 0.4 0.4/2.2 = 18%

Average CPI = 0.5+1.0+0.3+0.4 = 2.2

How faster would the machine be if load time is 2 cycles?

What if two ALU instructions could be executed at once?
Second Example on CPI
Given: instruction mix of a program on a RISC processor
What is average CPI?
What is the percent of time used by each instruction class?
Classi Freqi CPIi CPIi × Freqi
ALU 50% 1 0.5×1 = 0.5
Load 20% 2 0.2×2 = 0.4
Store 10% 3 0.1×3 = 0.3
Branch 20% 2 0.2×2 = 0.4
Average CPI = 0.5+0.4+0.3+0.4 = 1.6
How faster would the machine be if load time is 2 cycles?
Speedup = 2.2/1.6 = 1.375 ≈ 37% improvement
Second Example on CPI
Given: instruction mix of a program on a RISC processor
What is average CPI?
What is the percent of time used by each instruction class?
Classi Freqi CPIi CPIi × Freqi
ALU 50% 1 0.5×1 = 0.5
Load 20% 5 0.2×5 = 1.0
Store 10% 3 0.1×3 = 0.3
Branch 20% 1 0.2×1 = 0.2
Average CPI = 0.5+1.0+0.3+0.2 = 2.0
How does this compare with using branch prediction to reduce a cycle?
Speedup = 2.2/2.0 = 1.1 = 10% improvement
Second Example on CPI
Given: instruction mix of a program on a RISC processor
What is average CPI?
What is the percent of time used by each instruction class?
Classi Freqi CPIi CPIi × Freqi
ALU 50% 0.5 0.5×0.5 = 0.25
Load 20% 5 0.2×5 = 1.0
Store 10% 3 0.1×3 = 0.3
Branch 20% 2 0.2×2 = 0.4
Average CPI = 0.25+1.0+0.3+0.4 = 1.95
What if two ALU instructions could be executed at once?
Speedup = 2.2/1.95 = 1.128 ≈ 12% improvement
MIPS as a Performance Measure
 MIPS: Millions Instructions Per Second
 Sometimes used as performance metric
o Faster machine  larger MIPS
 MIPS specifies instruction execution rate

Instruction Count Clock Rate

MIPS = =
Execution Time × 106 CPI × 106

 We can also relate execution time to MIPS

Inst Count Inst Count × CPI

Execution Time = =
MIPS × 106 Clock Rate
Drawbacks of MIPS
Three problems using MIPS as a performance metric

1. Does not take into account the capability of instructions

o Cannot use MIPS to compare computers with different instruction sets

because the instruction count will differ

2. MIPS varies between programs on the same computer

o A computer cannot have a single MIPS rating for all programs

3. MIPS can vary inversely with performance

o A higher MIPS rating does not always mean better performance

o Example in next slide shows this anomalous behavior

MIPS example
 Two different compilers are being tested on the same program for a 4 GHz
machine with three different classes of instructions: Class A, Class B, and
Class C, which require 1, 2, and 3 cycles, respectively.

 The instruction count produced by the first compiler is 5 billion Class A

instructions, 1 billion Class B instructions, and 1 billion Class C instructions.

 The second compiler produces 10 billion Class A instructions, 1 billion Class

B instructions, and 1 billion Class C instructions.

 Which compiler produces a higher MIPS?

 Which compiler produces a better execution time?
Solution to MIPS Example
 First, we find the CPU cycles for both compilers
o CPU cycles (compiler 1) = (5×1 + 1×2 + 1×3)×109 = 10×109
o CPU cycles (compiler 2) = (10×1 + 1×2 + 1×3)×109 = 15×109
 Next, we find the execution time for both compilers
o Execution time (compiler 1) = 10×109 cycles / 4×109 Hz = 2.5 sec
o Execution time (compiler 2) = 15×109 cycles / 4×109 Hz = 3.75 sec
 Compiler1 generates faster program (less execution time)
 Now, we compute MIPS rate for both compilers
o MIPS = Instruction Count / (Execution Time × 106)
o MIPS (compiler 1) = (5+1+1) × 109 / (2.5 × 106) = 2800
o MIPS (compiler 2) = (10+1+1) × 109 / (3.75 × 106) = 3200
 So, code from compiler 2 has a higher MIPS rating !!!
Single- vs. Multi-cycle CPU
 Drawbacks of Single Cycle Processor: Long cycle time
o All instructions take as much time as the slowest

ALU Instruction Fetch Reg Read ALU Reg Write

longest delay
Load Instruction Fetch Reg Read ALU Memory Read Reg Write

Store Instruction Fetch Reg Read ALU Memory Write

Branch Instruction Fetch Reg Read ALU

Jump Instruction Fetch Decode

 Alternative Solution: Multicycle implementation

o Break down instruction execution into multiple cycles
Single- vs. Multi-cycle CPU
 Break instruction execution into five steps
o Instruction fetch
o Instruction decode and register read
o Execution, memory address calculation, or branch completion
o Memory access or ALU instruction completion
o Load instruction completion
 One step = One clock cycle (clock cycle is reduced)
o First 2 steps are the same for all instructions

Instruction # cycles Instruction # cycles

ALU & Store 4 Branch 3
Load 5 Jump 2
Single- vs. Multi-cycle Performance
 Assume the following operation times for components:
o Instruction and data memories: 200 ps
o ALU and adders: 180 ps
o Decode and Register file access (read or write): 150 ps
o Ignore the delays in PC, mux, extender, and wires
 Which of the following would be faster and by how much?
o Single-cycle implementation for all instructions
o Multicycle implementation optimized for every class of instructions
 Assume the following instruction mix:
o 40% ALU, 20% Loads, 10% stores, 20% branches, & 10% jumps
Single- vs. Multi-cycle Performance
Instruction Instruction Register ALU Data Register
Total
Class Memory Read Operation Memory Write
ALU 200 150 180 150 680 ps
Load 200 150 180 200 150 880 ps
Store 200 150 180 200 730 ps
Branch 200 150 180 530 ps
Jump 200 150 decode and update PC 350 ps

 For fixed single-cycle implementation:

o Clock cycle = 880 ps determined by longest delay (load instruction)

 For multi-cycle implementation:

o Clock cycle = max (200, 150, 180) = 200 ps (maximum delay at any step)
o Average CPI = 0.4×4 + 0.2×5 + 0.1×4+ 0.2×3 + 0.1×2 = 3.8

 Speedup = 880 ps / (3.8 × 200 ps) = 880 / 760 = 1.16