SV6256P Datasheet

Low Power WiFi Dual Band 802.11 a/b/g/n SoC

General Description The only external clock source needed for
SV6256P based designs is a high speed
The SV6256P is a low-power single chip crystal or oscillator. SV6256P support a
device with the highest level of integration for variety of reference clocks which include 19.2,
internet of thing embedded systems. It is 20, 24, 25, 26, 38.4, 40 and 52 MHz. The USB
designed to support all mandatory IEEE application only support two reference clocks
802.11b data rates of 1, 2, 5.5 and 11 Mbps, which are 25MHz and 40MHz.
all 802.11g payload data rates of 6, 9, 12, 18,
24, 36, 48 and 54 Mbps, as well as 802.11n SV6256P Features
MCS0~MCS7, HT20/HT40, 800ns and 400ns
guard interval. • All CMOS IEEE 802.11 a/b/g/n single chip
• Single stream 802.11n provides highest
It includes a dual band WLAN CMOS efficient throughput and superior RF performance
power amplifier (PA) and an internal low noise for embedded system
amplifier (LNA). The Radio Frequency Front- • Advanced 1x1 802.11n features:
end is single-ended bi-directional input and − Full / Half Guard Interval
output. − Frame Aggregation
− Space Time Block Coding (STBC)
The SV6256P has additional LDOs and DCDC
− Greenfield mode
buck convertor that could provide noise
isolation for digital and analog supplies and • Integrated WLAN CMOS efficient power
excellent power efficient with minimum BOM amplifier with internal power detector and
cost. closed loop power calibration
• Package
While they both provide multiple peripheral − QFN 48L, 6x6 mm, 0.4mm pitch
interfaces including SPI_MASTER,
UART_DATA, UART_DEBUG, I2C, I2S, etc.

All rights reserved Proprietary and confidential information of Shenzhen iComm Semiconductor Co., Ltd. 2019
 SV6256P Datasheet V1.0

VDDIO VDD33

RF single-ended
Input / Output Antenna
LDO_EN
Matching
UART/USB/SDIO/SPI Data SV6256P System Clock

Other GPIOs

SV6256P System Block Diagram

Interface XTAL

19.2M~52M Hz

25M/40M Hz
Application
SPI Master

SPI Data
SPI Data

PSRAM
UART

Flash
PWM
SDIO

ADC
USB

I2C

I2S
SPI Data 1 v

SDIO 1 v

USB 1 v

IOT 2 1 1 5 4 1 1 1 v

Liability Disclaimer
Shenzhen iComm Semiconductor Co., Ltd. reserves the right to make changes without further notice
to the product. Shenzhen iComm Semiconductor Co., Ltd. does not assume any liability arising out of
the application or use of any product or circuits described herein.

Shenzhen iComm Semiconductor Co., Ltd. Proprietary and Confidential Page 2 of 39

 SV6256P Datasheet V1.0

Revision History
Version Date Description
1.0 2021/03/02 Initial release

Shenzhen iComm Semiconductor Co., Ltd. Proprietary and Confidential Page 3 of 39

 SV6256P Datasheet V1.0

Table of Contents
1 System Overview ................................................................................................................. 9

1.1 General Description .................................................................................................... 9

1.2 MAC Features ............................................................................................................. 10

1.3 PHY features ............................................................................................................... 10

1.4 SYSTEM ....................................................................................................................... 10

1.5 HOST INTERFACE ..................................................................................................... 10

1.6 System Clocking and Reset..................................................................................... 11

1.7 Design for Test ........................................................................................................... 11

2 Power Supplies and Power Management ...................................................................... 12

2.1 General Description and PMU Power Connection .............................................. 12

2.2 DLDO ............................................................................................................................ 12

2.3 Buck Converter .......................................................................................................... 12

2.4 Power Management Control .................................................................................... 12

2.5 Power-on Sequence .................................................................................................. 14

2.6 Reset Control .............................................................................................................. 15

3 Interface Description ......................................................................................................... 16

3.1 SPI Data Timing Waveform ...................................................................................... 16

3.2 SDIO Timing Waveform ............................................................................................ 17

3.3 USB Timing Waveform.............................................................................................. 18

4 DC Characteristics ............................................................................................................. 20

4.1 Absolute Maximum Ratings..................................................................................... 20

4.2 Environmental Ratings ............................................................................................. 20

4.3 Thermal Characteristics ........................................................................................... 21

4.4 Electrostatic Discharge Specifications ................................................................. 21

Shenzhen iComm Semiconductor Co., Ltd. Proprietary and Confidential Page 4 of 39

 SV6256P Datasheet V1.0

4.5 Power-On Hours(POH) .............................................................................................. 21

4.6 Recommended Operating Conditions and DC Characteristics ........................ 22

5 Frequency References ...................................................................................................... 24

5.1 Crystal Oscillator Specifications ................................................................................ 24

5.2 External Clock-Requirements and Performance ..................................................... 24

6 Electrical Specifications ................................................................................................... 25

6.1 WLAN RF Performance Specifications .................................................................. 26

7 System Power Consumption ........................................................................................... 28

8 Pin Descriptions ................................................................................................................. 29

8.1 Interface Selection ..................................................................................................... 31

8.2 User Define I/O Function Selection ........................................................................ 34

8.3 IOT ADC ....................................................................................................................... 35

9 Package Information ......................................................................................................... 37

10 Part Number .................................................................................................................... 39

Shenzhen iComm Semiconductor Co., Ltd. Proprietary and Confidential Page 5 of 39

 SV6256P Datasheet V1.0

Lists of Tables
Table 1: SV6256P Power State Description ............................................................... 13

Table 2: Reset Timing Parameters .............................................................................. 15

Table 3: SPI Data Timing Specifications ..................................................................... 16

Table 4: SDIO version 2.0 Timing Specifications ....................................................... 17

Table 5: USB High-Speed Source Electrical Characteristics .................................... 18

Table 6: USB Full-Speed Source Electrical Characteristics ...................................... 18

Table 7: USB Low-Speed Source Electrical Characteristics ..................................... 19

Table 8: Absolute Maximum Ratings ........................................................................... 20

Table 9: Environmental Ratings ................................................................................... 20

Table 10: The thermal characteristics of the SV6256P ............................................. 21

Table 11: ESD Specifications....................................................................................... 21

Table 12: Power-On Hours........................................................................................... 21

Table 13: Recommended Operating Conditions and DC Characteristics ................ 22

Table 14: Crystal Oscillator Specifications.................................................................. 24

Table 15: External Clock-Requirements and Performance ....................................... 24

Table 16: 2.4G WLAN RF Performance Specifications ............................................. 26

Table 17: 5G WLAN RF Performance Specifications ................................................ 27

Table 18: Power Consumption at DCDC mode (DCDC buck convertor is enable) . 28

Table 19: Power Consumption at LDO mode (DCDC buck convertor is disable) ... 28

Table 20: SV6256P Package Pin-out .......................................................................... 30

Table 21: The strapping truth table .............................................................................. 31

Table 22: The strapping pin of GPIO07....................................................................... 31

Table 23: The strapping pin of GPIO14/15 for Flash/PSRAM interface ................... 32

Table 24: The strapping pin of GPIO14/15 for SPI DATA slave interface ................ 32

Shenzhen iComm Semiconductor Co., Ltd. Proprietary and Confidential Page 6 of 39

 SV6256P Datasheet V1.0

Table 25: The strapping pin of GPIO14/15 for SDIO interface .................................. 33

Table 26: The strapping pin of GPIO14/15 for USB slave interface ......................... 33

Table 27: The PAD multiplex for each PAD for IOT application ............................... 34

Table 28: IOT ADC Pin Location.................................................................................. 36

Table 29: IOT ADC Specifications ............................................................................... 36

Table 30: SV6256P Part Number ................................................................................ 39

Shenzhen iComm Semiconductor Co., Ltd. Proprietary and Confidential Page 7 of 39

 SV6256P Datasheet V1.0

List of Figures
Figure 1: SV6256P Block Diagram ................................................................................ 9

Figure 2 : SV6256P Power Connection....................................................................... 12

Figure 3: SV6256P Power State .................................................................................. 13

Figure 4: Power-on sequence ...................................................................................... 14

Figure 5 : Reset Timing ................................................................................................ 15

Figure 6: SPI Data TIMING WAVEFORM ................................................................... 16

Figure 7: SDIO Timing Waveform ................................................................................ 17

Figure 8: RF Front-End Reference Topology for RF Performance ........................... 25

Figure 9: SV6256P QFN Pin Assignment (top view).................................................. 29

Figure 10: ADC Block diagram..................................................................................... 36

Figure 11: QFN 6 x 6 mm Package Dimensions ........................................................ 38

Shenzhen iComm Semiconductor Co., Ltd. Proprietary and Confidential Page 8 of 39

 SV6256P Datasheet V1.0

1 SYSTEM OVERVIEW
DC-DC
MCU Power
Supply
LDO
(Optional)
RAM PMU Ctrl 32K RTC External
Sleep CLK

ROM Dedicated
XTAL OSC Crystal

LDO_EN
eFuse POR
IO

High Speed UART

SYSTEM

SYSTEM BUS
UART
WDT
DMA SPI DATA

TIMER SDIO
INTERRUPT
I2C

SPI Master GPIOs

PADMUX
PWMs
USB
ADCs

I2S TX/RX
802.11 a/b/g/n Flash/PSRAM CTRL
802.11n 802.11n
Radio GPIOs
PHY MAC

Figure 1: SV6256P Block Diagram

1.1 GENERAL DESCRIPTION

The SV6256P WLAN is designed to support IEEE 802.11 a/b/g/n single stream with the state of-
the-art design techniques and process technology to achieve low power consumption and high
throughput performance to address the requirement of mobile and handheld devices. The
SV6256P WLAN low power function uses the innovative design techniques and the optimized
architecture which best utilizes the advanced process technology to reduce active and idle power,
and achieve extreme low power consumption at sleep state to extend the battery life. The
SV6256P WLAN A-MPDU Tx function maximizes the throughput performance while achieving the
best buffer utilization.

Shenzhen iComm Semiconductor Co., Ltd. Proprietary and Confidential Page 9 of 39

 SV6256P Datasheet V1.0

1.2 MAC FEATURES

◼ 802.11 a/b/g/n/e/i/d
◼ 802.11n features
– A-MPDU Tx & Rx
– Support immediate Block-Ack
◼ AP/STA mode
– Soft-AP
◼ Rate adaption mechanism
◼ WFA features
– WEP/TKIP/WPA/WPA2
– WMM/WMM PS

1.3 PHY FEATURES

◼ 802.11b, 11g, 11a, and 802.11n 1T1R
◼ Short Guard Interval
◼ Greenfield mode
◼ STBC in RX mode
◼ Enhanced and robust sensitivity for wider coverage range
◼ Supports calibration algorithm to handle no-idealities effects from CMOS RF block

1.4 SYSTEM
◼ Andes Technology N10 processor w/ ILM/DLM and I-cache
◼ 128K ROM and 192 KB SRAM for Instruction and data SRAM in total
◼ 8K retention SRAM
◼ Suspend/Wake-up manger controller
◼ Two channel DMA off load CPU loading.
◼ One Flash controller supports both Flash and PSRAM up to 64MB/64Mb with XIP
◼ One I2S TX/RX channel for 8~32bits/8~192KHz in master/slave mode.
◼ One SPI master
◼ One I2C
◼ One UART_Debug
◼ Four 10-bit ADC for IOT
◼ Five PWMs
◼ Four millisecond timers
◼ Four microsecond timers
◼ Two watchdog
◼ All pins can be multiplexed to GPIO by user scenario

1.5 HOST INTERFACE

◼ High Speed UART
⚫ Support RTSN/CTSN/RX/TX, 4 pins
⚫ Baud rate up to 4.8MHz
◼ UART
⚫ Support RX/TX, 2 pins
⚫ Baud rate up to 921600
◼ SPI Data
⚫ Provide proprietary/user CMD
◼ SDIO , SDIO 2.0 support both 1.8v and 3.3v in VIO

Shenzhen iComm Semiconductor Co., Ltd. Proprietary and Confidential Page 10 of 39

 SV6256P Datasheet V1.0

◼ USB

1.6 SYSTEM CLOCKING AND RESET

The SV6256P has a system clocking block and reset which controls the clocks and power going
to other internal modules. Its inputs consist of sleep requests from these modules and its outputs
consist of clock enable and power signals which are used to gate the clocks going to internal
modules. The system clocking and reset block also manages resets going to other modules
within the device.

1.7 DESIGN FOR TEST

It also has features which enable testing of digital blocks via ATPG scan, memories via MBIST,
analog components, and the radio.

Shenzhen iComm Semiconductor Co., Ltd. Proprietary and Confidential Page 11 of 39

 SV6256P Datasheet V1.0

2 POWER SUPPLIES AND POWER MANAGEMENT

2.1 GENERAL DESCRIPTION AND PMU POWER CONNECTION
The power management unit (PMU) contains Low Dropout Regulators (LDOs), buck DC-DC
converter and reference bandgap circuit.

The PMU integrated multi-LDOs and one buck converter. Those circuits are optimized for the given
functions by balancing quiescent current, dropout voltage, line / load regulation, ripple rejection and
output noise.

The input voltage of the buck converter is 3.3V. Its output voltage is 1.6V and feeds into the input
power of the RF circuit and DLDO which has 1.2V output voltage for all digital circuits.

Figure 2 shows the typical power connection for SV6256P. DLDO and some RF circuits are powered
by the buck converter output. The VDDIO is a power input which may be 3.3V from the host side. The
connection structure is shown in the figure below.

VDD33_PA
PA
3.3V

RF
(including VCO)

RF
VBAT Buck DC-DC VDDLX_DCDC 1.6V BB
Convertor
VDD33_DCDC VDD16_ABB
VDD16_SYN Digital

DLDO
VDDIO DVDDIO1/DVDDIO3/VDD33_USB RTC & PMU

DVDD12
1.2V

Figure 2 : SV6256P Power Connection

2.2 DLDO
The DLDO is integrated in the PMU to supply digital core. It converts voltage from 1.6V input to 1.2V
output which suits the digital circuits. The input is typically connected to the buck’s output.

2.3 BUCK CONVERTER

The regulator is a DC-DC step-down converter (buck converter) to source 300mA (max.) with 2.0V to
1.5V programmable output voltage based on the register setting. It supplies power for the RF circuit
and DLDO.

2.4 POWER MANAGEMENT CONTROL

Shenzhen iComm Semiconductor Co., Ltd. Proprietary and Confidential Page 12 of 39
 SV6256P Datasheet V1.0

There are three power modes that SV6256P operates when it is initialized: HOST_OFF, ACTIVE
mode and SLEEP mode. There are two intermediate system transition modes: FW_DOWNLOAD
and WARM_UP mode. The following are the brief introduction to each mode.

HOST OFF
(LDO_EN=0)

Power & Clock settling done (<1.3 ms)

FW
DOWNLOAD

FW download done

ACTIVE Clock settling

WARM
SLEEP criteria UP

Interrupt occurs

SLEEP

Figure 3: SV6256P Power State

Table 1: SV6256P Power State Description

State Description
When LDO_EN pin is de-asserted and logically low, the chip is brought
to this state immediately.
HOST OFF Sleep clock and internal power supply is disabled.
After LDO_EN pin is asserted, the internal power and clock will be
settled down within 1.3 ms.
FW DOWNLOAD States for firmware download after power and clock is settled down.
The host controller can determine when to enter sleep to turn off most
circuit in SV6256P. All the RF, DPLL circuits are turned off. In sleep
SLEEP mode, the system could be awakened after the sleep time is expired or
by an external wake up signal from the host controller.
All internal states are maintained and the Crystal oscillator is disabled.
The system transitions from SLEEP to ACTIVE. The crystal or oscillator
WARM UP
is brought up and the PLL is enabled.
The high speed clock is operational and sent to each block by the clock
control register.
ACTIVE
The RF circuit is enabled to transmit or receive data, and the whole
system is under normal operation.

Shenzhen iComm Semiconductor Co., Ltd. Proprietary and Confidential Page 13 of 39

 SV6256P Datasheet V1.0

2.5 POWER-ON SEQUENCE

Figure 4 shows the power-on sequence of the SV6256P from power-up to firmware download,
including the initial device power-on reset evoked by LDO_EN signal. The LDO_EN input level must
be kept the same as VDDIO voltage level. After initial power-on, the LDO_EN signal can be held low
to turn off the SV6256P or pulsed low to induce a subsequent reset. After LDO_EN is assert and host
starts the power-on sequence of the SV6256P. From that point, the typical SV6256P power-on
sequence is shown below:
1. Within 1.3 millisecond, the internal power-on reset (POR) will be done. And host could
download firmware code of DPLL setting if the crystal is not default setting, 26MHz. The
internal running clock is crystal frequency.
2. After 100us of DPLL settling time, host could set internal clock to full speed and finish all the
downloading of firmware code.
Ramp time > 50 µs
VBAT>3.13 V
VBAT

Ramp time > 50 µs

VDDIO>3.13 V 1.7V
VDDIO
＊
>60µS

LDO_EN

<50 µs
DVDD12
<450 µs
<50 µs
DVDD16

<900us
Internal POR
DPLL settling time<100us
>1.3 ms
>100 µs

FW Download
DPLL configure setting Host downloads code
(if crystal is not 26MHz) (Host could change
internal clock to DPLL)

Note: ＊
For IOT application, the timing between VDDIO and LDO_EN should be greater than
[external flash VCC (min) to /CS Low+ 60us]. For example, if we use W25Q16JV as external
flash, the timing between VDDIO and LDO_EN should be greater than (20us+60us).

Figure 4: Power-on sequence

Shenzhen iComm Semiconductor Co., Ltd. Proprietary and Confidential Page 14 of 39

 SV6256P Datasheet V1.0

t1
VBAT_Min

VBAT
VDD_Min

VDDIO

VIL_nRS
LDO_EN T

Figure 5 : Reset Timing

Table 2: Reset Timing Parameters

Parameters Description Min. Unit

t1 Duration of LDO_EN signal level < VIL_nRST to 30 us
reset the chip

2.6 RESET CONTROL

The SV6256P LDO_EN pin can be used to completely reset the entire chip. After this signal has been
de-asserted, the SV6256P is in off mode waits for host communication. Until then, the MAC, BB, and
SOC blocks are powered off and all modules are held in reset. Once the host has initiated
communication, the SV6256P turns on its crystal and later on DPLL. After all clocks are stable and
running, the resets to all blocks are automatically de-asserted.

Shenzhen iComm Semiconductor Co., Ltd. Proprietary and Confidential Page 15 of 39

 SV6256P Datasheet V1.0

3 INTERFACE DESCRIPTION
3.1 SPI DATA TIMING WAVEFORM

CS#

tCHSL tSLCH tCHL tCLH tSHL

CLK

tDVCH tCHDX

MOSI MSB

tCLQV tSHQX

MISO high MSB high

Figure 6: SPI Data TIMING WAVEFORM

Table 3: SPI Data Timing Specifications

Symbol Parameter Min. Typ. Max. Unit

tCHSL CS# active hold time 10 ns
tSLCH CS# active setup time 3 ns
tSHL CS# inactive time 300 ns
tCHL CLK high time 12.5 ns
tCLH CLK low time 12.5 ns
tDVCH Data in (MISO) setup time 3 ns
tCHDX Data in (MISO) hold time 3 ns
tCLQV Data output delay 6.5 ns
tSHQX Data output disable time 6 ns

Shenzhen iComm Semiconductor Co., Ltd. Proprietary and Confidential Page 16 of 39

 SV6256P Datasheet V1.0

3.2 SDIO TIMING WAVEFORM

Figure 7: SDIO Timing Waveform

Table 4: SDIO version 2.0 Timing Specifications

Symbol Parameter Min. Typ. Max. Unit

Clock CLK (All values are referred to min(V IH) and max (VIL).
fpp Clock frequency Data Transfer Mode 0 50 MHz
tTLH Clock rise time 3 ns
tTHL Clock fall time 3 ns
Inputs CMD, DAT (reference to CLK)
tISU Input set-up time 6 ns
tIH Input hold time 2 ns
Outputs CMD, DAT (reference to CLK)
Output Delay time during Data
tODLY 14 ns
Transfer Mode
tOH Output Hold time 2.5 Ns

Shenzhen iComm Semiconductor Co., Ltd. Proprietary and Confidential Page 17 of 39

 SV6256P Datasheet V1.0

3.3 USB TIMING WAVEFORM

Table 5: USB High-Speed Source Electrical Characteristics

Symbol Description Condition Min. Typ. Max. Unit

Driver characteristics
tHSRLEW Slew rate of rising edge - - - 1600 V/usec
tHSFLEW Slew rate of falling edge - - - 1600 V/usec
Driver - Specified by eye pattern - - - -
waveform template in USB2.0 spec.
Clock Timings
THSRDRATE High-speed data rate 479.76 - 480.24 Mbps
High-Speed Data Timings
TJ Data source jitter Source and receiver jitter specified by the eye pattern template
RXJT Receiver jitter tolerance defined in USB2.0 spec.

Table 6: USB Full-Speed Source Electrical Characteristics

Symbol Description Condition Min. Typ. Max. Unit

Driver characteristics
tFR Rise time CL = 50 pF 4 - 20 ns
10% ~ 90% of |VOH – VOL|
tHSFLEW Fall time CL = 50 pF 4 - 20 ns
90% ~ 10% of |VOH – VOL|
tFRMA Differential rise/fall time Specified by eye pattern 90 - 110 %
matching (tFR/tFF) template in USB2.0 spec.
Clock Timings
TFSTXDRATE Full-speed TX data rate 11.994 - 12.006 Mbps
TFSRXDRATE Full-speed RX data rate 11.97 - 12.03 Mbps
Full-Speed Data Timings
TFDEOP Source jitter for differential - -2 - 5 ns
transition to SE0 transition
TJR1 Receiver jitter To next transition 18.5 - 18.5 ns
TJR2 Receiver jitter For paired transition -9 - 9 ns
TFEOPT Source SE0 interval of EOP - 160 - 175 ns
TFEOPR Receiver SE0 interval of EOP - 82 - - ns
TFST Width of SE0 interval during - - - 14 ns
differential transition

Shenzhen iComm Semiconductor Co., Ltd. Proprietary and Confidential Page 18 of 39

 SV6256P Datasheet V1.0

Table 7: USB Low-Speed Source Electrical Characteristics

Symbol Description Condition Min. Typ. Max. Unit

Driver characteristics
tFR Rise time CL = 200 pF~ 600pF 75 - 300 ns
10% ~ 90% of |VOH–VOL|
tHSFLEW Fall time CL = 200pF ~ 600pF 75 - 300 ns
90% ~ 10% of |VOH–VOL|
tFRMA Differential rise/fall time Specified by eye pattern 80 - 125 %
matching (tFR/tFF) template in USB2.0 spec.
Clock Timings
TFSTXDRATE Low-speed TX data rate 1.49925 - 1.50075 Mbps
TFSRXDRATE Low-speed RX data rate 1.49925 - 1.50075 Mbps
Full-Speed Data Timings
TFDEOP Source jitter for differential - -40 - 100 ns
transition to SE0 transition
TJR1 Receiver jitter To next transition -75 - 75 ns
TJR2 Receiver jitter For paired transition -45 - 45 ns
TFEOPT Source SE0 interval of EOP - 1.25 - 1.5 ns
TFEOPR Receiver SE0 interval of EOP - 670 - - ns
TFST Width of SE0 interval during - - - 210 ns
differential transition

Shenzhen iComm Semiconductor Co., Ltd. Proprietary and Confidential Page 19 of 39

 SV6256P Datasheet V1.0

4 DC CHARACTERISTICS
4.1 ABSOLUTE MAXIMUM RATINGS
The absolute maximum ratings in Table 8 indicate levels where permanent damage to the device can
occur, even if these limits are exceeded for only a brief duration. Functional operation is not
guaranteed under these conditions. Operation at absolute maximum conditions for extended periods
can adversely affect long-term reliability of the device.

Table 8: Absolute Maximum Ratings

Symbol Description Max Rating Unit

(domain)
VDD16 VDD input for analog 1.6V -0.3 to 3.6 V
VDD33_SX VDD input for external -0.3 to 3.6 V
components I/O control
VDD33_RF VDD input for external -0.3 to 3.6 V
components I/O control
DVDDIO1 VDD input for I/O -0.3 to 3.6 V
DVDDIO3 VDD input for I/O -0.3 to 3.6 V
VDD33_USB VDD input for I/O -0.3 to 3.6 V
DVDD12 VDD output for internal digital -0.3 to 1.32 V
circuit
VDD16_DCDC VDD input for digital circuit’s -0.3 to 3.6 V
LDO
VDD33_DCDC VDD input for DCDC -0.3 to 3.6 V

4.2 ENVIRONMENTAL RATINGS

The environmental ratings are shown in Table 9: Environmental Ratings
Table 9: Environmental Ratings

Part Number Value Units

Operating Temperature(TA) SV6256P -40 to +85 °C

4.2.1 Storage Condition

The calculated shelf life in sealed bag is 12 months if stored between 0°C and 40°C at less than 90%
relative humidity (RH). After the bag is opened, devices that are subjected to solder reflow or other
high temperature processes must be handled in the following manner:
a) Mounted within 168 hours of factory conditions < 30 °C /60%RH
b) Storage humidity needs to maintained at <10% RH
c) Baking is necessary if customer exposes the component to air over 168 hours, baking
condition: 125°C / 8 hours

Shenzhen iComm Semiconductor Co., Ltd. Proprietary and Confidential Page 20 of 39

 SV6256P Datasheet V1.0

4.3 THERMAL CHARACTERISTICS

Thermal characteristics without external heat sink in still air condition

Table 10: The thermal characteristics of the SV6256P

Symbol Description Typ. Unit

TJ Maximum Junction Temperature (Plastic Package) 125 °C
θJA Thermal Resistance θJA (°C /W) for JEDEC 4L system PCB 37.8 °C/W
θJC Thermal Resistance θJC (°C /W) for JEDEC 4L system PCB TBD °C/W
Thermal Characterization parameter ΨJt (°C /W) for JEDEC
ΨJt 4.13 °C/W
4L system PCB
Maximum Lead Temperature (Soldering 10s) 260 °C
Notes: * JEDEC 51-7 system FR4 PCB size: 3” x 4.5” (76.2 x 114.3 mm)
* Thermal characteristics without external heat sink in still air condition

4.4 ELECTROSTATIC DISCHARGE SPECIFICATIONS

This is an ESD sensitive product. Observe precaution and handle with care. Extreme caution must be
exercised to prevent electrostatic discharge (ESD) damage. Proper use of wrist and heel grounding
straps to discharge static electricity is required when handling these devices.

Table 11: ESD Specifications

Pin Type Test Condition ESD Rating Unit

Human Body Mode refers to MIL-STD- Pass ±2.5 KV
(HBM) 883G Method 3015.7
Charged Device JEDEC –500 +500 V Pass 500 V
Model(CDM) specification JESD22-
C101, all pins

4.5 POWER-ON HOURS(POH)

This information is provided solely for your convenience and does not extend or modify the warranty
provided under iComm's standard terms and conditions for iComm semiconductor products.

Table 12: Power-On Hours

OPERATION CONDITION Part Number Power-On

Hours(POH)(hours)
TA up to 85°C a SV6256P 87600
a. The TX duty cycle (power amplifier ON time) is assumed to be 10% of the device POH. Of the
remaining 90% of the time, the device can be in any other state.

Shenzhen iComm Semiconductor Co., Ltd. Proprietary and Confidential Page 21 of 39

 SV6256P Datasheet V1.0

4.6 RECOMMENDED OPERATING CONDITIONS AND DC CHARACTERISTICS

Table 13: Recommended Operating Conditions and DC Characteristics

Domain(Symbol) Description Min. Typ. Max. Unit

VDD16 VDD input for analog 1.6V 1.6 V
VDD33_SX VDD input for external 3.13 3.3 3.46 V
components I/O control
VDD33_RF VDD input for external 3.13 3.3 3.46 V
components I/O control
DVDDIO1 VDD input for GPIO pins 3.13 3.3 3.46 V
DVDDIO3 VDD input for GPIO pins 3.13 3.3 3.46 V
(same level as DVDDIO1)
VDD33_USB VDD input for HSDP/HSDM 3.13 3.3 3.46 V
VDD input for GPIO pins 1.71 3.3 3.46
DVDD12 VDD output for internal digital 1.2 V
circuit
VDD16_DCDC VDD input for digital circuit’s 1.6 V
LDO
VDD33_DCDC VDD input for DCDC 3.13 3.3 3.46 V
(VIL) Input Low voltage when -0.3 0.8 V
VDDIO=3.3V
Input Low voltage when -0.3 0.6 V
VDDIO=1.8V
(VIH) Input High voltage when 2 3.6 V
VDDIO=3.3V
Input High voltage when 1.2 3.6 V
VDDIO=1.8V
(VT+) Schmitt trigger low to high 1.6 1.74 1.89 V
threshold voltage when
VDDIO=3.3V
Schmitt trigger low to high 1.03 1.07 1.15 V
threshold voltage when
VDDIO=1.8V
(VT-) Schmitt trigger high to low 1.27 1.4 1.56 V
threshold voltage when
VDDIO=3.3V
Schmitt trigger high to low 0.67 0.7 0.72 V
threshold voltage when
VDDIO=1.8V
(VOL) Output low voltage when 0.4 V
VDDIO=3.3V
Output low voltage when 0.45 V
VDDIO=1.8V
(VOH) Output high voltage when 2.4 V
VDDIO=3.3V
Output high voltage when 1.3 V
VDDIO=1.8V

Shenzhen iComm Semiconductor Co., Ltd. Proprietary and Confidential Page 22 of 39

 SV6256P Datasheet V1.0

Domain(Symbol) Description Min. Typ. Max. Unit

(RPD) Input weakly pull-down KΩ
resistance when
VDDIO=3.3V.
All GPIO pins have internal
weakly pull- down option
except that GPIO_5 has
internal weakly pull-up option
(RPU) Input weakly pull-high KΩ
resistance when
VDDIO=3.3V.
All GPIO pins have internal
weakly pull- down option
except that GPIO_5 has
internal weakly pull-up option
(IOL) Low level output current @ 11.9 17.7 23.4 mA
VOL(max), 8mA setting
Low level output current @ 15.8 23.5 31.1 mA
VOL(max), 12mA setting
(IOH) High level output current @ 17.2 34.1 58.8 mA
VOH(min), 8mA setting
High level output current @ 23.9 47.2 81.5 mA
VOH(min), 12mA setting

Shenzhen iComm Semiconductor Co., Ltd. Proprietary and Confidential Page 23 of 39

 SV6256P Datasheet V1.0

5 FREQUENCY REFERENCES
5.1 CRYSTAL OSCILLATOR SPECIFICATIONS
Table 14: Crystal Oscillator Specifications

Parameter Condition/Notes Min. Typ. Max. Unit

Frequency Range − Between 19.2MHz~52MHz
Crystal
− − 10 pF
load Capacitance
ESR − − − 70 
Frequency tolerance
Initial and − -20ppm − 20ppm ppm
over temperature

5.2 EXTERNAL CLOCK-REQUIREMENTS AND PERFORMANCE

Table 15: External Clock-Requirements and Performance

Parameter Condition/Notes Min. Typ. Max. Unit

Frequency Range − Between 19.2MHz~52MHz
OSCIN
AC-couple analog signal 400 − 1500 mVPP
Input Voltage
Frequency
tolerance
− -20ppm − 20ppm ppm
Initial and
over temperature
Duty Cycle 26MHz clock 40 50 60 %
26MHz clock at 1KHz offset − − −119 dBc/Hz
Phase Noise 26MHz clock at 10KHz offset − − −129 dBc/Hz
(802.11a/b/g) 26MHz clock at 100KHz offset − − −134 dBc/Hz
26MHz clock at 1MHz offset − − −139 dBc/Hz
26MHz clock at 1KHz offset − − −125 dBc/Hz
Phase Noise 26MHz clock at 10KHz offset − − −135 dBc/Hz
(802.11n 2.4/5GHz) 26MHz clock at 100KHz offset − − −140 dBc/Hz
26MHz clock at 1MHz offset − − −145 dBc/Hz

Shenzhen iComm Semiconductor Co., Ltd. Proprietary and Confidential Page 24 of 39

 SV6256P Datasheet V1.0

6 Electrical Specifications

Antenna
Matching

RF_IO

RF Port Antenna Port

Figure 8: RF Front-End Reference Topology for RF Performance

Note: All specifications are measured at the RF Port unless otherwise specified.

Shenzhen iComm Semiconductor Co., Ltd. Proprietary and Confidential Page 25 of 39

 SV6256P Datasheet V1.0

6.1 WLAN RF PERFORMANCE SPECIFICATIONS

Table 16: 2.4G WLAN RF Performance Specifications

Parameter Condition/Notes Min. Typ. Max. Unit

Frequency Range 2412 - 2484 MHz
CCK, 1 Mbps -95.5 dBm
Rx Sensitivity CCK, 2 Mbps -93.5 dBm
(CCK) CCK, 5.5 Mbps -91.0 dBm
CCK, 11 Mbps -88.0 dBm
OFDM, 6 Mbps -91.5 dBm
OFDM, 9 Mbps -90.0 dBm
OFDM, 12 Mbps -88.0 dBm
Rx Sensitivity OFDM, 18 Mbps -86.0 dBm
(OFDM) OFDM, 24 Mbps -82.5 dBm
OFDM, 36 Mbps -79.5 dBm
OFDM, 48 Mbps -74.5 dBm
OFDM, 54 Mbps -73.5 dBm
HT20, MCS0 -91.0 dBm
Rx Sensitivity HT20, MCS1 -88.0 dBm
(HT20) HT20, MCS2 -86.0 dBm
Greenfield HT20, MCS3 -81.5 dBm
800nS GI HT20, MCS4 -79.0 dBm
Non-STBC HT20, MCS5 -74.5 dBm
HT20, MCS6 -73.5 dBm
HT20, MCS7 -72.5 dBm
Parameter Condition/Notes Min. Typ. Max. Unit
CCK, 1 Mbps
41 dB
RX Adjacent Channel (30 MHz offset)
Rejection (CCK) CCK, 11 Mbps
41 dB
(25 MHz offset)
OFDM, 6 Mbps
39 dB
RX Adjacent Channel (25 MHz offset)
Rejection (OFDM) OFDM, 54 Mbps
23 dB
(25 MHz offset)
HT20, MCS0
38 dB
RX Adjacent Channel (25 MHz offset)
Rejection (HT20) HT20, MCS7
21 dB
(25 MHz offset)
CCK, 1-11 Mbps 19 dBm
TX Output Power
OFDM, 54 Mbps 16 dBm
(with PADPD)
HT20, MCS7 15 dBm

Shenzhen iComm Semiconductor Co., Ltd. Proprietary and Confidential Page 26 of 39

 SV6256P Datasheet V1.0

Table 17: 5G WLAN RF Performance Specifications

Parameter Condition/Notes Min. Typ. Max. Unit

Frequency Range 5180 - 5850 MHz
OFDM, 6 Mbps -91.0 dBm
OFDM, 9 Mbps -89.5 dBm
OFDM, 12 Mbps -88.0 dBm
Rx Sensitivity OFDM, 18 Mbps -86.0 dBm
(OFDM) OFDM, 24 Mbps -82.5 dBm
OFDM, 36 Mbps -79.5 dBm
OFDM, 48 Mbps -74.5 dBm
OFDM, 54 Mbps -73.5 dBm
HT20, MCS0 -90.0 dBm
HT20, MCS1 -87.5 dBm
HT20, MCS2 -85.5 dBm
Rx Sensitivity HT20, MCS3 -81.5 dBm
Greenfield
HT20, MCS4 -79.0 dBm
800nS GI
HT20, MCS5 -74.5 dBm
Non-STBC
HT20, MCS6 -73.0 dBm
HT20, MCS7 -72.0 dBm
HT40, MCS0 -87.0 dBm
HT40, MCS7 -68.5 dBm
Parameter Condition/Notes Min. Typ. Max. Unit
OFDM, 6 Mbps
28 dB
RX Adjacent Channel (20 MHz offset)
Rejection (OFDM) OFDM, 54 Mbps
19 dB
(20 MHz offset)
HT20, MCS0
27 dB
RX Adjacent Channel (20 MHz offset)
Rejection (HT20) HT20, MCS7
6 dB
(20 MHz offset)
OFDM, 54 Mbps 13.5 dBm
TX Output Power
HT20, MCS7 13 dBm
(with PADPD)
HT40, MCS7 13 dBm

Shenzhen iComm Semiconductor Co., Ltd. Proprietary and Confidential Page 27 of 39

 SV6256P Datasheet V1.0

7 System Power Consumption

Table 18: Power Consumption at DCDC mode (DCDC buck convertor is enable)

WLAN Operational Modes Typ.d Unit

OFFa 2 uA
Rx, CCK, 1 Mbps 68 mA
Rx, OFDM, 54 Mbps 68 mA
Rx, HT20, MCS7 68 mA
Rx, HT40, MCS7 75 mA
Rx, 5.18G HT20, MCS7 88 mA
Rx, 5.805G HT20, MCS7 88 mA
Rx, 5.18 G HT40, MCS7 97 mA
Rx, 5.805G HT40, MCS7 97 mA
Tx, CCK, 1 Mbps 307 mA
Tx, OFDM, 54 Mbps@15dBm 256 mA
Tx, HT20, MCS7@15dBm 260 mA
Tx, HT40, MCS7@15dBm 260 mA
Tx, 5.18 G HT20, MCS7 310 mA
Tx, 5.805G HT20, MCS7 293 mA

Table 19: Power Consumption at LDO mode (DCDC buck convertor is disable)

WLAN Operational Modes Typ.d Unit

OFFa 2 uA
Rx, CCK, 1 Mbps 113 mA
Rx, OFDM, 54 Mbps 113 mA
Rx, HT20, MCS7 113 mA
Rx, HT40, MCS7 124 mA
Rx, 5.18G HT20, MCS7 133 mA
Rx, 5.805G HT20, MCS7 133 mA
Rx, 5.18 G HT40, MCS7 142 mA
Rx, 5.805G HT40, MCS7 142 mA
Tx, CCK, 1 Mbps@18dBm 328 mA
Tx, OFDM, 54 Mbps@15dBm 280 mA
Tx, HT20, MCS7@15dBm 283 mA
Tx, HT40, MCS7@15dBm 285 mA
Tx, 5.18 G HT20, MCS7 356 mA
Tx, 5.805G HT20, MCS7 335 mA
a. OFF mode test condition: VBAT=3.3V, VIO=3.3V, LDO_EN=0V.
b. Intra-beacon Sleep when MCU is turn on.
It is used in the applications that require the CPU to be working.
c. Intra-beacon Sleep when MCU is turn off.
d. Conditions: VBAT at 3.3v, VDDIO at 3.3V, 25°C.

Shenzhen iComm Semiconductor Co., Ltd. Proprietary and Confidential Page 28 of 39

 SV6256P Datasheet V1.0

8 Pin Descriptions
This section contains a listing of the signal descriptions (see Figure 9 for the SV6256P QFN package
pin-out)

38

37
48

47

46

45

44

43

42

41

40

39

VDD33_SX
VDD33_RF

VDD33_RF
RF_IO_2G

RF_IO_5G

VDD16
GND

GND

GND

GND

GND

GND
1 GPIO22 VDD33_SX 36

2 GPIO21 XTALO 35

3 GPIO20 XTALI 34

4 GPIO00 GPIO19 33

5 GPIO01 GPIO18 32

6 GPIO02 GPIO17 31

7 GPIO03 SV6256P GPIO16 30

8 GPIO04 GPIO15 29

9 GPIO05 GPIO14 28

10 GPIO06 DVDDIO3 27

11 GPIO07 DVDD12 26

12 DVDDIO1 VDD16_DCDC 25
VDDLX_DCDC
VDD33_DCDC
VDD33_USB
LDO_EN

GPIO08

GPIO09

GPIO10

GPIO11

GPIO12

GPIO13

HSDM
HSDP
13

14

15

16

17

18

19

20

21

22

23

24

Figure 9: SV6256P QFN Pin Assignment (top view)

Shenzhen iComm Semiconductor Co., Ltd. Proprietary and Confidential Page 29 of 39

 SV6256P Datasheet V1.0

Table 20: SV6256P Package Pin-out

No. Name Description Type

1 GPIO22 General Purpose I/O Pins I/O
2 GPIO21 General Purpose I/O Pins I/O
3 GPIO20 Strapping Purpose I/O Pins I/O
4 GPIO00 General Purpose I/O Pins I/O
5 GPIO01 General Purpose I/O Pins I/O
6 GPIO02 General Purpose I/O Pins I/O
7 GPIO03 General Purpose I/O Pins I/O
8 GPIO04 General Purpose I/O Pins I/O
9 GPIO05 General Purpose I/O Pins I/O
10 GPIO06 General Purpose I/O Pins I/O
11 GPIO07 Strapping Purpose I/O Pins I/O
12 DVDDIO1 VIO input for GPIO00~07/GPIO20~22 Power
13 LDO_EN Reset signal to power down IC Input
14 GPIO08 General Purpose I/O Pins I/O
15 GPIO09 General Purpose I/O Pins I/O
16 GPIO10 General Purpose I/O Pins I/O
17 GPIO11 General Purpose I/O Pins I/O
18 GPIO12 General Purpose I/O Pins I/O
19 GPIO13 General Purpose I/O Pins I/O
20 VDD33_USB VIO input for GPIO08~13/HSDP/HSDM Power
21 HSDP HSDP I/O
22 HSDM HSDM I/O
23 VDD33_DCDC analog 3.3V input for DCDC Power
24 VDDLX_DCDC DCDC buck regulator: output to inductor Power
25 VDD16_DCDC DCDC 1.6V Power
26 DVDD12 Digital 1.2V input Power
27 DVDDIO3 VIO input for GPIO14~19 Power
28 GPIO14 Strapping Purpose I/O Pins I/O
29 GPIO15 Strapping Purpose I/O Pins I/O
30 GPIO16 General Purpose I/O Pins I/O
31 GPIO17 General Purpose I/O Pins I/O
32 GPIO18 General Purpose I/O Pins I/O
33 GPIO19 General Purpose I/O Pins I/O
34 XTALI Input of crystal clock reference Input
35 XTALO Output of crystal clock reference output
36 VDD33_SX analog 3.3V input Power
37 VDD16 analog 1.6V input Power
38 VDD33_SX analog 3.3V input Power
39 VDD33_RF analog 3.3V input Power
40 VDD33_RF analog 3.3V input Power
41 GND Ground GND
42 RF_IO_5G 5 GHz RF input & output port RF I/O
43 GND Ground GND

Shenzhen iComm Semiconductor Co., Ltd. Proprietary and Confidential Page 30 of 39

 SV6256P Datasheet V1.0

No. Name Description Type

44 GND Ground GND
45 GND Ground GND
46 RF_IO_2G 2.4 GHz RF input & output port RF I/O
47 NC NC Pin NC
48 NC NC Pin NC

8.1 INTERFACE SELECTION

SV6256P has bootstrap pins to select interface which including debug interface, host I/O.
There are GPIO07, GPIO14, GPIO15 and GPIO20 (see Table 21 for detail). The bootstrap
pin of GPIO07 decides switching the debug interface out to GPIOs (see Table 22 for detail).
The bootstrap pins of GPIO14 and GPIO15 decode switch the host IO out to GPIOs (see
/Table 24/Table 25/Table 26). The bootstrap pin of GPIO20 decides switching 25MHz or
40MHz clock when using USB interface (see Table 21 for detail).

Table 21: The strapping truth table

strapping truth table

Interface mode Description
GPIO[07]
0 AICE debug for ICE debug interface
1 NC NC (default)
GPIO[15], GPIO[14]
00 SPIFL-E SPI flash w/I in-place execution (default)
01 SPIDATA SPI data mode
10 SDIO SDIO mode
11 USB USB mode
GPIO[20]
0 USB_XO25M for USB 25MHz clock (default)
1 USB_XO40M for USB 40MHz clock

Table 22: The strapping pin of GPIO07

GPIO07 Low High

I/O Function I/O Function
Name I/O PULL I/O PULL
Pin No. SPIFL-E/SPIDATA/SDIO/USB SPIFL-E SPIDATA/SDIO/USB
4 GPIO00 I/O F TMSC I/O F GPIO00 NC
5 GPIO01 I F TCKC I F GPIO01 NC
6 GPIO02 I PU nSRST I PU GPIO02 NC
7 GPIO03 I F UART0_RXD I F GPIO03 NC
8 GPIO04 O F UART0_TXD O F NC NC

Shenzhen iComm Semiconductor Co., Ltd. Proprietary and Confidential Page 31 of 39

 SV6256P Datasheet V1.0

Table 23: The strapping pin of GPIO14/15 for Flash/PSRAM interface

GPIO15/14 2'b00
Pin No. Name I/O PULL I/O Function
9 GPIO05 O F UART1_RTS
10 GPIO06 I F UART1_RXD
11 GPIO07 O PU UART1_TXD
14 GPIO08 I/O F GPIO08
15 GPIO09 I F UART1_CTS
16 GPIO10 I/O F GPIO10
17 GPIO11 I/O F GPIO11
18 GPIO12 I/O F GPIO12
19 GPIO13 O PU SPI_PSRAM_CSN
28 GPIO14 I/O PD SPI_flash_IO0_DI (MOSI)
29 GPIO15 O PD SPI_flash_CLK
30 GPIO16 I/O PU SPI_flash_IO3_HD
31 GPIO17 O PU SPI_flash_CSN
32 GPIO18 I/O PD SPI_flash_IO1_DO (MISO)
33 GPIO19 I/O PU SPI_flash_IO2_WP
3 GPIO20 I/O F GPIO20
2 GPIO21 I F GPIO21
1 GPIO22 I/O F GPIO22

Table 24: The strapping pin of GPIO14/15 for SPI DATA slave interface

GPIO15/14 2'b01
Pin No. Name I/O PULL I/O Function
9 GPIO05 O F NC
10 GPIO06 I F NC
11 GPIO07 O PU Strapping
14 GPIO08 O F SPI0_S_INT
15 GPIO09 I F NC
16 GPIO10 I F SPI0_S_MOSI
17 GPIO11 I F SPI0_S_CLK
18 GPIO12 O F SPI0_S_MISO
19 GPIO13 I F SPI0_S_CSN
28 GPIO14 I/O F Strapping
29 GPIO15 I/O F Strapping
30 GPIO16 I/O F NC
31 GPIO17 I/O F NC
32 GPIO18 I/O F NC
33 GPIO19 I/O F NC
3 GPIO20 O F GPIO20(WIFI_WAKE_HOST)
2 GPIO21 I F GPIO21(HOST_WAKE_WIFI)
1 GPIO22 O F NC

Shenzhen iComm Semiconductor Co., Ltd. Proprietary and Confidential Page 32 of 39

 SV6256P Datasheet V1.0

Table 25: The strapping pin of GPIO14/15 for SDIO interface

GPIO15/14 2'b10
Pin No. Name I/O PULL I/O Function
9 GPIO05 O F NC
10 GPIO06 I F NC
11 GPIO07 O PU Strapping
14 GPIO08 I/O F SD_D2
15 GPIO09 I F SD_D3
16 GPIO10 I/O F SD_CMD
17 GPIO11 I/O F SD_CLK
18 GPIO12 I/O F SD_D0
19 GPIO13 O F SD_D1
28 GPIO14 I/O F Strapping
29 GPIO15 O F Strapping
30 GPIO16 I/O F NC
31 GPIO17 O F NC
32 GPIO18 I/O F NC
33 GPIO19 I/O F NC
3 GPIO20 I/O F GPIO20(WIFI_WAKE_HOST)
2 GPIO21 I F GPIO21(HOST_WAKE_WIFI)
1 GPIO22 I/O F NC

Table 26: The strapping pin of GPIO14/15 for USB slave interface

GPIO15/14 2'b11
Pin No. Name I/O PULL I/O Function
9 GPIO05 O F NC
10 GPIO06 I F NC
11 GPIO07 O PU Strapping
14 GPIO08 O F NC
15 GPIO09 I F NC
16 GPIO10 I F NC
17 GPIO11 I F NC
18 GPIO12 O F NC
19 GPIO13 I F NC
28 GPIO14 I/O F Strapping
29 GPIO15 I/O F Strapping
30 GPIO16 I/O F NC
31 GPIO17 I/O F NC
32 GPIO18 I/O F NC
33 GPIO19 I/O F NC
3 GPIO20 O F GPIO20(WIFI_WAKE_HOST)
2 GPIO21 I F GPIO21(HOST_WAKE_WIFI)
1 GPIO22 O F NC

Shenzhen iComm Semiconductor Co., Ltd. Proprietary and Confidential Page 33 of 39

 SV6256P Datasheet V1.0

8.2 USER DEFINE I/O FUNCTION SELECTION

After bootstrap, the IOT application also provides a pad multiplex switching from the
bootstrap function to selected I/O function by register signals. There is a condition to leave
bootstrap function. That is switching to GPIO first then switching to select I/O function. The
Table 27 shows the all I/O functions for each PAD.

Table 27: The PAD multiplex for each PAD for IOT application

Pin No. Pin Name Alternate Functions

I/O F GPIO[00]
4 GPIO00
O F PWM0
I/O F GPIO[01]
5 GPIO01
O F PWM1
I/O F GPIO[02]
6 GPIO02
O F PWM2
I/O F GPIO[03]
7 GPIO03 O F PWM3
I F UART0_RXD
I/O F GPIO[04]
8 GPIO04 O F PWM4
O F UART0_TXD
I/O F GPIO[05]
9 GPIO05 O F UART1_RTS
I/O F I2S_BCLK
I/O F GPIO[06]
10 GPIO06 I F UART1_RXD
I F I2S_DI
I/O F GPIO[07]
11 GPIO07 O PU UART1_TXD
O F I2S_DO
I/O F GPIO[08]
14 GPIO08 I/O F I2S_BCLK
O PD SPI_M_CLK
I/O F GPIO[09]
15 GPIO09 I F UART1_CTS
I/O F I2S_LRCLK
I/O F GPIO[10]
I F I2S_DI
16 GPIO10
I PU SPI_M_MISO
I/O PU I2C_SDA
17 GPIO11 I/O F GPIO[11]
I/O F GPIO[12]
O F I2S_DO
18 GPIO12
O PU SPI_M_MOSI
O PU I2C_SCL

Shenzhen iComm Semiconductor Co., Ltd. Proprietary and Confidential Page 34 of 39

 SV6256P Datasheet V1.0

Pin No. Pin Name Alternate Functions

I/O F GPIO[13]
I/O F I2S_LRCLK
19 GPIO13
O PU SPI_M_CS
O PU SPI_PSRAM_CSN
I/O F GPIO[14]
28 GPIO14
I/O PD SPI_flash_IO0_DI
I/O F GPIO[15]
29 GPIO15
O PD SPI_flash_CLK
I/O F GPIO[16]
30 GPIO16
I/O PU SPI_flash_IO3_HD
I/O F GPIO[17]
31 GPIO17
O PU SPI_flash_CSN
I/O F GPIO[18]
32 GPIO18
I/O PD SPI_flash_IO1_DO
I/O F GPIO[19]
33 GPIO19
I/O PU SPI_flash_IO2_WP
I/O F GPIO[20]
3 GPIO20
O F I2S_MCLK
I/O F GPIO[21]
2 GPIO21 O PU I2C_SCL
O F UART0_TXD
I/O F GPIO[22]
1 GPIO22 I/O PU I2C_SDA
I F UART0_RXD
*If using SDIO/SPI DATA/USB application, IO pin function is fixed and defined by driver.

8.3 IOT ADC

Shenzhen iComm Semiconductor Co., Ltd. Proprietary and Confidential Page 35 of 39

 SV6256P Datasheet V1.0

SV6256P IOT application provides an ADC named IOT_ADC for sensing external voltage. It
is an inverse binary thermal code design, the more the voltage, the less the data read.

1V D[9:0] D0

Vsense[3:0] IOTADC PHY DOUT[9:0]

0V Down-sample to D1023
Fs=10MHz
16K

Figure 10: ADC Block diagram

Table 28: IOT ADC Pin Location

Pin No. Pin Name IOT ADC inputs

1 GPIO22 Vsense[0]
2 GPIO21 Vsense[1]
3 GPIO20 Vsense[2]
4 GPIO00 Vsense[3]

Table 29: IOT ADC Specifications

Parameter Description Condition/Notes Min Typ. Max Unit

Nbits Number of bits 10 Bits
Integral nonlinearity Histogram method
INL ±4 LSB
over full scale
Differential Histogram method
DNL ±2 LSB
nonlinearity over full scale
Input Range 0 1 V
Input impedance 100K Ohms
Clock rate Successive
FCLK approximation input 10 MHz
clock rate
Input capacitance 2 pF
Number of
4
channels
Sampling rate of
Fsample 16/8 KSPS
each ADC
Maximum input
F_input_max 7.2/3.6 kHZ
signal frequency
Active supply current Average for ADC
I_active 1 mA
during conversion
Power-down supply
I_PD current for core Disable ADC 1 uA
supply
Absolute offset
±40 mV
error
Gain error ±2.5 %

Shenzhen iComm Semiconductor Co., Ltd. Proprietary and Confidential Page 36 of 39

 SV6256P Datasheet V1.0

9 PACKAGE INFORMATION
6 x 6 mm (body size), 0.4mm pitch QFN-48

Marking format (top view)

SV6256P

XXXXXXX
XXXXX
Pin #48
Indicates Pin #1(Laser Marked)

Indicates Pin #1(Laser Marked)

Indicates Pin #1(Laser Marked)

Shenzhen iComm Semiconductor Co., Ltd. Proprietary and Confidential Page 37 of 39

 SV6256P Datasheet V1.0

Figure 11: QFN 6 x 6 mm Package Dimensions

Shenzhen iComm Semiconductor Co., Ltd. Proprietary and Confidential Page 38 of 39

 SV6256P Datasheet V1.0

10 Part Number

The table below provides the ordering information of the SV6256P.

Table 30: SV6256P Part Number

Part Number Band Operating Temp(°C) Package

SV6256P Dual Band -40 to +85 QFN 6x6

Shenzhen iComm Semiconductor Co., Ltd. Proprietary and Confidential Page 39 of 39