ECEN620: Network Theory
Broadband Circuit Design
Fall 2022
Lecture 1: Introduction
Sam Palermo
Analog & Mixed-Signal Center
Texas A&M University
Why Broadband Circuits?
• Broadband circuits are used in many wireline and
wireless communication systems
• Trends in processor design and the growing
demand for digital connectivity are pushing data
rates and bandwidth requirements in these
systems
• In this class, we will study key clocking and
amplifier circuits that enable these
communication systems to scale in performance
2
Class Topics
• Broadband circuit design methodologies
• Clocking circuits
• Phase-Locked Loops (PLLs)
• Clock-and-Data Recovery systems (CDRs)
• Broadband amplifiers
• Transimpedance, limiting, and variable-gain amplifers
3
Analog Circuit Sequence
Pre/Co-Requisite
326
474/704
Optical Interconnects
Circuits & Systems
689 625 720
4
Administrative
• Instructor
• Sam Palermo
• 315E WERC Bldg., 979-845-4114, spalermo@tamu.edu
• Office hours: M 2:30PM-4:00PM & R 4:00PM-5:30PM
• In-person and online via Zoom
• Lectures
• TR 11:10AM-12:15PM
• Videos posted on Canvas
• Class web pages
• https://people.engr.tamu.edu/spalermo/ecen620.html
• Will use Canvas for turning in assignments
5
Class Material
• Textbook: Class Notes and Technical Papers
• Key References
• Phaselock Techniques, F. Gardner, John Wiley & Sons, 2005.
• Design of Integrated Circuits for Optical Communications, B.
Razavi, McGraw-Hill, 2003.
• Phase-Locked Loops: Design, Simulation, & Applications, R. Best,
McGraw-Hill, 1997.
• Broadband Circuits for Optical Fiber Communication, E. Sackinger,
Wiley, 2005.
• Design of Analog CMOS Integrated Circuits, B. Razavi, McGraw-
Hill, 2001.
• Class notes will be posted online
6
Grading
• Exams (50%)
• Two midterm exams (25% each)
• Homework (25%)
• Collaboration is allowed, but independent simulations and write-ups
• Need to setup CADENCE simulation environment
• Turn in via Canvas
• No late homework will be graded
• Final Project (25%)
• Groups of 1-3 students
• Report and PowerPoint presentation required
• Turn in report and presentation files via Canvas
7
Prerequisites
• Circuits
• ECEN474/704 or approval of instructor
• Basic knowledge of CMOS gates, flops, etc…
• Circuit simulation experience (HSPICE, Spectre)
• Systems
• Basic knowledge of s- and z-transforms
• MATLAB experience
8
Simulation Tools
• Matlab
• Cadence
• 90nm CMOS device models
• Can use other technology models if they are a
90nm or more advanced CMOS node
• Other tools, schematic, layout, etc… are
optional
9
Preliminary Schedule
• Dates may change with reasonable notice
10
High-Speed Electrical Link System
11
10GHz PLL Example
PLL Performance TxPLL RxPLL [Meghelli (IBM) ISSCC 2006]
Min freq (GHz) 8.98 8.96
Max freq (GHz) 13.54 13.47 Measured Jitter Transfer Function
5
Mean freq (GHz) 11.26 11.22
Lock range (GHz) 4.56 4.52
0 (2MHz,-3dB)
G a in (d B )
-5
+/-20.2% +/-20.1%
-10
Fine tune hold range 5.8% 5.8%
-15
-20 0.1
Quarter rate clock phase noise -117.8 -117.7 1 10
@ 10MHz offset (dBc/Hz) Frequency (MHz)
Jitter, 1MHz-100MHz (ps rms) 1.5 1.4
Jitter, fc/1667-100MHz (ps rms) 0.64 0.64
100mW Power consumption
(with clock distribution)
12
High-Speed Logic Example:
Divide-by-2 with CML FF
[Razavi]
• High-speed logic blocks are required in numerous high-
speed circuits, such as PLLs, CDRs, and equalizers
• Relative to CMOS logic, current-mode logic (CML) circuits
can achieve higher bandwidth due to lower self-loading
• Additional bandwidth extension can be achieved with the
addition of passives (inductors) and feedback
13
Detailed Serial-Link Receiver Architecture
From on-chip PLL (5GHz)
C2-I C2-Q VDDIO=1V
Vcm I-Clock control 2 1
Phase rotator D0
CDR
(2.5Gb/s)
50Ω 2 1
PI PI logic D1
Q-Clock control 8 2 1
D2
In_P I Q
2 1
In_N T-Coil Compensation D3
Phase Edge
2:8 8:16
Network detector
(10Gb/s)
DMUX DMUX Data
Amp
Data Edge
DFE Amp Clock
VGA Block Tap weights DFE
logic
ESD
CML Key Features:
VDDA=1.2V VDD=1.0V CMOS logic
- Half-rate design
- 5-tap continuously adaptive DFE
- Variable gain amplifier
- Digital CDR
- ESD protection (HBM & CDM)
- 130mW (with DFE and CDR logic)
[Meghelli (IBM) ISSCC 2006]
14
CDR Loop
Data Clock
I Rotator
D D Early Control
Z-1 D/A PI
From on-chip PLL
Data Digital
DMUX XORs Q Rotator
Filter C2-I
E E Late Control
Z-1 D/A PI
C2-Q
Edge Clock
Jitter Tolerance
Receiver Jitter tolerance curve ( BER<1e-9)
1.4
Key Features: 1.2
1
- Fully digital loop
Sine Jitter (UI pp)
Tracking bandwidth ~9MHz
0.8
- Can handle up to +/- 4000ppm
0.6
frequency offset
0.4
- Independent I,Q control
0.2
0
1.00E+05 1.00E+06 1.00E+07 1.00E+08 1.00E+09
Modulation Frequency
[Meghelli (IBM) ISSCC 2006]
15
Variable-Gain Amplifier (VGA) Example
Key Features:
• Dual Diff Amps
• Half/Full Amplitude
• Switched R Degen
• 7 Bit Thermometer
• Multi-bit Slewrate
• Glitchless Operation
• Continuous Adjustment
• Optimized with GA
[Sorna (IBM) ISSCC 2005]
Optical Receiver Front-End
[Razavi]
• Transimpedance amplifiers (TIAs) convert an input
current signal into an output voltage with a
transimpedance gain
• Limiting amplifier amplifies the TIA output to a
reliable level to achieve a given BER with a certain
decision element (comparator)
17
Next Time
• Linear circuit analysis review
18
