DEPARTMENT OF ELECTRONICS KMBB COLLEGE OF ENGINEERING & TECHNOLOGY.

IMPORTANT QUESTIONS & PORTIONS FOR 4th SEMESTER DEC SHORT QUESTIONS 1. State De-Morgan's theorem. 2. What is lithography process. 3. Define excitation table. Write excitation table for JK flip flop. 4. How many 32K8 RAM chips are needed to provide a memory capacity of 256K Bytes . 5. Define implicant and prime implicant in a K-map. 6. Find the 1's complement of 100010.01. 7. find the 2's complement representation of -30. 8. find the 1's complement representation of -35. 9. add 45 & 23 by 9's complement method. 10. Distinguish between digital and discrete signal. 11. What are the advantages of digital electronics. 12. VHDL stands for what. 13. Define entity in VHDL. 14. Give some examples of valid identifiers in VHDL. 15. Distinguish between Very Log and VHDL. 16. What are the maximum positive and negative numbers that can be represented by 4-bit binary number using 1. 1's complement 2. 2's copmlement. 17. Distinguish between Decoder, Encoder and Multiplexer in digital circuits. 18. What do you mean by Sequential Logic Circuit ? Hence distinguish between synchronous and asynchronous sequential logic circuit. 19. How FAN OUT & FAN INof a gate is specified ? 20. Realize an INVERTER and OR gate using NAND gate. 21. Add -23 & +56 using 2's complement method. 22. Use K-map to reduce the expression F= A+BC'+CD. 23. Convert 23AC to octal,binary & decimal. 24. What is the basic difference between DRAM & SRAM . 25. What is race around condition in flip flops. 26. Define excitation table of a FF. 27. What do u mean by universal shift register. 28. Write the VHDL code for HALF ADDER. 29. 30. LONG QUESTIONS 1. K-map minimization problems such as Minimize F=m(2,3,5,6,7,12,13) F= m(2,3,5,6,7,12,13)+d(0,1,4,14) F= m(0,2,3,7,11,13,14,15) F=m(1,3,4,5,9,11,12,13,14,15) F=M(0,4,6,7,8,12,13,14,15) F=M(0,1,2,3,8,10,13) 2.MINIMIZE the following boolean expression using boolean algebra 1. F=A'BC'+AB'C'+AB'C+ABC'+ABC 2. F=XY+X'+Z'+XY'Z(XY+Z) 3. F=(AB+C)(C'+D)(C'+D+E)

3. SOP & POS CONVERSION. eg: convert F= ABC'+AB'C+A'B'C' into POS F= A+ BC +AC to canonical SOP & POS. F= (A+B+C)(A'+B'+C)(A'+B+C) to SOP. 4. Simplify the following using K-map. i. A'B+ABD+AB'CD'+BC ii. BC+AC'+AB+BCD iii. A'BCD'+ABCD'+ABC'D'+A'B'C'D'+ABC'D+A'B'C'D+AB'CD'+ABCD 5. Implement F=AB+C'+DE using NAND & NOR gates only. 6. What do u mean by logic array? Explain its application.Draw the general structure of an AND-OR PLA. 7. What do u mean by magnitude comparator. Explain a 2-bit magnitude comparator. 8. What is a decoder ?reliaze a 4:16 decoder using 3:8 de coder. 9. Implement FA using decoder & OR gates. 10. Implement FA using HA. 11. DISCUSS multiplexer & implement OR ,XOR gates using MUX. 12. Implement 8:1 MUX using two 4:1 MUX. 13. IMPLEMENT the given function using 8:1 mux and 4:1 mux. F= m(1,3,4,11,12,13,14,15) 14. IMPLEMENT the given function using 8:1 mux and 4:1 mux. F= m(0,1,3,4,8,9,15) 15. IMPLEMENT the given function using 8:1 mux and 4:1 mux. F= M (1,3,5,6,7,12,13,14,15) 16. EXPLAIN a multiplier. Discuss a 2 bit multiplier. 17. Explain SR LATCH with function/truth table. why its name so given?what is its drawback. 18. Explain JK Flip flop. 19. What is a master slave flip flop ? Explain its operation. 20. Discuss race around condition in flip flops & how it can be avoided. 21. Design a 3-bit/MOD-8 up/down synchronous counter with proper logic diagram. 22. Design a 3-bit/MOD-8 up/down Asynchronous counter with proper logic diagram. 23. DESIGN a MOD -16/4 BIT Ripple/asynchronous counter with proper timing diagram. 24. DESIGN a MOD -9 Ripple/asynchronous counter with proper timing diagram. 25. Design a mod-6 synchronous counter using JK FF. 26. Draw the state table for the given state diagram.

27.design a sequential circut using D/JK/T FF for the following state diagram.

28. find the state table and state equation for the given state diagram.

30.draw the state table & state diagram for the sequential circuit whose state equation is given by the following equation.

31.what is lithography and pattering? Explain with a suitable example. 32.Explain CMOS AS inverter. Draw the layout of inverter. 33. explain CMOS as NOR gate. 34. Explain CMOS as NAND gate. 35. Implement F= AB+D using CMOS. 36. What do u mean by layout?Draw the layout of NOR/NAND gate. 37. Discuss design rule in VLSI. 38. 39. 40. 41. 42. Write a VHDL code for full adder. Write dtaflow model for 3:8 decoder. Write the behavioral model code for D-FF. write the VHDL programe for functional description ofJK FF. write the VHDL CODE FOR a synchronous counter.

43. How many 328 RAM chips are needed to provide a memory capacity of 256K Bytes? How many address lines must be used to access 256K bytes? How many of these lines are connected to the adress inputs of all chips? How many lines must be decoded for the chip select input.specify the size of the decoder? ( Semester 2009) 44. how many 328 ram chips are needed to provide a memory capacity of 512 Bytes? how many lines of the adress must be vused to access 512K Bytes? How many of these lines are connected to adress inputs of all chips? How many of these adress lines must be

decoded for the chip select inputs?specify the size of the decoder? (Semester 2010)