Function and Tasks

— In some situations same functionality is required at many places in

a program.

— These commonly used codes (functionality) should be abstracted

into routines and they should be invoked instead of repeating
code.

— Verilog provides functions and tasks to break up large behavior

designs into smaller codes.

— Task or functions can only contain sequential statements.

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 Functions

— Functions are declared with keyword function and endfunction.

— Functions are used to return a single value. They cannot have

output and inout ports.

— A function must have at least one input argument. It may contain

more than one input.

— Delay, Event and Timing Control statements are not allowed inside
function.

— Functions always executes in zero simulation time.

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 Functions

— When a function is declared, a register with the same name is

implicitly(by default) declared in verilog.

— A value is returned back by assigning appropriate value to the

implicit register (function name).

— The function is invoked by specifying function name followed by

input arguments.

— A function can be called from a function, task, port declaration,

continuous assignment and procedural assignment.

— A function can invoke other functions but it cannot invoke other

tasks.
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 Functions

Declaration : Style1
function [return_type] function_name;
//input declarations;
//local registers declaration;
begin //begin-end if multiple statements
sequential statements;
end
endfunction
— Return type and all inputs are 1-bit reg by default.
— Return variable name is same as function_name.
— Only Blocking sequential statements are allowed.

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 Functions

Declaration : Style2
function [return_type] function_name (input_declarations);
//local registers declaration;
begin
sequential statements;
end
endfunction
Usage:
assign net_name = function_name (input_list);
reg_name1 = function_name (input_list);
reg_name2 <= function_name (input_list);

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 Functions-Examples

Problem Statement : Write a function which accepts 8 bit input din and
returns parity. Use for loop instead of reduction operator.

function parity (input [7:0] din); module parity_cal (din, dout);

integer i; input [7:0] din;
reg temp; output dout;
begin
temp=0; //function declaration
for (i=0; i<=7; i= i + 1)
temp= temp ^ din[i]; assign dout=parity(din);
parity=temp;
end endmodule
endfunction
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 Functions-Examples

Problem Statement : Write a function to return maximum out of three

integers a, b and c.

function integer maximum (input signed [31:0] a, b, c) ;

begin
module max (a, b, c, result) ;
if (a > b && a> c)
input signed [31:0] a, b, c;
maximum=a;
output integer result;
else if (b>c)
//function declaration
maximum=b;
else always @ (*)
maximum=c; result=maximum(a, b, c);
end
endfunction endmodule
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 Automatic function

— A function call allocates static memory to variables used in its

operation.

— If the same function is called again, same set of allocated

memories are used for its operation.

— In case of recursive or re-entrant functions (function called within a

function) using static memories may give wrong result.

— automatic keyword is added after function keyword to target a

recursive function.

— An automatic function allocates a new set of memory to the

variables every time a function is called.
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 Automatic function

Problem Statement : Write a function which accepts positive integer and

returns factorial of that number.

function [63:0] fact (input [31:0] din); module fact_test (din, dout);
begin input [31:0] din;
if (din<=1) output reg [63:0] dout;
fact=1;
else //function declaration
fact= fact(din -1) * din ; always @ (*)
end dout=fact(din);
endfunction
endmodule
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 Automatic functions

Assume that user gave 4 as an input to the fact_test function. What will
be the value of the dout.

Expected: 24 Outcome: 1

Memory 1 Memory 1 Memory 1 Memory 1

Function
4 3 2 1
Input
Function
fact (3) *4 fact (2) *3 fact (1) *2 1
Return

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 Automatic functions

To solve this issue we will use add automatic keyword because we

intend to design a recursive function.

function automatic [63:0] fact (input [31:0] din);

begin
if (din<=1)
fact=1;
else
fact= fact(din -1) * din ;
end
endfunction

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 Automatic functions

Since automatic keyword is added to the function, for every function call
a new set of memory is created and the result is returned to location
where the function call occurs.

Memory 1 Memory 2 Memory 3 Memory 4

Function
4 3 2 1
Input
Function
4 * fact (3) 3* fact (2) 2* fact (1) 1
Return

4*3*2* 1 3*2* 1 2* 1 1

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 Signed Function

A signed function is one which returns signed values. This can be

done by adding signed keyword before the function return size.
Problem Statement : Write a function which accepts 16-bit unsigned
number and returns 16-bit signed number.
module sample (a, b, c ) ;
input [15:0] a;
function signed [15:0] sign (input [15:0] a);
output [15:0] b, c;
begin
//function declaration
sign=a;
end assign b=(sign(a))>>>3;
endfunction assign c=a>>>3;

endmodule
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 Functions

Functions have access to variables declared outside its scope.

module test (input [31:0] din, output integer b) ;

integer c=10, d=4;
function [31:0] adder (input [31:0] a);
begin d=7; adder= a + c; end
endfunction

always @ (*)
b=adder(din);

endmodule
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 Constant function

— Constant function are functions which are used during elaboration

time.

— A constant function can not modify global variables.

— A constant function can only call a constant function.

— Input argument for a constant function should either be a

parameter or a constant.

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 Constant function

function [31: 0] log2 (input [31: 0] data);

reg [31: 0] temp;
begin module encoder (en, din, dout);
temp=0;
while (data>1) parameter in_size=8;
begin input [in_size-1 : 0] din;
data=data>>1; input en;
temp=temp + 1; output [(log2(in_size)) -1: 0] dout;
end
//function declaration
log2=temp;
//module functionality
end
endfunction endmodule

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 Tasks

— Tasks are declared with keyword task and endtask.

— Tasks can pass multiple values through output and inout ports.

— A task may have zero or more arguments of type input, output or

inout.

— Delay, Event and Timing Control statements are allowed inside

tasks.

— Tasks may execute in non-zero simulation time.

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 Tasks

— A task can be called from a task and procedural assignment.

— A task can invoke other tasks and functions.

— A task is invoked by specifying task name followed by input,

output or inout arguments.

— The argument should be specified in the same order they are

declared.

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 Tasks

Declaration : Style1
task task_name;
//input, output or inout declarations;
//local registers declaration;
begin //begin-end if multiple statements
[timing_control] sequential statements;
end
endtask

— By default the size of ports and local registers is 1-bit reg.

— Both Blocking and Non-Blocking sequential statements are
allowed.

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 Tasks

Declaration : Style2
task task_name (input, output or inout declarations);
// local registers declaration;
begin
[timing_control] sequential statements;
end
endtask
Usage:
task_name (input, output or inout list);

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 Tasks-Examples

Problem Statement : Write a task which accepts 8-bit input a, b and

provides 8-bit outputs ab_and, ab_xor, ab_nand

task task_exam1; module task_test (a, b, c, d, e);

input [7:0] a, b; input [7:0] a, b;
output [7:0] ab_and, ab_xor, output reg [7:0] c, d, e;
ab_nand;
begin //Task declaration
ab_and= a & b;
ab_xor= a ^ b; always @ (*)
ab_nand= ~(a & b); task_exam1(a, b, c, d, e);
end
endmodule
endtask
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 Tasks-Examples

Example: inout task module task_inout;

integer x=0;
task increment; //Task declaration
inout integer a;
a=a + 1; initial
endtask begin
increment(x);
$display(“x=%d”, x );
Result:
x=6;
x=1
increment(x);
x=7
$display(“x=%d”, x );
end
endmodule
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 Tasks-Examples

Example: task with no argument module task_test;

//Task declaration
task count;
initial
integer total;
begin
total=total + 1;
count.total=3;
endtask
count;
count;
Result:
count;
6
$display(count.total );
end
endmodule

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 Tasks-Examples

Example: Multiple Calls module task_test;

integer a=4, b=8;
task increment;
inout integer x ; //Task declaration
#10 x=x + 1; initial
endtask increment(a);
initial
Result: #2 increment(b);
0 a=4 b=8
10 a=9 b=8 initial
12 a=9 b=10 $monitor($time, “a= %d, b=%d”, a , b);
endmodule
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 Automatic Tasks

Example: Multiple Calls module task_test;

integer a=4, b=8;
task automatic increment;
inout integer x ; //Task declaration
#10 x=x + 1; initial
endtask increment(a);
initial
Result: #2 increment(b);
0 a=4 b=8
10 a=5 b=8 initial
12 a=5 b=9 $monitor($time, “a= %d, b=%d”, a , b);
endmodule
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 Functions-Tasks Difference

Functions Tasks

Functions are used to return single value Tasks can be provide multiple values

Function musts have at least one input Tasks may have zero or more arguments
argument of type input, output or inout

Timing control statements are not allowed Timing control statements are allowed

Always executes in zero simulation time May not execute in zero simulation time
Both Blocking and Non Blocking
Only Blocking statements are allowed
statements are allowed

Functions can invoke other functions only Tasks can invoke other functions and tasks

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 Parameters

— Parameters are used to declare constants in Verilog.

— These constants can be overridden during compilation time.

— defparam keyword is used to override a parameter.

— Parameter can also be overridden using #() after the module

name in a module instance.

— If both defparam and #() are used, the value of defparam will
be used for overriding.

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 Parameter Declaration

module custom_adder (a, b, cin, sum, carry);

parameter size=0;
input [size-1: 0] a, b;
input cin;
output [size-1: 0] sum;
output carry;

assign {carry, sum}= a + b + cin;

endmodule

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 Parameter - ANSI C Style

module custom_and
#(parameter size=0)
(input [size-1: 0] a, b, output [size-1: 0] op_and);

assign op_and= a & b;

endmodule

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 Overriding Syntax

defparam instance_label.parameter_name1=value1;
defparam instance_label.parameter_name2=value2;

module_name #(value1, value2) label (port mapping);

module_name #(.parameter_name1(value1),
.parameter_name1(value2))
label (port mapping);

Mixture of defparam and #() can be used in a single code.

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 Overriding Parameter

module adder_test;

defparam m0.size=4;
reg cin; reg [m0.size-1: 0] a, b;
wire [m0.size-1: 0] sum; wire carry;

custom_adder m0 (a, b, cin, sum, carry);

always
begin
a=$random; b=$random; c=$random; #10;
end
endmodule
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 Overriding Parameter

module and_test ;

reg [m0.size – 1 : 0] a, b;
wire [m0.size -1 : 0] op_and;
custom_and #(6) m0 (a, b, op_and);

always
begin
a=$random; b=$random; #10;
end

endmodule

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