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Data Sheet
PRELIMINARY
April 2008

AR6002 ROCmTM Single-Chip MAC/BB/Radio for 2.4/5 GHz

Embedded WLAN Applications
General Description are available in Wafer Level Chip Scale Packages
The Atheros AR6002 is the 2nd generation of the (WLCSP) or Ball Grid Arrays (BGA) packaging .
WLAN ROCm family. Building on the advanced AR6002 Features
performance and features of the AR6001 family,
■ All-CMOS IEEE 802.11a/b/g or 802.11b/g
the compact size and low power consumption of single-chip client
this single chip design make it an ideal vehicle
■ Integrated PA, LNA and RF switch
for adding WLAN to hand-held and other
minimizing external component count
battery-powered consumer electronic devices.
Both IEEE 802.11g (2.4 GHz) and 802.11a (5 GHz) ■ Data rates of 1–54 Mbps for 802.11g, 6-54
standards are supported by the AR6002 family. Mbps for 802.11a
■ Advanced power management to minimize
The AR6002 supports both SDIO 1.1 and GSPI
host interfaces.
a
standby, sleep and active power
i l
The AR6002 family includes a highly integrated,
n t
■ Host interface support for SDIO and GSPI
front-end module ((Power Amplifier, Low-Noise
Amplifier and RF switch), enabling low-cost
id e
■ Security support for WPS, WPA2, WPA,
WAPI and protected management frames
designs with minimal external components. The
n f■ Support for 2.4 and 5 GHz operation in all
RF performance, data throughput, and power
consumption further improve upon the
Co available bands in all regulatory domains
■ Full 802.11e QoS support including WMM
performance of the AR6001 family. Advanced
s
ero
and U-APSD
architecture and protocol techniques save power
during sleep, stand-by and active states. ■ Standard 2, 3 and 4 wire Bluetooth
Fast antenna diversity is also supported, t h coexistence handshake support
allowing optimal antenna selection on a per-
:A ■ IEEE 1149.1, JTAG, test access port and

ary
packet basis. The AR6002 family supports 2, 3 boundary scan
and 4 wire Bluetooth coexistence protocols with ■ 18 fully-programmable GPIO pins

in
advanced algorithms for predicting channel
■ 16550-compliant UART

l m
usage by the co-located Bluetooth transceiver.
i
The AR6002 family provides multiple peripheral ■ SPI or I2C for EEPROM support

Pr e
interfaces including UART, SPI, I2C and 18 GPIO
pins. All internal clocks are generated from a
single external crystal/oscillator. A variety of
■ Internally generated low-frequency oscillator
for low-power sleep

reference clocks are supported which include ■ Available in 7 x 7 mm BGA package with 0.5
19.2, 24, 26, 38.4, 40 and 52 MHz. AR6002 chips mm pitch or WLCSP package with 0.4 mm
pitch

SDIO PA
HOST Mailbox A 802.11a/g 802.11a/g 802.11a/g
SDIO or GSPI DMA H MAC BB Radio LNA1

GSPI B

I LNA2 LNA2 Input

N
Console UART T Memory i-port
E
Controller
R Xtensa
N d-port
EEPROM SPI/I2C Bridge A RAM CPU
L
ROM
LED GPIO B
U 32 KHz OSC
S LF CLK
Power, Clock (optional)
Test, ICE JTAG AR6002 Management REF CLK OSC/XTAL

AR6002 System Block Diagram

© 2000-2008 by Atheros Communications, Inc. All rights reserved. Atheros™, ROCm™, 5-UP™, Driving the Wireless Future™, Atheros Driven™, Atheros
Turbo Mode™, and the Air is Cleaner at 5-GHz™ are trademarks of Atheros Communications, Inc. The Atheros logo is a registered trademark of
Atheros Communications, Inc. All other trademarks are the property of their respective holders.
Subject to change without notice.
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2 • AR6002 MAC/BB/Radio for Embedded WLAN Applications Atheros Communications, Inc.

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Table of Contents
1 Functional Description ................. 5 3.2 Transmitter (Tx) Block ....................... 22
1.1 Overview ................................................... 5 3.2.1 Synthesizer (SYNTH) Block ... 22
1.2 XTENSA CPU ....................................... 5 3.3 Bias/Control (BIAS) Block ................ 23
1.3 Virtual Memory Controller (VMC) .... 5 3.4 Baseband Block ................................... 23
1.4 AHB and APB Blocks ........................... 5 3.4.1 SM Block ................................... 24
1.5 Master SI/SPI Control ......................... 5 3.4.2 AGC Block ................................... 24
3.4.3 TIM Block .................................... 24
1.6 GPIO ....................................................... 6
3.4.4 FFT and VIT Blocks .................... 24
1.7 LEDs ....................................................... 6
3.4.5 BBB Block ..................................... 25
1.8 MBOX ..................................................... 6
1.9 UART ..................................................... 6 4 Electrical Characteristics ............27
1.10 Reset Control ......................................... 6 4.1 Absolute Maximum Ratings ................ 27
1.10.1 CPU Reset ................................... 7 4.2 Recommended Operating
ia l
1.11 Reset Sequence ...................................... 7
n t
Conditions ........................................... 28

1.12 Power Management ............................. 7

4.3
e
DC Electrical Characteristics ............ 29
id
1.12.1 Hardware Power States ............ 7 4.4
n f Radio Receiver Characteristics ......... 32
1.12.2 Sleep State Management ............ 10
Co
4.5
4.6
Radio Transmitter Characteristics ... 35
AR6002 Synthesizer Characteristics 36
1.13 System Clocking (RTC Block) ........... 10
s
ero
1.13.1 High Speed Clocking .............. 10 4.7 Typical Power Consumption
1.13.2 Low-Speed Clocking .................. 10 Performance ........................................ 38

t h
1.13.3 Interface Clock ............................ 11 4.7.1 Measurement Conditions for Low

ry :A
1.13.4 Antenna Switching ..................... 11
1.14 MAC/BB/RF Block ............................ 12
Power State ............................... 38
4.7.2 Measurement Conditions for

in a
1.14.1 MAC Block ............................... 12
Continuous Receive Using
LNA1 ............................................ 39

l m
1.15 Clock Distribution, JTAG, and
i
Testing .................................................. 13
4.7.3 Measurement Conditions for

Pr e
Continuous Receive Using
1.16 CPU Subsystem .................................. 14 LNA2 ............................................ 40
1.17 CPU Power Consumption ................. 14 4.7.4 Measurement Conditions for
Continuous Transmit Using xPA 41
1.18 Memory ................................................ 14
4.7.5 Measurement Conditions for
1.19 Interrupts ............................................. 15 Continuous Transmit
Without xPA ................................ 42
2 Host Interfaces ............................. 17
2.1 SDIO and GSPI Interfaces ..................... 17 5 AC Specifications ........................43
2.2 Host Interface Address Map ............. 17 5.1 Optional External 32 KHz Input Clock
Timing ..................................................... 43
2.3 Mailboxes ............................................. 19
2.3.2 Error Conditions ......................... 19 5.2 External 19.2/24/26/38.4/40/52 MHz
Reference Input Clock Timing ......... 43
2.4 Interrupts ............................................. 19
5.3 SDIO/GSPI Interface Timing ........... 44
2.4.1 AR6002 to Host ........................ 19
2.4.2 Host to AR6002 ........................... 19
6 Pin Descriptions ...........................47
3 Radio .............................................. 21
7 Package Dimensions ...................53
3.1 Receiver (Rx) Block ................................ 21

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8 Ordering Information ................. 55

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1. Functional Description
1.1 Overview Any one of these interfaces can request access
The AR6002 is a single chip 802.11 (a, b, g) to the ROM or RAM modules within the VMC.
device based on the cutting edge technology. The VMC contains arbiters to serve these three
The AR6002 has large internal RAM which interfaces on a first-come-first-serve basis.
precludes the need for external memory. It
contains a dual-band radio, a MAC, a CPU, 1.4 AHB and APB Blocks
power management functions, and other The AHB block acts as an arbiter. It has AHB
functions. Its internal logic and boot code are interfaces from three Masters:
designed to detect the presence of an external ■ MAC,
host and to automatically begin
communicating with that host. The supported ■ MBOX (from the Host), and
Host interfaces are SDIO and GSPI (Generic ■ CPU.
SPI). See the AR6002 block diagram on page 1.
See below for more on the MBOX and MAC.
The XTENSA CPU communicates directly with Depending upon the address, the AHB data
the RAM and ROM modules within the device
without any caching. Boot code in the ROM
i l
request can go into one of the two slaves: APB
a
block or the VMC. Data requests to the VMC
first detects the presence of an external host. It
then begins communicating with this host. The t
are generally high-speed memory requests,
n
host then downloads additional code into the
id e
while requests to the APB block are primarily
meant for register access.
RAM which the XTENSA CPU can later
execute.
n f
The APB block acts as a decoder. It is meant
The AR6002 supports a total of 18 GPIOs. Some
Co
only for access to programmable registers
within the AR6002’s main blocks. Depending
of these GPIOs are shared with the UART
interface as well as the SI block. The SI block
ro s upon the address, the APB request can go to
one of the eight places listed below:

h e
supports both I2C as well as SPI interfaces and
■ RF Interface (APB serial block)
serial devices such as EEPROMs or
At
can be used to communicate with external
■ VMC
:
ary
programmable oscillators. ■ SI/SPI
■ MBOX
1.2 XTENSA CPU
in ■ GPIO

l m
At the heart of the chip is the XTENSA CPU.
i
This CPU has four interfaces: ■ UART

Pr e
■ The Code RAM/ROM interface (iBus), ■ Real Time Clock (RTC), or
going to the Virtual Memory Controller
(VMC). ■ MAC/BB

■ The Data RAM Interface (dBus), going to The AR6002 RF module has a long-shift
the VMC interface which allows the CPU to directly
control its registers via APB access. Hence the
■ The AHB interface which has been APB block converts 32-bit APB reads and
translated from the CPU's internal XTENSA writes by the CPU into serial transfers to the RF
Local Memory Interface (XLMI) bus. This is module.
used mainly for register accesses.
■ JTAG interface for debugging 1.5 Master SI/SPI Control
The AR6002 has a master serial interface (SI)
1.3 Virtual Memory Controller (VMC) that can operate in two, three, or four-wire bus
The VMC contains 80 kBytes of ROM and 184 configurations to control EEPROMs or other
kBytes of RAM. It has three interfaces: I2C/SPI devices. Multiple I2C devices with
different device addresses are supported by
■ iBus,
sharing the two-wire bus. Multiple SPI devices
■ dBus, and are supported by sharing the clock and data
■ AHB interface.
signals and using separate software-controlled
GPIO pins as chip selects.

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1.8 MBOX
An SI transaction consists of two phases: a data The MBOX is a service module to handle one of
transmit phase of 0-8 bytes followed by a data two possible external hosts: SDIO or GSPI. The
receive phase of 0-8 bytes. The flexible SI AR6002 can handle only one of these hosts at
programming interface allows software to any given time. The type of host the AR6002
support various address and command uses depends upon the polarity of some
configurations in I2C/SPI devices. In addition, package pins upon system power-up. The
software may operate the SI in either polling or MBOX has two interfaces: an APB interface for
interrupt mode. access to the MBOX registers and an AHB
interface which is used by the external host to
1.6 GPIO access the VMC memory or other registers
within the AR6002.
The AR6002 has 17 GPIO pins with direct 1.9 UART
software access. Many are multiplexed with
other functions such as UART, SI, and The AR6002 includes a high-speed Universal
Bluetooth coexistence (see Section 6 for details). Asynchronous Receiver/Transmitter (UART)
interface that is fully compatible with the 16550
Each GPIO supports the following UART industry standard. Unlike standard
configurations via software programming:
a l
RS232 modules, AR6002's UART interface
supports the transfer of multiple bytes of data
i
■ Input available for sampling by a software
n t
between the CPU and the UART. This reduces
the bandwidth requirements on AR6002's CPU
register

id e
when it communicates with the UART. The
■ Input triggering an edge or level CPU
interrupt f
UART supports:
n
■ Input triggering a level chip wakeup
Co
■ Polling and interrupt modes
■ Full duplex buffer system with 16-byte
interrupt
■ Open-drain or push-pull output driver
ro s
Tx/Rx FIFOs
■ 5-, 6-, 7-, or 8-bit characters

h e■ 1-, 1 1/2-, or 2-stop bit generation

■ Output source from a software register or
t ■ Odd, even, or no parity.

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the Sigma Delta Pulse-width Modulation
(PWM) DAC In addition, different sets of

ary
GPIO pins have internal pull-up/down ■ Data rates of:
options that are software configurable.
in
The AR6002 has one Sigma Delta PWM DAC
–
–
57600 bps
38400 bps

l im
shared by all of the GPIO pins. It allows the – 28800 bps

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GPIO pins to drive intermediate output voltage
levels for functions such as LED dimming. The
DAC has a period of 256 samples with a
–
–
–
19200 bps
9600 bps
4800 bps
configurable number of clock cycles per – 2400 bps
sample. By programming a register, software
can control the duty cycle of the Sigma Delta 1.10 Reset Control
PWM DAC, approximating an intermediate The AR6002 CHIP_PWD_L or the SYS_RST_L
voltage level.
pins can be used to completely reset the entire
chip. After these signals have been de-asserted,
1.7 LEDs The AR6002 waits for the host power enable
The AR6002 can drive LEDs using GPIO pins. signal to be asserted by the external host
An external NPN transistor can provide higher processor. Until this signal is asserted, the
power drive. Note that the LED connects to the MAC, BB, and SOC blocks are powered off and
battery voltage. For multiple LED groups, all modules except the host interface are held in
multiple GPIOs can be assigned. The GPIO reset.
Sigma Delta PWM DAC can provide a
continuous dimmer function. Once the HOST_PWR_EN signal has been
asserted, then the AR6002 turns on its crystal
and later on its PLL. After all clocks are stable
and running, the resets to all blocks are

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automatically de-asserted. The only resets that (Use of SYS_RST_L is optional but must be
stay asserted are given below: de-asserted if asserted.) See the Host
Interface chapter for a table listing interface
■ Warm and cold resets to the MAC type options.
■ Warm reset to the radio (The cold reset gets 3. For SDIO and GSPI interface modes, the
automatically de-asserted) AR6002 enters the HOST_OFF state. The
The above resets are deasserted by software. host then reads interface registers to
All AR6002 reset control logic resides in the determine the type of function that the
RTC block to ensure stable reset generation. AR6002 supports.
4. When the host is ready to use the WLAN, it
1.10.1 CPU Reset enables the AR6002 by writing to the
The CPU Reset is a bit different from the other function enable bit which sets the
resets mentioned above. There are four HOST_PWR_EN signal.
scenarios where the CPU Reset can be asserted:
5. The AR6002 enters the WAKEUP state then
1. It can be driven form the SYS_RST_L pin, the SOC_ON state and enables the XTENSA
de-assertion of HOST_PWR_EN, or from a CPU to begin the boot process. Software
write to an internal register.
l
configures the AR6002 functions and
ia
2. The CPU Reset is also dependent upon the
boot strap signal EJTAG_SEL which is
n t
interfaces. When the AR6002 is ready to
receive commands from the host, it will set
latched from the GPIO_17 pin upon system
id e
the function ready bit.
initialization. The EJTAG_SEL signal is set
when there is an In-Circuit Emulator (ICE)
n f
6. The host reads the ready bit and can now
send function commands to the AR6002.
connected to the chip's JTAG port. In this
Co
7. The CPU may continue to be held in reset
situation, it is desirable to hold the CPU in
reset even after the SYS_RST_L pin has been
ro s under some circumstances until its reset is
cleared by an external pin or when the host
de-asserted and the rest of the chip is
h e
running. In this situation, the CPU Reset is
clears a register. See section 1.10 above.

At
asserted until GPIO_13 has been set 8. The MAC cold reset and the MAC/BB
(presumably by the ICE).

ry :
3. It is also possible to hold the CPU in reset
warm reset will continue to stay asserted
until their respective reset registers are

in a
until the host clears an internal register.
This depends upon the boot-strap signal
cleared.

1.12 Power Management

l i m
CPU_INIT_RST which is latched upon
system initialization from the GPIO_16 pin. The AR6002 provides integrated power

Pr e
If CPU_INIT_RST is set, then the CPU will management and control functions and
be held in reset until the host clears an extremely low power operation for maximum
internal AR6002 register. battery life across all operational states by:
■ Gating clocks for logic when not needed
4. The CPU can also be reset from the write
■ Shutting down unneeded high speed clock
that set bit-6 of the RTC_RESET register. sources
■ Reducing voltage levels to specific blocks in
1.11 Reset Sequence some states
After a COLD_RESET event, the AR6002 will ■ Reducing Tx and Rx active duty cycles
enter the SDIO_OFF state and await an enable ■ Lowering CPU frequency when
event from the host. The AR6002 CPU will not computational load is reduced
execute any instructions until after the host
enables the AR6002. The typical AR6002 1.12.1 Hardware Power States
COLD_RESET sequence is shown below:
AR6002 hardware has six top level hardware
1. The host system de-asserts CHIP_PWD_L, power states managed by the RTC block.
if asserted (use of CHIP_PWD_L is optional, Table 1-1 describes the input from the MAC,
but must be de-asserted to use the AR6002). CPU, SDIO/MBOX, interrupt logic, and timers
that effect the power states.
2. SYS_RST_L is de-asserted. The AR6002
latches the input level on GPIO-4 and Figure 1-1 depicts the state transition diagram.
GPIO-5 to determine the host interface type.

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Table 1-1. Power Management States

State Description
OFF CHIP_PWD_L pin assertion immediately brings the chip to this state
Sleep clock is disabled
No state is preserved
HOST_OFF WLAN is turned off
Only the host interface is power on - the rest of the chip is power gated (off)
The host instructs the AR6002 to transition to WAKEUP by writing a register in
the host interface domain
Embedded CPU and WLAN do not retain state (separate entry)
- This state can be bypassed by asserting CLK_REQ during de-assertion
CHIP_PWD_L
NON_ASSOCIATED_SLEEP Only the sleep clock is operating.
The high speed crystal or oscillator is disabled.

ia l
CPU, MAC, BB can be voltage scaled
n t
this state to the WAKEUP state
id e
Any wakeup events (host, LF-Timer, GPIO-interrupt) will force a transition from

All internal states are maintained

n f
ASSOCIATED_SLEEP Only the sleep clock is operating
Co
o s
The high speed crystal or oscillator is disabled

r
e
CPU, MAC, BB can be voltage scaled

h
t
Any wakeup events (MAC, host, LF-Timer, GPIO-interrupt) will force a

:A
transition from this state to the WAKEUP state

ry
All internal states are maintained
WAKEUP
a
The system transitions from sleep states to ON

in
The high frequency clock is gated off as the crystal or oscillator is brought up

l im and the PLL is enabled

Pr e
WAKEUP duration is programmable (default 3.8ms)
ON The high speed clock is operational and sent to each block enabled by the clock
control register
Lower level clock gating is implemented at the block level, including the CPU,
which can be gated off using the WAITI instruction while the system is on. No
CPU, host and WLAN activities will transition to sleep states.

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CHIP_PWD_L (from any state)

Off Low
Power
~CHIP_PWD_L SYS_RST_L or
~HOST_PWR_EN
(from any state)
Host Off
HOST_PWR_EN
ia l
n t
id e
Non-Associated Sleep
n f
XTAL Off
Co
s
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‘Any host Non-ASSOC_
transactions’ SLEEP_EN

t h
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Associated Sleep

ry
XTAL Off

in a WAKEUP
Events

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Pr e
Wakeup
Clocks Gated

Sleep XTAL_SETTLE (~2msec)

criteria
High
On Power

Wakeup Events:
Sleep Criteria:
MAC Clock request
CPU_SLEEP & HOST/MBOX request
~MAC_CLK_REQ & LF timer expiration
~HOST_CLK_REQ & UART request
~MBOX_CLK_REQ GPIO Interrupt

Figure 1-1. AR6002 State Transitions

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1.12.2 Sleep State Management The PLL output is programmable but it will
Sleep state minimizes power consumption usually run at one of only two frequencies: 320
while saving system states. In deep sleep state, MHz (during 802.11a mode) or 352 MHz
all high speed clocks are gated off and the (during 802.11 b/g mode). This base clock is
external crystal is powered off. Light sleep is divided into several clocks for the MAC and BB
similar to deep sleep, but the XTAL remains modules. There are clocks running at 160 MHz,
running for faster WAKEUP. For the AR6002 to 80 MHz, and 40 MHz going to the MAC and BB
enter sleep state, the MAC, SDIO/MBOX, and modules for 802.11a mode. (In 802.11g mode,
CPU systems must be in sleep state. these are running at 176 MHz, 88 MHz, and 44
MHz.)
When the embedded XTENSA CPU executes
the WAITI command, the SDIO/MBOX is idle The SOC clock comes from a clock divider
and the MAC system is in sleep state, the module which divides the base clock by a
AR6002 enters the system Sleep state. In sleep programmable value. By default, this value is
state, the system gates all clock trees based on 8. Hence in 802.11a mode (320 MHz base
REF_CLK with only the sleep clock logic clock), the default SOC frequency is 40 MHz
operating. The system remains in sleep state and in 802.11b/g mode (352 MHz base clock),
until a WAKEUP event causes the system to the SOC frequency is 44 MHz.
enter WAKEUP state, wait for the high When the AR6002 exits SLEEP state, it enters
frequency clock source to stabilize, and finally
ungate all enabled clock trees. The CPU exits
i l
WAKEUP state and asserts CLK_REQ or
a
enables its internal crystal oscillator depending
the WAITI state only when an interrupt
arrives, which may result from the system t
on the clock configuration. The AR6002
n
WAKEUP event.
id e
remains in WAKEUP state for a programmable
duration that must cover clock settling time.

1.13 System Clocking (RTC Block) ON states.

n f
CLK_REQ remains asserted in WAKEUP and

The AR6002 has an RTC block which controls

C o Clocking
the clocks and power going to other internal
o s
1.13.2 Low-Speed

er
modules. Its inputs consist of sleep requests The AR6002 has eliminated the need for a
from these modules and its outputs consists of

t
clock enable and power signals which are used h second crystal thereby reducing system cost.
Instead, there is now a ring oscillator which

:A
to gate the clocks going to these modules. The produces a clock that is nominally running at 2
RTC block also manages resets going to other
ry
MHz, but this can depending on process and
modules with the device. The AR6002’s

in a
clocking is grouped into two types: high-speed
and low-speed.
temperature.
The AR6002 has an internal calibration module

l im
1.13.1 High Speed Clocking
which produces a 32.768 KHz output with
minimal variation. For this, it uses the high-

Pr e
speed crystal input as the golden clock.
The crystal drives the primary clock source for Typically, this crystal input is only available
the internal PLL within the AR6002. REF_CLK when the system is in the normal operating
is the primary clock source for the analog and state and is shut down during network sleep.
digital systems. It is a high-frequency clock
sourced from either an external crystal or Hence the calibration module can adjust for
oscillator source. It is the input to the RF process and temperature variations only when
synthesizer for generating required frequencies the system is in the normal operating state.
for proper 802.11 operation. An on-chip PLL During network sleep, this module cannot
creates the appropriate clock frequency for adjust for variations in the ring-oscillator
digital logic. When the AR6002 is in SLEEP output.
state, REF_CLK is not needed. To minimize In case the output from the calibration module
power consumption, the REF_CLK generator is not accurate enough, the AR6002 does have
shuts down during deep sleep. If an external the capability to use an external low-speed
crystal is being used, the AR6002 disables the clock source. This external clock source can be
on-chip oscillator driver. If REF_CLK is coming used as the sleep clock instead of the
from an external oscillator source, the AR6002 calibration module output. GPIO_8 in the
de-asserts its CLK_REQ signal and the external AR6002 can be used as the external clock
clock source may shut down REF_CLK. source pin.

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However, the external clock source need not AR6002 information, including SDIO Common
run at 32 KHz. It can be running at any similar I/O Area (CIA), when the AR6002 is in SLEEP
low frequency. The TSF and other low state.
frequency timers need to be programmed to
match this frequency. 1.13.4 Antenna Switching
In addition to providing the low-frequency For designs that use external front-end
sleep clock for the AR6002, the 2 MHz ring components, the AR6002 provides the ability to
oscillator also runs the state machines and control those components and the internal
counters inside the AR6002's Power Control LNA with the antenna switch table. The switch
Module (PCM). The PCM controls all power table (see Table 1-2) contains 10 entries, each 5
and isolation control signals for the entire chip. bits wide, and is indexed by:
1.13.3 Interface Clock ■ The antenna selected by the MAC
■ The state of the transceiver (idle, receive, or
In addition to the clocking mentioned above,
transmit)
there is another clock source for the AR6002.
This clock is referred to as the host clock (either ■ Controls for Rx attenuation
SDIO or GSPI). This clock is completely
independent from those mentioned above and a l
When fast-receive antenna diversity is enabled,
i
is driven by the external host to communicate
n t
the baseband will temporarily override the
antenna selected by the MAC once a packet has
with the AR6002

id
been detected.e
This clock drives the interface logic as well as a
few registers which can be accessed by the
n f
host. This allows this host to probe some
Co
s
NOTE: Refer to AR6002 ART Reference Guide for more details on switching.

ro
h e
Table 1-2. Switch Table
At
Chip Ant
ry :
State
Idle
Select
—
in—
a
Rx Atten Register Name
BB_ANTENNA_CONTROL
Bluetooth
l i—m — BB_ANTENNA_CONTROL
Active
Tx
Pr e 1 — BB_SWITCH_TABLE1
Rx 1 No
Rx 1 Yes
Rx 1 Yes
Tx 2 — BB_SWITCH_TABLE2
Rx 2 No
Rx 2 Yes
Rx 2 Yes

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Each 5-bit register controls the following control antenna selection and external LNA,
AR6002 outputs (listed in the order of the most for example. For applications where the
significant bit to the least significant bit): AR6002 shares an antenna with another
wireless chip, ANTD is reserved for controlling
■ ANTE
the shared antenna switch.
■ ANTD
In normal operation, the polarity of the
■ ANTC antenna switch settings align with the
■ ANTB progammable switch table in the baseband. For
low power states, the polarity of the switch
■ ANTA settings are shown in Table 1-3.
The least significant bit of the register is ANTA.
ANTE, ANTD, ANTC, ANTB, and ANTA are
general purpose outputs that can be used to
Table 1-3. Switch Polarity for Low Power States
Chip Switch Pin Chip PWD Host Off Network Sleep
AR6002G/X ANTE Low Low Low
(BGA Package) ANTD High BT_CLK_EN*
l
BT_CLK_EN*

ia
ANTC Low Low

n t
Low
ANTB
ANTA
Low
Low
Low
Low
id e Low
Low
AR6002GZ/XZ ANTE Low Low
o nf Low
(CSP Package) ANTD High
s C
High High
ANTC
ANTB
Low
Low
e ro Low
Low
Low
Low
ANTA
t hLow Low Low

ry :A
* The polarity of ANTD is the same as BT_CLK_EN.

1.14 MAC/BB/RF Block

in a
im
The MAC has an APB interface for register
l
Pr e
accesses as well as an AHB interface which is
used by the MAC to access memory within the
VMC.

1.14.1 MAC Block

The AR6002 Wireless MAC consists of five
major blocks:
■ single host interface unit (HIU),
■ five queue control units (QCU),
■ five DCF control units (DCU),
■ single protocol control unit (PCU), and
■ single DMA receive unit (DRU).

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WMAC

DRU
DCU Arb

QCU
DCU

HIU QCU PCU

DCU

QCU

ia l
n t
id e
n f
Figure 1-2. AR6002 WMAC Interface
Co
The host interface unit connects the MAC to the
outside world via a fixed, standardized
ro s hardware, usually, QCU 4 is mapped to DCU4
and QCU3 to DCU3 and so on and the intent is

h e
interface. For AR6002, the HIU is a bridge to for the five DCUs to be used as follows:
the on-chip AHB/APB busses.
At ■ The highest-priority DCU is DCU 4.

ry :
Frame transmission begins with the QCUs,
which are responsible for managing the DMA
Typically, this DCU is the one associated
with beacons.

in a
of frame data from the host via the HIU, and
for determining when a frame is available for
transmission. Each QCU feeds into (targets)
■ The next highest priority DCU is DCU 3.
Typically, this DCU is the one associated

l i m
exactly one DCU. Ready frames are passed
with beacon-gated frames (i.e., "CAB"
traffic).

Pr e
from a QCU to its targeted DCU.
■ The next highest priority DCU is DCU 2.
The DCU manages the VDCF channel access
Typically, this DCU would be designated to
procedure on behalf of all QCUs associated
use the HCF channel access mechanism,
with it. Once the DCU gains access to the
and all frames that are to be transmitted
channel, it passes the frame to the PCU, which
according to the HCF protocol would flow
manages the final details of sending the frame
through this DCU.
to the baseband logic. The PCU also handles
processing responses to the transmitted frame ■ The remaining two DCUs (DCU1 and
and reporting the transmission attempt results DCU0) typically are used for normal EDCF
to the DCU. channel access, with DCU1 having higher
priority over DCU0. Software is responsible
Frame reception begins in the PCU, which
for mapping the eight priority levels called
receives the incoming frame bit stream from
for in the 802.11e specification on to the two
the baseband logic. The PCU passes the frame
physical EDCF DCUs.
data to the DRU, which manages receive
descriptors and transfers the incoming frame
1.15 Clock Distribution, JTAG, and Testing
data and status to the host via the HIU.
The AR6002 has clock distribution circuitry
The AR6002 MAC implements five QCUs/ which balances all the clocks going to the BB
DCUs, which support 802.11e method of and MAC. The fundamental clock (160/176
channel access. Though not required by the MHz) is provided by the RF module which gets

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divided. The BB needs this fundamental clock RF Digital-to-Analog converter (DAC), as well
together with several divided versions of it. as the internal clock synthesizer.
The MAC requires a divided 40/44 MHz clock.
In addition AR6002 has a built in JTAG 1.16 CPU Subsystem
boundary scan of its pins. It also has features The following Figure 1-3 shows the AR6002's
which allow for testing of the MBIST modules, CPU Subsystem:
the RF Analog-to-Digital converter (ADC), the

TAP
JTAG
Controller

iRAM
XTENSA
CORE
dRAM

XLMI

CPU_AHB AHB
ia l
n t
id e
n f
Co
ro s
Figure 1-3. CPU Subsystem

The heart of the CPU subsystem consists of the

h e■ RTC power state control:

t
XTENSA core. This is a 32-bit RISC core with a
The core frequency is controlled by the Real

:A
5-stage pipeline and with 16-bit and 24-bit
Time Control (RTC) module in AR6002. The
instruction encoding. The AR6002 does not
ry
XTENSA core is designed to run at a maximum
utilize the Tensilica Instruction Extension (TIE)
feature.
in a
The core accesses local memory space through
frequency of 60 MHz. In deep sleep mode, the
voltage supply to the SOC block, which
includes the CPU, can be scaled down to save

l im
iRAM interface for instructions and dRAM leakage power. Refer to “System Clocking

Pr e
interface or data. The core can also access (RTC Block)” on page 10 for detailed
memory through its Xtensa Local memory descriptions.
Interface (XLMI) bus. This bus is used
■ CPU Idle Instruction:
primarily to access registers within the MAC,
BB, and other AR6002 functions. Software can put the CPU into Idle sleep state
by issuing a WAITI instruction. This will gate
The module "CPU_AHB" converts this XLMI
off all clocks within the CPU core.
bus into a standard AHB bus. This module can
buffer up to 4 write requests. When the ■ Logic level clock gating:
XTENSA core makes a read request, all The core has been configured with several
buffered write requests are first completed in clock gating elements which scale down clocks
order to maintain data integrity. to circuitry that is not changing.
The CPU subsystem also has a TAP controller
which allows for debugging using an external 1.18 Memory
JTAG interface. The AR6002 supports the following virtual and
physical memory mapping. See Figure 1-4 for
1.17 CPU Power Consumption details.
The XTENSA core power consumption can be
controlled by the following means:

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0x40_0000

0xc0_0000
iRAM 0x12_e000
Space RAM
0x80_0000 (184 k)
dRAM 0x10_0000
Space
0x40_0000 0xf_4000
XLMI ROM
Space (80 k)
0 0xe_0000
Virtual Memory
Space 0x4_0000
(12 Mbytes) XLMI
(256k)
0
Virtual Memory
Space
(4 Mbytes)

ia l
n t
Figure 1-4. Virtual and Physical Memory Mapping
id e
1.19 Interrupts n f
The AR6002 core supports a total of 18 Co
interrupts. The first one (Int. 0) is a software
interrupt at level-1 and the second one (Int. 1)
ro s
is a timer interrupt at level-2. The others are
h e
t
hardware interrupts for various configurations.
A
ry :
in a
l i m
Pr e

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ia l
n t
id e
n f
Co
ro s
h e
t
ry :A
in a
l im
Pr e

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2. Host Interfaces
The AR6002 can work in various modes of IO information area (CIA) registers for identifying
host configuration, including SDIO and and initializing the AR6002. These registers
Generic SPI (GSPI). include the card common control register
(CCCR) and function basic register (FBR) as
Table 2-1 shows pin settings for mode
well as CIS tuple space for CIS0 and CIS1. All
configuration, sampled during reset.
other interface communication occurs in SDIO
Table 2-1. Pin Settings for Mode function 1 address space. Figure 2-1 shows the
Configuration generic SDIO address map.
GPIO5 GPIO4 Configuration Figure 2-1 shows the generic SDIO address
map.
0 0 GSPI Mode
1 X SDIO Mode
0 1 Reserved

2.1 SDIO and GSPI Interfaces

ia l
The AR6002 interface is compliant with SDIO
v1.1 and supports the SDIO common
n t
id e
CIA (Function 0)
n f
CCCR
FBR__(function__1) Co
0x000000 - 0x0000FFF
s Window
16_MB

ero
0x000100 - 0x0001FFF FBR__(function__2) Window Optional
0x000200 - 0x0002FFF
t h
FBR__(function__3) Window Code
Storage

:A
...

Area (CSA)

ry
0x000300 - 0x0003FFF FBR__(function__7) Window

in a
0x000700 - 0x0007FFF
0x000800 - 0x0008FFF
RFU
CIS__Area

l i m
0x001000 - 0x0017FFF common_and_per-function

Pr e
0x018000 - 0x001FFFF RFU CIS_ Pointers

128 K Register Space

(Function 1-7)
0x000000 - 0x001FFFF Function - Unique

Figure 2-1. SDIO Address Map

2.2 Host Interface Address Map

The host sees the same address map interface mapping has been added to mailbox 0 for
regardless of the physical interface used, thus future usage.
allowing the software layer above the physical Figure 2-2 shows the host interface address
interface to be identical across physical map.
interface types. The lower 2 KB of address
space must map all interface registers. The
SDIO and GSPI interface can use mailbox
aliases above 2 KB as these aliases provide
larger window interfaces for increased
performance. An extra 6 KB of address

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10 KB – 16 KB
Extra Mailbox 0 0x3FFF
alias for future Mbox0 Alias
usage 0x2800
Mbox3 Alias
2 KB – 10 KB 0x2000
Maps to SDIO
and GSPI only
Mbox2 Alias
(Larger 0x1800
aliases for Mbox1 Alias
MBox access) 0x1000
Mbox0 Alias
0x800
Window
Host Side
SDIO/GSPI CIS Window
0x600
Control Registers Internal
0x400 Memory Map
Mbox3 DMA
0 KB – 2 KB 0x300
Maps to all
interfaces 0x200
Mbox2 DMA
ia l
256 MB

0x100
Mbox1 DMA
n t
Mbox0 DMA
id e
0x000

n f
o
Figure 2-2. Host Interface Address Map
C
ro s
h e
At
ry :
in a
l i m
Pr e

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2.3 Mailboxes 2.4 Interrupts

The AR6002 supports four full duplex This section summarizes how interrupts flow
mailboxes to move messages between the between the AR6002 CPU and Host CPU. All
AR6002 and the external host. Messages interrupts can be masked by control registers.
include packets, control messages, or any
software-defined communication. AR6002 2.4.1 AR6002 to Host
hardware uses End of Message (EOM) markers ■ The AR6002 CPU writes to the interrupt
to denote the end of a message that spans one register
or more memory descriptors on the AR6002 ■ Data ready
side. Rx FIFO is not empty (clears on Rx FIFO
The flow control of the four mailboxes must be empty)
managed by software. To assist software flow ■ Error interrupts, underflow or overflow
control, hardware provides eight counters as a ■ Wake up interrupt
credit mechanism. The counters may count Set when the AR6002 exits sleep
messages, memory buffers, packets, or any unit ■ Flow control
that software defines. The host and AR6002
Any COUNT goes from 0 to 1 (cleared
CPUs can read and write these counters using
ordinary writes or atomic operations. Counter
when COUNT goes 1 to 0)
ia l
resource use is optional. ■ Option
n t
All AR6002 internal interrupts can be
2.3.2 Error Conditions
id e
mapped to the host in case the host wants to
If the host driver and AR6002 software lose
flow control synchronization for any reason,
n f
take complete control of the AR6002 MAC
and resources
mailbox errors conditions could arise.
C o Host to AR6002
2.4.2
■ Tx Mailbox Overflow
s
ero
■ Host writes to INT_WLAN
If no DMA descriptors are available on the
■ Error Interrupts (underflow or overflow)

t h
AR6002 Tx side, but the host still sends a
message, the Tx Mailbox stalls the host ■ TX_CNT goes from 1 to 0 (out of

:A
physical interface. If the host interface descriptors)

ry
remains stalled with the Tx FIFO full for a
timeout period FIFO_TIMEOUT, a timeout

in a
error occurs. An interrupt is sent to the
AR6002 CPU and the Host CPU. If the host

i m
status overflow bit is set, any mailbox Tx
l
Pr e
bytes that arrive from the host when the
mailbox is full, are discarded. When the
host clears overflow interrupt, mailbox
FIFOs return to normal operation. Software
must then either resynchronize flow control
state or reset the AR6002 to recover.
■ Rx Mailbox Underflow
If the host DMA engine reads a mailbox that
does not contain any data, the host physical
interface stalls. If this condition persists for
more than a timeout period, the host and
the AR6002 are sent an underflow error
interrupt. As long as the host status
underflow bit is set, any mailbox reads that
arrive when the mailbox is empty, return
garbage data. When the host clears
underflow interrupt, mailbox FIFOs return
to normal operation. Software must then
either resynchronize flow control state or
reset the AR6002 to recover.

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ia l
n t
id e
n f
Co
ro s
h e
At
ry :
in a
l i m
Pr e

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3. Radio
The AR6002 transceiver consists of four major ■ Transmitter (Tx)
functional blocks (see Figure 3-1): ■ Frequency synthesizer (SYNTH)
■ Receiver (Rx) ■ Associated bias/control (BIAS)

RFIn Receiver RxOut

Frequency
REFCLK
Synthesizer

TxIn
RFOut Transmitter

Bias/Control Control

Radio
ia l
Figure 3-1. Radio Functional Block Diagram
n t
id e
3.1 Receiver (Rx) Block
n f
The receiver converts an RF signal (with 20
Co the receiver topology includes an LNA, a VGA,
MHz bandwidth) to baseband I and Q outputs.
The receiver is tuned to 2.4 GHz and 5.4 GHz
ro s a direct conversion mixer and a baseband
programmable filter. For the 2 GHz operation,
for IEEE 802.11 b/g and 802.11a signals,
h e the receiver is implemented using the direct

Rx block diagram.
At
respectively. Figure 3-2 shows the Radio Tx/ conversion topology.

ry :
For the 5 GHz operation, the receiver is
For both 5G and 2G paths, mixers down
convert the signal to baseband in-phase (I) and

in a
comprised of a low noise amplifier (LNA)
followed by a variable gain amplifier (VGA), a
radio frequency (RF) mixer, an intermediate
quadrature-phase (Q) signals. The I and Q
signals are low-pass filtered and amplified by
the baseband programmable gain filter

l i m
frequency (IF) mixer, and a baseband controlled by digital logic. The baseband I and

Pr e
programmable gain filter. For the 5 GHz Q signals are sent to the ADC. The baseband
operation, the receiver is implemented using programmable gain filter is shared between the
the sliding IF topology. 2G and 5G paths.
For the 2 GHz operation, the receiver is The DC offset of the receive chain is reduced
comprised of two separate paths: LNA1 and using multiple digital to analog converters
LNA2. For the LNA1 path, the receiver input is (DACs) controlled by the MAC/baseband
shared with the power amplifier (PA) output, block. Additionally, the receive chain can be
thus eliminating the need for an external digitally powered down to conserve power.
transmit/receive (T/R) switch. By eliminating
an external T/R switch the overall cost of the
final solution is reduced. For the LNA2 path,
the T/R switch is needed because LNA2 input
is not shared with the PA output. LNA2 path is
targeted for applications where the best
receiver sensitivity is the primary objective,
whereas the LNA1 path is for cost sensitive
applications. For the LNA1 path, the receiver is
comprised of an LNA, an LNA buffer, a VGA, a
direct conversion mixer and a baseband
programmable gain filter. For the LNA2 path,

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5G Tx

rf5out XX
X X
TxinI

2G Tx
TxinQ

X
Tx Filter
Rf2out/
LNA1in LNA1 path – 2G Rx

RxoutI
X
RxoutQ
rf2in

LNA2 path – 2G Rx Rx Filter

ia l
n t
rf5in
X X
id e
5G Rx

n f
Figure 3-2. Radio Tx/Rx Block Diagram Co
ro s
3.2 Transmitter (Tx) Block
h e
The transmitter converts baseband I and Q
inputs to bands centered around 2.4 GHz and At The transmit chain can be digitally powered
down to conserve power. To ensure that FCC

ry
5.4 GHz for IEEE 802.11 b/g and 802.11a : limits are observed and output power stays

in Figure 3-2.
in a
signals respectively. A block diagram is shown close to the maximum allowed, transmit output
power is adjusted by a closed loop digitally
programmable control loop at the start of each

l m
The outputs of the DAC are low pass filtered
i
through an on-chip reconstruction filter to
packet. The closed-loop power control can be

Pr e
based on an on-chip or off-chip power detector.
remove spectral images and out-of-band
quantization noise.
3.2.1 Synthesizer (SYNTH) Block
For the 5 GHz operation, the transmitter is The radio supports an on-chip synthesizer to
comprised of the programmable reconstruction generate local oscillator (LO) frequencies for
filter, an IF mixer, an RF mixer, a preamplifier receiver and transmitter mixers. Figure 3-3
and a PA. The IF mixer converts baseband shows the synthesizer topology.
signals to an intermediate frequency. The RF
mixer converts the IF signal into radio The Synthesizer can use several Xtals such as
frequency signals, which are driven off_chip 19.2, 24, 26, 38.4, 40, and 52 MHz. For AR6002,
through the preamplifier and the PA. For the 5 the default Xtal is 26 MHz.
GHz operation, the transmitter is implemented A reference circuitry generates a signal used as
using the sliding IF topology. the synthesizer reference input. An on-chip
For the 2 GHz operation, the transmitter is voltage controlled oscillator (VCO) provides
comprised of the programmable reconstruction the desired LO signal based on a phase/
filter, a direct conversion mixer, a preamplifier frequency locked loop. The loop filter
and a PA. For the 2 GHz operation, the components are all integrated on-chip and can
transmitter is implemented using the direct be digitally controlled. On power up or
conversion topology.

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channel reselection, the synthesizer takes about

0.2 msec to settle.

Reference Phase
Charge To Local
Input from Frequency VCO
Pump Oscillator
Crystal Detector Loop Filter
(on-chip)

Divider
Synthesizer
Channel Select
Figure 3-3. Radio Synthesizer Block Diagram

3.3 Bias/Control (BIAS) Block

The bias/control block provides reference 3.4 Baseband Block
voltages and currents for all other circuit
ia l
The AR6002 baseband module (BB) is the
blocks (see Figure 3-4). An on-chip bandgap
reference circuit provides the needed voltage t
physical layer controller for the 802.11a/g air
n
and current references based on an external
6.19 KΩ ± 1% shunted to GND resistor.
id e
interface. It is responsible for modulating data
packets in the transmit direction, and detecting
f
and demodulating data packets in the receive
n
Codirection. All processing is done at the
baseband frequency. See Figure 3-4.

ro s
h e Biasing Bias Reference Resitor
Control Interface From
At Control Registers
...

Baseband
:
ary
Figure 3-4. Bias/Control Block Diagram

in
l i m
Pr e
detection flags,
rssi & noise-floor updates
802.11b
AGC
downsampled data Receiver
gain
adc samples, updates
power meas.
Tx data bytes from
mac, bb phy
State
configuration
Front-End Machine
& Config. Rx data bytes,
timing, rssi / PLCP header,
time domain radio configuration
band-width
samples decoded data & gain control
info

FFT Viterbi
Channel
Correction

Figure 3-5. Baseband Module Block Diagram

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There are five major blocks within the data path. This feedback loop recognizes when
baseband module: input signals seen by the ADC are either too
small or too large, or even saturated. When this
■ SM
situation happens, the AGC block requests a
■ AGC gain change to the radio through the SM block
■ TIM radio interface.

■ FFT Because the state of current and previous gain

changes usually coincide with the arrival/
■ VIT departure of packets on the air, the AGC block
■ BBB also signals detection status to the SM block, so
that it can turn on necessary receiver blocks
Described below are the major functions for that would otherwise be idle with no signal to
each block, and how they interact with other decode. There are two major mechanisms for
blocks in the system. this: strong signal detection and weak signal
detection. Strong signal detection simply looks
3.4.1 SM Block for large changes in incoming signal strength,
The SM block is the main state machine for the and will assume that these "strong signals" are
baseband PHY. It encapsulates two major
a l
most likely packets to try and decode. Weak
i
interfaces to the MAC and radio modules. The
MAC interface is the interface that passes
n t
signal detection will correlate against known
preamble sequences when gain changes are not
packet data to/from the MAC layer. This is
id e
occurring. A match with a CCK or OFDM short
done through a dedicated 8-bit bus interface
that is controlled through transmit and receive
n f
preamble will trigger a detection flag for these
types of "weak signals."
framing signals. A separate configuration
address space for the baseband block is written o Block
3.4.3CTIM
through the MAC block, as the baseband block
is not directly connected to the AHB bus. The
ro s
The TIM block is the time domain baseband

h
baseband to radio interface is a low-latency e front end for the transmitting and receiving of
packets. On transmit, it is responsible for
t
shift control interface that allows the baseband

:A
filtering and upsampling signals to a
module to quickly and autonomously adjust bandwidth and sampling rate appropriate to

ry
radio settings to reflect the current packet the DAC. If there are any radio impairments

in a
sizing and direction flow. This usually takes
the form of gain updates, ADC and DAC on/
off settings, transmit and receive bias settings,
that need to be corrected (carrier leak, etc.),
they are corrected here. On receive, the TIM

i m
and calibration mode configurations.
l
block does all data path processing for time
domain related signals. Like on transmit, this

Pr e
For transmitted packets, the SM block also includes all filtering and sample rate
houses the OFDM and CCK encoders/ conversions necessary for processing the
modulators. These encoder/modulator blocks incoming signal. Power measurements are
format the packet data from the MAC, and performed here to aid the AGC block in ADC
generate symbols which are used for signal sizing. Correlation to know preamble
transmission over the air. These symbols are sequences are also done here for weak signal
either converted into the frequency domain for detection. When a detection flag is set, coarse
OFDM modulation (FFT block), or are directly timing acquisition and frequency correction are
upsampled to the DAC for CCK modulation done in the TIM block, as these functions are
(Front-End block). Decisions on rate and performed on data before translation into
output power are directed by the MAC frequency domain signals (in the FFT).
through the use of transmit data headers.
3.4.4 FFT and VIT Blocks
3.4.2 AGC Block The FFT block takes a signal sampled in time,
The AGC block is responsible for two receive and performs a fast fourier transform to get
related functions: signal sizing and signal frequency bins of data sampled in frequency
detection. Because the ADC dynamic range bins. These frequency bins are used for OFDM
does not span all possible input power levels, symbol decoding. For receive packets, an
an automatic gain control feedback loop is estimate of the channel over the air is
designed into the radio and baseband receive computed in the FFT block as the long training

24 • AR6002 MAC/BB/Radio for Embedded WLAN Applications Atheros Communications, Inc.

24 • April 2008 PRELIMINARY: ATHEROS CONFIDENTIAL
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sequence is a known sequence in the frequency

domain. Before symbols can be decoded, this
channel estimate is inverted and applied to the
incoming frequency symbols for channel
correction. The Viterbi soft-decision decoder is
contained within the VIT block, and is
responsible for descrambling, deinterleaving,
and decoding the symbols from the FFT.
For transmitted OFDM symbols, the FFT block
is reused and "run in reverse" to compute the
inverse fast fourier transform (iFFT). While
running in iFFT mode, the FFT block takes in
symbols from the SM block, and converts them
to time samples that can be upsampled and
filtered in the TIM block.

3.4.5 BBB Block

The BBB block is the 802.11b receiver used to
ia l
demodulate and decode CCK packets in the 2.4
n t
GHz range channels. It is a self contained unit
that does not need other logic from the OFDM
id e
blocks except for some Front-End (TIM)
filtering and down conversion. When a
n f
potential packet is detected by the AGC block,
Co
both the OFDM receiver logic and the BBB
block logic are enabled in a voting process.
ro s
h e
This process reduces potential latency penalties
by running both receivers in parallel while the

At
detection state machine (AGC) tries to decide

ry :
which type of protocol the incoming packet has
been modulated with. This is done by

in a
comparing the relative preamble correlation
power for the two protocol types.

l i m
Pr e

Atheros Communications, Inc. AR6002 MAC/BB/Radio for Embedded WLAN Applications • 25

PRELIMINARY: ATHEROS CONFIDENTIAL April 2008 • 25
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ia l
n t
id e
n f
Co
ro s
h e
At
ry :
in a
l i m
Pr e

26 • AR6002 MAC/BB/Radio for Embedded WLAN Applications Atheros Communications, Inc.

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4. Electrical Characteristics
4.1 Absolute Maximum Ratings
Table 4-1 summarizes the absolute maximum If a 3V supply is available on the board, it can
ratings and Table 4-2 lists the recommended be tied to VDD_ANT. If not, an internal
operating conditions for the AR6002. Absolute regulator can be used. VCC_FEM accepts
maximum ratings are those values beyond voltages from 3.2V to 4.2V and provides an
which damage to the device can occur. output regulated to 3.0V on LDO_OUT. A
lower voltage, down to 3.0V, can be provided,
Functional operation under these conditions,
but the output voltage is about 200mV below
or at any other condition beyond those
the input. If LDO is used, VDD_ANT should be
indicated in the operational sections of this
tied to LDO_OUT.
document, is not recommended.
The AR6002 requires 3 power levels, 1.2V, 1.8V NOTE: Maximum rating for signals follows the
and 3V. The digital core runs off of 1.2V. The supply domain of the signals.
analog block requires 1.2V and 1.8V to operate.
A 3V level is required to control front-end
ia l
components like xPA or a switch, which are
made of semiconductors requiring 2.8V or
n t
higher.
id e
Table 4-1. Absolute Maximum Ratings
n f
Symbol (Domain) Parameter
Co Max Rating Unit
s
ero
DVDD12 Digital 1.2V core supply -0.3 to 1.35 V
AVDD12 Analog 1.2V core supply -0.3 to 1.35 V
AVDD18 t h
Analog 1.8V I/O supply -0.3 to 2.5 V
DVDD_SDIO

ry :A
SDIO I/O supply -0.3 to 4.0 V
DVDD_GPIO0
DVDD_GPIO1
in a
GPIO0 I/O supply
GPIO1 I/O supply
-0.3 to 4.0
-0.3 to 4.0
V
V
DVDD_BT
l i m BT coexistence I/O supply -0.3 to 4.0 V

Pr e
VCC_FEM Battery voltage LDO input -0.3 to 4.35 V
VDD_ANT Antenna control I/O supply -0.3 to 3.15 V
RFin Maximum RF input (reference to 50Ω input) +10 dBm

Tstore Storage temperature –45 to 135 °C

ESD Electrostatic discharge tolerance 2000 [1] V

[1]All pins except XTALI (BGA pin A11, CSP bump 85), RF5INN (BGA pin B1, CSP bump 8), and RF5INP (BGA pin B1,CSP
bump 9). Maximum rating is 1000V for XTALI and 1500V for RF5INN/RF5INP.

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4.2 Recommended Operating Conditions

Table 4-2. Recommended Operating Conditions

Symbol (Domain) Parameter Min Typ Max Unit

DVDD12 Digital 1.2V core supply 1.14 1.2 1.26 V
AVDD12 Analog 1.2V core supply 1.14 1.2 1.26 V
AVDD18 Analog 1.8V I/O supply 1.71 1.8 1.89 V
DVDD_SDIO SDIO I/O supply 1.71 1.8 3.46 V
DVDD_GPIO0 GPIO0 I/O supply 1.71 1.8 3.46 V
DVDD_GPIO1 GPIO1 I/O supply 1.71 1.8 3.46 V
DVDD_BT BT coexistence I/O supply 1.71 1.8 3.46 V
VCC_FEM Battery voltage LDO input 3.0 3.6 4.2 V
VDD_ANT Antenna control I/O supply 1.71 3.0 3.46 V
Tambient Ambient temperature –40 25
a
85

i l °C

n t
id e
n f
Co
ro s
h e
t
ry :A
in a
l im
Pr e

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4.3 DC Electrical Characteristics

Table 4-3 and Table 4-4 list the general DC operating conditions (unless otherwise
electrical characteristics over recommended specified).

Table 4-3. General DC Electrical Characteristics (For 3.3 V I/O Operation)

Symbol Parameter Conditions Min Typ Max Unit
VIH High Level Input Voltage 0.8 x Vdd - Vdd + 0.3 V
VIL Low Level Input Voltage –0.3 - 0.2 x Vdd V
IIL Input Leakage Without Pull-up 0 V < Vin < Vdd –10 10 μA
Current or Pull-down 0 V < Vout < Vdd
With Pull-up or 0 V < Vin < Vdd –65 65 μA
Pull-down 0 V < Vout < Vdd
VOH High Level Output Voltage IOH = –4 mA Vdd – 0.35 - - V

IOH = –12 mA[1] Vdd – 0.35 -

ia l - V
VOL Low Level Output Voltage IOL = 4 mA -
t
- 0.40 V
IOL = 12 mA[1] -

id en - 0.40 V
CIN Input Capacitance[2] -

n f
- 6 - pF

Co
[1]For these pins only: SDIO_DATA_0, SDIO_DATA_1, SDIO_DATA_2, SDIO_DATA_3
[2]Parameter not tested; value determined by design simulation

ro s
h e
t
Table 4-4. General DC Electrical Characteristics (For 1.8 V I/O Operation)
A
:
ary
Symbol Parameter Conditions Min Typ Max Unit
VIH High Level Input Voltage 0.8 x Vdd - Vdd + 0.2 V
VIL
in
Low Level Input Voltage –0.3 - 0.2 x Vdd V
IIL
l i m
Input Leakage Without Pull-up 0 V < Vin < Vdd –10 - 10 μA

Pr e
Current or Pull-down 0 V < Vout < Vdd
With Pull-up or 0 V < Vin < Vdd –35 - 35 μA
Pull-down 0 V < Vout < Vdd
VOH High Level Output Voltage IOH = –2 mA Vdd – 0.35 - - V

IOH = –6 mA[1] Vdd – 0.35 - - V

VOL Low Level Output Voltage IOL = 2 mA - - 0.3 V
IOL = 6 mA [1] - - 0.3 V
CIN Input Capacitance[2] - - 6 - pF

[1]For these pins only: SDIO_DATA_0, SDIO_DATA_1, SDIO_DATA_2, SDIO_DATA_3

[2]Parameter not tested; value determined by design simulation

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The following three figures show the Power Sequence operation for the AR6002.

I/O Supply = AVDD18, DVDD_SDIO, DVDD_GPIO0, DVDD_GPIO1, DVDD_BT, VCC_FEM, VDD_ANT

1.2V Supply = DVDD12, AVDD12

I/O Supply

1.2V Supply

CHIP_PWD_L

SYS_RST_L

Ta Tb Tc Td

Figure 4-1. Power Up/Power Down Timing While Asserting CHIP_PWD_L

ia l
n t
id e
I/O Supply

n f
1.2V Supply
Co
ro s
CHIP_PWD_L

h e
t
:A
SYS_RST_L

Ta
a ry Te Tf Td

m in
l i
Pr e
Figure 4-2. Power Up/Down Timing While Asserting SYS_RST_L

I/O Supply

1.2V Supply

CHIP_PWD_L

SYS_RST_L

Tf Tg

Figure 4-3. Reset and Power Cycle Timing

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Table 4-5. Timing Diagram Definitions

Description Min (μsec)

Ta Time between I/O supply valid** and 0
1.2V supply valid

Tb Time between 1.2V supply valid and 5

CHIP_PWD_L deassertion

Tc Time between CHIP_PWD_L assertion 0

and 1.2V supply invalid

Td Time between 1.2V supply invalid and 0

I/O supply valid

Te Time between 1.2V supply invalid and 0

SYS_RST_L deassertion

Tf Length of SYS_RST_L pulse 1

ia l
Tg Length of CHIP_PWD_L pulse 5
n t
** Supply valid represents the voltage level has reached
id e
90% level.
n f
Co
ro s
h e
At
ry :
in a
l i m
Pr e

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4.4 Radio Receiver Characteristics

Table 4-7 and Table 4-6 and Table 4-8
summarize the AR6002 receiver characteristics.
Table 4-6. Receiver Characteristics for 2.4 GHz Operation (LNA1 Path - Shared Tx/Rx)

Symbol Parameter Conditions Min Typ Max Unit

Frx Receive input frequency range 5 MHz 2.312 - 2.484 GHz
channel spacing
NF Receive chain noise figure See Note [1] - 5 - dB

Srf Sensitivity See Note [2] dBm

- -95 -
1 Mbps
- -91 -
2 Mbps
- -89 -
5.5 Mbps
- -86 -
11 Mbps
- -90 -
6 Mbps
- -90 -
9 Mbps
12 Mbps
-
-
-89
-86
i
-
a
- l
18 Mbps
24 Mbps
- -83
n t -
36 Mbps
-
-
id e
-79
-75
-
-
48 Mbps
54 Mbps
n f - -73 -

IP1dB Input 1 dB compression (min. gain) -

Co - +11 - dBm
IIP3 Input third intercept point (min. gain) -
ro s - +19 - dBm
ERphase I, Q phase error
h e - 1 - degree

t
:A
ERamp I, Q amplitude error - 0.5 - dB

ry
Radj Adjacent channel rejection 10 to 20 MHz dB
1 Mbps
11 Mbps
in a -
-
35
33
-
-
6 Mbps

l
54 Mbpsim -
-
36
22
-
-

Pr e
TRpowup Time for power up (from RxOn) - - 1.5 - μs

[1]Does not include the effect of an external RF filter.

[2]Sensitivity performance based on the Atheros reference design, which includes RF filter. No T/R switch, no external
LNA. Port shared with the PA.

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Table 4-7. Receiver Characteristics for 2.4 GHz Operation (LNA2 Path - Separate Rx)

Symbol Parameter Conditions Min Typ Max Unit

Frx Receive input frequency range 5 MHz 2.312 - 2.484 GHz
channel spacing
NF Receive chain noise figure See Note [1] - 3.5 - dB

Srf Sensitivity See Note [2] dBm

1 Mbps - -97 -
2 Mbps - -93 -
5.5 Mbps - -91 -
11 Mbps - -88 -
6 Mbps - -92 -
9 Mbps - -92 -
12 Mbps - -91 -
18 Mbps - -88 -
24 Mbps -
a
-85
i l -
36 Mbps
48 Mbps
-
-
n t-82
-77
-
-
54 Mbps
id e
- -75 -
IP1dB Input 1 dB compression (min. gain) -
n f - +3 - dBm
IIP3 Input third intercept point (min. gain) -
Co - +11 - dBm
ERphase I,Q phase error

ro s - 1 - degree

ERamp I,Q amplitude error

h e - 0.5 - dB
Radj Adjacent channel rejection

At 10 to 20 MHz dB
1 Mbps
11 Mbps
ry : -
-
36
34
-
-
6 Mbps
54 Mbps
in a -
-
37
24
-
-
TRpowup
l i m
Time for power up (from RxOn) - - 1.5 - μs

Pr e
[1]Does not include the effect of an external RF filter or Tx/Rx antenna switch.
[2]Sensitivity performance based on the Atheros reference design, which includes RF filter, Tx/Rx antenna switch, no
external LNA

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Table 4-8. Receiver Characteristics for 5 GHz Operation

Symbol Parameter Conditions Min Typ Max Unit

Frx Receive input frequency range 5 MHz center 4.90 - 5.925 GHz
frequency
NF Receive chain noise figure (max. See Note [1] and [2] - 5.5 dB
gain)
Srf Sensitivity See Note [2] dBm
6 Mbps - -92 -
54 Mbps - -73 -
IP1dB Input 1 dB compression (min. gain) - +5 - dBm
IIP3 Input third intercept point - +13 - dBm
(min. gain)
ERphase I,Q phase error - 2 - degree

ERamp I,Q amplitude error - 0.5 - dB

Radj Adjacent channel rejection 10 to 20 MHz
ia l dB

t
en
6 Mbps - 22 -
54 Mbps - 5 -
Ralt Alternate channel rejection 20 to 30 MHz
f id - dB
6 Mbps
o n
- 37
54 Mbps
s C - 20
TRpowup Time for power up (from RxOn) -

e ro - 1.5 - μs

[1]With an external LNA.

t h
[2]Sensitivity performance is based on the Atheros reference design, which includes RF filter, Tx/Rx antenna switch,
and an external LNA.

ry :A
in a
l im
Pr e

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4.5 Radio Transmitter Characteristics

Table 4-9 and Table 4-10 summarize the
transmitter characteristics for AR6002.
Table 4-9. Transmitter Characteristics for 2.4 GHz operation

Symbol Parameter Conditions Min Typ Max Unit

Ftx Transmit output frequency range 5 MHz center 2.312 - 2.484 GHz
frequency
Pout Without xPA: Mask Compliant CCK - +8 - dBm
output power
Without xPA: EVM Compliant - +5 - dBm
OFDM output power for 64 QAM
With xPA: Mask Compliant CCK - +16 - dBm
output power
With xPA: EVM Compliant OFDM
output power for 64 QAM
- +16

ia l - dBm

t
en
SPgain PA gain step See Note [1] - 0.5 - dB

fid
Apl Accuracy of power leveling loop See Notes [2] [3] - +1/-1.5 - dB

OP1dB Output P1dB (max. gain)

o n
2.442 GHz - 12 - dBm

sC
OIP3 Output third order intercept point 2.442 GHz - 19 - dBm
(max gain)

ero
SS Sideband suppression - -35 - dBc
TTpowup Time for power up (from TxOn)
t h - - 1.5 - μs

:A
[1]Guaranteed by design.

ry
[2]Manufacturing calibration required.

a
[3]Not including tolerance of external power detector and its temperature variation.

in
l i m
Pr e

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Table 4-10. Transmitter Characteristics for 5 GHz Operation

Symbol Parameter Conditions Min Typ Max Unit

Ftx Transmit output frequency range 20 MHz center 4.9 - 5.925 GHz
frequency
Pout EVM Compliant OFDM output See Note [1] - -2 - dBm
power for 64 QAM
SPgain PA gain step See Note [2] - 0.5 - dB

Apl Accuracy of power leveling loop See Note [3] - +1/-1.5 - dB

OP1dB Output P1dB (max. gain) 5.25 GHz - 4 - dBm

OIP3 Output third order intercept point 5.25 GHz - 12 - dBm
(max gain)
SS Sideband suppression - -32 - dBc
Txmask Transmit spectral mask See Note [4] dBr
At 11 MHz offset
At 20 MHz offset
-
-
-22
-32
-

i
-
a l
At 30 MHz offset - -52
n t -
TTpowup Time for power up (from TxOn) -

id e
1.5 - μs

[1]Measured without a BALUN. Output is single ended.

n f
[2]Guaranteed by design.
[3]Manufacturing calibration required.
Co
System includes external PA.
ro s
[4]Measured at the antenna connector port. Average conducted transmit power levels = 18 dBm at 64 QAM (OFDM).

h e
AR6002 Synthesizer Characteristics A
t
4.6
r y
Table 4-11 and Table 4-12 summarize the
:
na
synthesizer characteristics for the AR6002.
i
l im
Table 4-11. Synthesizer Composite Characteristics for 2.4 GHz Operation

Pr e
Symbol Parameter Conditions Min Typ Max Unit
Pn Phase noise (at Tx_Out) dBc/Hz
At 30 KHz offset - –99 -
At 100 KHz offset - –99 -
At 500 KHz offset - –108 -
At 1 MHz offset - –115 -
Fc Center channel frequency Center frequency at 2.312 - 2.484 GHz
5 MHz spacing [1]
Fref Reference oscillator frequency ± 20 ppm - 40/262 - MHz

Fstep Frequency step size (at RF) See Note - 1 - MHz

TSpowup Time for power up (from sleep) - - 0.2 - ms

[1]Frequency is measured at the Tx output.

[2] Other supported frequencies are: 19.2, 24, 26, 38.4, 40, and 52 MHz.

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Table 4-12. Synthesizer Composite Characteristics for 5 GHz Operation

Symbol Parameter Conditions Min. Typ. Max. Unit

Pn Phase noise (at Tx_Out) dBc/Hz
- -
At 30 KHz offset –91
- -
At 100 KHz offset –91
- -
At 500 KHz offset –100
- -
At 1 MHz offset –107
Fc Center channel frequency Center frequency at 4.90 - 5.925 GHz
5 MHz spacing [1]
Fref Reference oscillator frequency ± 20 ppm - 40/263 - MHz

Fstep Frequency step size (at RF) See Note [2] - 5 - MHz

TSpowup Time for power up (from sleep) - - 0.2 - ms

ia l
[1]Frequency is measured at the Tx output.
n t
[2]5 MHz channel spacing is for the 5.725 to 5.925 GHz band.
[3] Other supported frequencies are: 19.2, 24, 26, 38.4, 40, and 52 MHz.
id e
n f
Co
ro s
h e
At
ry :
in a
l i m
Pr e

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4.7 Typical Power Consumption

Performance
The following tables illustrate TYPICAL, room
temperature power consumption data
measured on the Atheros SD21 evaluation
board.

Table 4-13. AR6002 Typical Power Consumption - Low Power States

Current Consumption [mA] Power

Consumption
Mode Chip Set @1.2 V @1.8 V @3.3 V [mW]
Standby CHIP_PWD AR6002G/GZ/X/XZ 0.008 0.000 0.000 0.010

HOST_OFF AR6002GZ/XZ 0.050 0.007 0.001 0.076

AR6002G 0.050 0.012 0.019

l
0.144

ia
AR6002X 0.050 0.007 0.019

n t 0.135

SLEEP AR6002GZ/XZ 0.500 0.007

e
0.002

id
0.619

nf
AR6002G 0.500 0.012 0.002 0.628

AR6002X 0.500
Co
0.007 0.002 0.619

IEEE PS DTIM=1 AR6002GZ/XZ 1.750

ro s 0.707 0.042 3.51

AR6002G
h e1.750 0.712 0.042 3.52

t
:A
AR6002X 1.750 0.707 0.042 3.51

ary
DTIM=3 AR6002GZ/XZ 0.917 0.240 0.015 1.58

AR6002G 0.917 0.245 0.015 1.59

in
l im AR6002X 0.917 0.240 0.015 1.58

Pr e
DTIM=10 AR6002GZ/XZ

AR6002G
0.625

0.625
0.077

0.082
0.006

0.006
0.91

0.92

AR6002X 0.625 0.077 0.006 0.91

4.7.1 Measurement Conditions for Low Power CHIP_PWD - all blocks power gated except for
State "Power, Clock Management"
T_amb = 25 ºC HOST_OFF - all blocks power gated except for
All I/O pins except CHIP_PWD_L are "Power, Clock Management", "SDIO", and
maintained at their default polarities. "GSPI."

DVDD12 = AVDD12 = 1.2 V SLEEP - "LF CLK" running; all blocks voltage
scaled or power gated except for "Power, Clock
AVDD18 = DVDD_SDIO = 1.8 V Management", "SDIO", "GSPI", and "GPIO";
internal state is maintained.
DVDD_GPIO0 = DVDD_GPIO1 = DVDD_BT =
DVDD_ANT = VCC_FEM = 3.3 V

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Table 4-14. AR6002 Typical Power Consumption - Continuous Receive Using LNA1
Path (Shared Tx/Rx)

LNA1 Path (Shared Tx/Rx)

[-70 dBm input level]

Current Consumption [mA]

Rate Power Consumption
[Mbps] @1.2 V @1.8 V @3.3 V [mW]
1 63 35 2 146

2 64 35 2 147

5.5 68 35 2 152

11 68 35 2 152

ia l
6 67 35 2 150
n t
9 67 35 2
id e
150

12 68 35 2
n f 152

18 68 35
Co
2 152

s
ero
24 69 35 2 153

36 71

t h 35 2 155

:A
48 72 35 2 156

54

a r
73
y 35 2 158

i n UsingforLNA1
4.7.2 Measurement Conditions

l i m
Continuous Receive

Pr e
T_amb = 25 ºC
DVDD12 = AVDD12 = 1.2 V
AVDD18 = 1.8 V
DVDD_SDIO = DVDD_GPIO0 =
DVDD_GPIO1 = DVDD_BT = DVDD_ANT =
VCC_FEM = 3.3 V

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Table 4-15. AR6002 Typical Power Consumption - Continuous Receive Using LNA2
Path (Separate Rx)

LNA2 Path (Separate Rx)

Current Consumption [mA]

Rate Power Consumption
[Mbps] @1.2 V @1.8 V @3.3 V [mW]
1 64 28 2 134

2 64 28 2 134

5.5 69 28 2 140

11 69 28 2 140

6 67 28 2 138

9 68 28 2 139
ia l
12 68 28 2 139
n t
18 69 28 2 140
id e
24 70 28 2
n f
141

36 71 28 2
Co 143

48 73 28
ro2 s 145

54 73 28
h e 2 145
t
ry :A
4.7.3 Measurement Conditions for
in
Continuous Receive Using LNA2
a
T_amb = 25 ºC
l im
Pr e
DVDD12 = AVDD12 = 1.2 V
AVDD18 = 1.8 V
DVDD_SDIO = DVDD_GPIO0 =
DVDD_GPIO1 = DVDD_BT = DVDD_ANT =
VCC_FEM = 3.3 V

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40 • April 2008 PRELIMINARY: ATHEROS CONFIDENTIAL
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www.DataSheet.co.kr

Table 4-16. AR6002 Typical Power Consumption - Continuous Transmit Using xPA

xPA Current
Consumption Total Power
AR6002 Current Consumption [mA] [mA] Consumption
Rate Target Output Including xPA
[Mbps] Power [dBm] @1.2 V @1.8 V @3.3 V @3.3 V [mW]
1 15 37 51 2 95 456

2 15 37 51 2 95 456

5.5 15 37 51 2 95 456

11 15 37 51 2 95 456

ial
6 15 44 65 2 95 490

nt
9 15 44 65 2 95 490

ide
12 15 44 65 2 95 490

nf
18 15 44 65 2 95 490

24 15 45 65 2
Co 94 488

36 14 45 58

ro s
2 89 459

48 13 45 55
h e 2 83 433

54 11 45
A t 65 2 74 422

ry
4.7.4 Measurement Conditions :
for

T_amb = 25 ºC in a
Continuous Transmit Using xPA

l i m
DVDD12 = AVDD12 = 1.2 V

Pr e
AVDD18 = 1.8 V
DVDD_SDIO = DVDD_GPIO0 =
DVDD_GPIO1 = DVDD_BT = DVDD_ANT =
VCC_FEM = 3.3 V

Atheros Communications, Inc. AR6002 MAC/BB/Radio for Embedded WLAN Applications • 41

PRELIMINARY: ATHEROS CONFIDENTIAL April 2008 • 41
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Table 4-17. AR6002 Typical Power Consumption - Continuous Transmit Without xPA

Target Current Consumption [mA]

Rate Output Power Power Consumption
[Mbps] [dBm] @1.2 V @1.8 V @3.3 V [mW]
1 8 38 108 2 247

2 8 38 108 2 247

5.5 8 38 108 2 247

11 8 38 108 2 247

6 8 47 108 2 258

9 8 47 108 2 258

12 8 47 108 2 258

18 8 47 107 2 256
ia l
n t
24 8 48 107 2
e
257

id
nf
36 7 48 105 2 254

48 6 48 104

Co 2 252

54 4 48 102

ro s 2 248

4.7.5 Measurement Conditions for

h e
Continuous Transmit Without xPA
t
T_amb = 25 ºC
DVDD12 = AVDD12 = 1.2 V
ry :A
AVDD18 = 1.8 V
in a
DVDD_SDIO = DVDD_GPIO0 =

l im
DVDD_GPIO1 = DVDD_BT = DVDD_ANT =

Pr e
VCC_FEM = 3.3 V

42 • AR6002 MAC/BB/Radio for Embedded WLAN Applications Atheros Communications, Inc.

42 • April 2008 PRELIMINARY: ATHEROS CONFIDENTIAL
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5. AC Specifications
5.1 Optional External 32 KHz Input Clock
Timing
Figure 5-1 and Table 5-1 show the external
32 KHz input clock timing requirements.

1/
CK1 CK6

CK7
CK2 CK3

ia l
t
Figure 5-1. Optional External 32 KHz Input Clock Timing Requirements
n
id e
Table 5-1. Optional External 32 KHz Input Clock Timing
n f
Symbol Description Min
Co Typ Max Unit
CK1 Frequency

ro
-
s 32.768 - KHz
CK2 Fall time

h e - - 100 ns
CK3 Rise time

At - - 100 ns
CK4
:
Duty cycle (high-to-low ratio) 15 - 85 %

ary
CK5 Frequency stability –50 - 50 ppm
CK6
in
Input high voltage 0.8*VDD_BT - VDD_BT+0.2 V
CK7
l i m
Input low voltage -0.3 - 0.2*VDD_BT V

Pr e
5.2 External 19.2/24/26/38.4/40/52 MHz
Reference Input Clock Timing
Figure 5-2 and Table 5-2 show the external
19.2/24/26/38.4/40/52 MHz reference input
clock timing requirements.

1/
CK1 CK6

CK7
CK2 CK3

Figure 5-2. External 19.2/24/26/38.4/40/52 MHz

Atheros Communications, Inc. AR6002 MAC/BB/Radio for Embedded WLAN Applications • 43

PRELIMINARY: ATHEROS CONFIDENTIAL April 2008 • 43
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Table 5-2. External 19.2/24/26/38.4/40/52 MHz Reference Input Clock Timing

Symbol Description Min Typ Max Unit
CK2 Fall time - - 0.1 * ns
period
CK3 Rise time - - 0.1 * ns
period
CK4 Duty cycle (high-to-low ratio) 40 - 60 %
CK5 Frequency stability -20 - 20 ppm
CK6 Input high voltage 1.14 - 3.46 V
CK7 Input low voltage -0.1 - 0.3 V

5.3 SDIO/GSPI Interface Timing

Figure 5-3 shows the write timing for a SDIO/
ia l
GSPI style transaction.
n t
id e
fP P
n f
Clock t WL
CotWH VIH
t THL
s
t TLH VIL

ero
t ISU tIH
VIH
Input
t h VIL

:A
ary
VOH
Output
VOL

in
shaded areas not valid
tO_DLY (max) t O_DLY (min)

l i m
Pr e
Figure 5-3. SDIO/GSPI Timing

44 • AR6002 MAC/BB/Radio for Embedded WLAN Applications Atheros Communications, Inc.

44 • April 2008 PRELIMINARY: ATHEROS CONFIDENTIAL
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Table 5-3 shows the values for timing

constraints for SDIO.

Table 5-3. SDIO Timing Constraints

Parameter Description Min Max Unit Note

fPP Clock frequency data transfer mode 0 25 MHz 100 pF ≥ CL (7 cards)
tWL Clock low time 10 - ns 100 pF ≥ CL (7 cards)
tWH Clock high time 10 - ns 100 pF ≥ CL (7 cards)
tTLH Clock rise time - 10 ns 100 pF ≥ CL (10 cards)
tTHL Clock fall time - 10 ns 100 pF ≥ CL (7 cards)
tISU Input setup time 5 - ns 25 pF ≥ CL (1 card)
tIH Input hold time 5 - ns 25 pF ≥ CL (1 card)
tO_DLY (min) Output delay time during data transfer mode 0 14 ns

ia l
25 pF ≥ CL (1 card)
tO_DLY (max) Output delay time during identification mode 0 50 ns
n t 25 pF ≥ CL (1 card)

id e
n f
Co
ro s
h e
At
ry :
in a
l i m
Pr e

Atheros Communications, Inc. AR6002 MAC/BB/Radio for Embedded WLAN Applications • 45

PRELIMINARY: ATHEROS CONFIDENTIAL April 2008 • 45
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Table 5-4 shows the values for timing

constraints for GSPI.

Table 5-4. GSPI Timing Constraints

Parameter Description Min Max Unit

fPP Clock frequency 0 48 MHz
tWL Clock low time 8.3 - ns
tWH Clock high time 8.3 - ns
tTLH Clock rise time - 2 ns
tTHL Clock fall time - 2 ns
tISU Input setup time 5 - ns
tIH Input hold time 5 - ns
tO_DLY Output delay 0 5 ns

ia l
n t
id e
n f
Co
ro s
h e
At
ry :
in a
l i m
Pr e

46 • AR6002 MAC/BB/Radio for Embedded WLAN Applications Atheros Communications, Inc.

46 • April 2008 PRELIMINARY: ATHEROS CONFIDENTIAL
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6. Pin Descriptions
This section contains a listing of the signal The following nomenclature is used for signal
descriptions (see Table 6-1 for the BGA types described in Table 6-2:
package pin outs).
The following nomenclature is used for signal IA Analog input signal
names:
I Digital input signal
NC No connection should be made to
I, H Input signals with weak internal
this pin
pull-up, to prevent signals from
floating when left open
_L At the end of the signal name,
indicates active low signals
I, L Input signals with weak internal
pull-down, to prevent signals
P At the end of the signal name,
from floating when left open
indicates the positive side of a
differential signal
I/O A digital bidirectional signal
N At the end of the signal name
ia l
indicates the negative side of a
I/O/L

n t
A digital bidirectional signal,
with a weak internal pull-down
differential signal
OA
id e
An analog output signal

n f
Co
O A digital output signal

r
P
o s A power or ground signal

h e
A t
r y:
m ina
l i
P re

Atheros Communications, Inc. AR6002 MAC/BB/Radio for Embedded WLAN Applications • 47

PRELIMINARY: ATHEROS CONFIDENTIAL April 2008 • 47
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Table 6-1. BGA Package Pinout

1 2 3 4 5 6 7 8 9 10 11 12 13
RF2 RF2 RF2IN VDD18_ VDD12_ BT_CLK
A AGND RF2INP PDET NC NC XTALI XTALO
OUTN OUTP N BIAS XTAL _OUT

VDD18_ VDD12_ VDD12 BIAS VDD12D VDD12_ VDD18_ BT_CLK

B RF5INP AGND NC NC DVDD12
FE LNA _BIAS REF _SYN BB XTAL _EN

VDD12_
C RF5INN AGND AGND AGND AGND AGND GPIO17 GPIO16
FE

PA5
D NC GPIO14 GPIO15
BIAS

RF5 VDD18_ DVDD_ DVDD_

E AGND AGND AGND AGND AGND DVSS
OUT VCO GPIO1 GPIO0

VDD12_ VDD12_
F AGND AGND AGND AGND AGND DVSS DVSS GPIO12 GPIO13
TX5 SYNTH

ial
XPA XPA
G AGND AGND AGND AGND AGND DVSS DVSS GPIO10 GPIIO11
BIAS2 BIAS5

H
VCCFE
M
LDO_
OUT
AGND AGND AGND AGND AGND DVSS
n tDVSS GPIO9 DVDD12

e
fid
VDDIO_ CLK_
J ANTA AGND DVSS DVSS DVSS DVSS DVSS DVSS DVDD12
ANT REQ

K ANTC ANTB
o n SYS_ CHIP_

sC
RST_L PWD_L

DVDD_

ro
L ANTD ANTE DVSS DVSS DVSS DVSS DVSS DVDD12
SDIO

M AGND GPIO0 GPIO2 DVDD12 GPIO4 GPIO6

h eGPIO8 TMS TCK TDO
SDIO_ SDIO_ SDIO_

DVDD_
At DVDD_ DVDD_
DATA3

SDIO_
DATA2

SDIO_
CLK

SDIO_
N DVDD12 GPIO1 GPIO3
BT

ry :
GPIO5 GPIO7
SDIO
DVDD12 TDI
SDIO CMD DATA1 DATA0

in a
i m
Table 6-2. Signal to Pin/Bump Mapping
l
Pr e
BGA CSP Source or External PAD Description
Symbol Pin Bump Type Destination Power Supply
Radio
ANTA J1 4 O Antenna VDD_ANT Control signal for RF
front end components
ANTB K2 13 O Antenna VDD_ANT Control signal for RF
front end components
ANTC K1 3 O Antenna VDD_ANT Control signal for RF
front end components
ANTD L1 12 O Antenna VDD_ANT Control signal for shared
antenna switch
ANTE L2 2 O Antenna VDD_ANT Control signal for RF
front end components
BIASREF B6 35 IA - Reference for internal
analog biasing
PDET A6 55 IA Power - External power detector
detector input
RF2INN A5 37 IA RF input - 2.4GHz RF input
RF2INP A4 29 IA RF input - 2.4GHz RF input

48 • AR6002 MAC/BB/Radio for Embedded WLAN Applications Atheros Communications, Inc.

48 • April 2008 PRELIMINARY: ATHEROS CONFIDENTIAL
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Table 6-2. Signal to Pin/Bump Mapping (continued)

BGA CSP Source or External PAD Description
Symbol Pin Bump Type Destination Power Supply
RF2OUTN A2 10 OA RF output - 2.4GHz RF output
RF2OUTP A3 20 OA RF output - 2.4GHz RF output
RF5OUT E1 7 OA RF output - 5GHz RF output on
AR6002X, NC on
AR6002G
RF5INN C1 8 IA RF input - 5GHz RF input on
AR6002X, NC on
AR6002G
RF5INP B1 9 IA RF input - 5GHz RF input on
AR6002X, NC on
AR6002G
XPABIAS2 G1 5 OA Analog output - Bias voltage for 2GHz
external PA
XPABIAS5 G2 6 OA Digital output -
l
Bias voltage for 5GHz

a
external PA on AR6002X,
i
t
NC on AR6002G

n
Clock
CLK_REQ J12 99 O - DVDD_SDIO
id e
Reference clock request

n f signal
XTALI A11 85 Crystal
Input
40 MHz
crystal
-

C o Reference crystal
interface signal
XTALO A12 86 Crystal
Output
40 MHz
crystal or
ro
-
s Reference crystal
interface signal or

source
h e
external clock external reference clock
input

A t
Digital Control (BT_ACTIVE, BT_FREQ, BT_PRIORITY, and RX_CLEAR are now mux’d with the GPIO signals)
SYS_RST_L K12 98 IH
r y: - DVDD_SDIO Full chip reset input

ina
CHIP_PWD_L K13 89 I - DVDD_SDIO Chip power down input
BT_CLK_EN B12 96 I AVDD18 Input enable signal for
reference clock output
BT_CLK_OUT A13
l im 105 O - Buffered reference clock

re
output

P
I2C (I2C_SCLO and I2C_SDAO now mux’d with the GPIO signals)
UART (RXDO, RXDO, UART_CTS_L and UART_RTS_L now mux’d with the GPIO signals)
GSPI Master (SPI_CK, SPI_CSO_L, SPI_MISO, and SPI_MOSI now mux’d with the GPIO signals)
SDIO
SDIO_CLK M13 88 I - DVDD_SDIO Also GSPI clock
SDIO_CMD N11 67 I - DVDD_SDIO Also GSPI MOSI
SDIO_DATA_0 N13 97 I/O - DVDD_SDIO Also GSPI MISO
SDIO_DATA_1 N12 87 I/O - DVDD_SDIO Also GSPI host interrrupt
SDIO_DATA_2 M12 77 I/O - DVDD_SDIO -
SDIO_DATA_3 M11 78 I/O - DVDD_SDIO Also GSPI CS
GSPI Slave: GSPI pins are MUXed with SDIO pins
GPIO
GPIO0 M2 22 I/OL - DVDD_BT BT_PRIORITY for
Bluetooth coexistence

Atheros Communications, Inc. AR6002 MAC/BB/Radio for Embedded WLAN Applications • 49

PRELIMINARY: ATHEROS CONFIDENTIAL April 2008 • 49
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Table 6-2. Signal to Pin/Bump Mapping (continued)

BGA CSP Source or External PAD Description
Symbol Pin Bump Type Destination Power Supply
GPIO1 N2 31 I/OL - DVDD_BT WLAN_ACTIVE for
Bluetooth coexistence
GPIO2 M3 11 I/OL - DVDD_BT BT_FREQUENCY for
Bluetooth coexistence
GPIO3 N3 1 I/OL - DVDD_BT BT_ACTIVE for
Bluetooth coexistence
GPIO4 M5 21 I/OL - DVDD_SDIO SDIO/GSPI interface
select
GPIO5 N5 30 I/OL - DVDD_SDIO SDIO/GSPI interface
select
GPIO6 M6 39 I/OL - DVDD_SDIO -
GPIO7 N6 49 I/OL - DVDD_SDIO TRST for JTAG debug
interface
GPIO8 M7 38 I/OL - DVDD_BT
a l
Optional external 32kHz
i
GPIO9 H12 100 I/OL — DVDD_GPIO0
n t
clock input
I2C SCL or SPI clock
GPIO10 G12 90 I/OL — DVDD_GPIO0
id e
I2C SDA or SPI MISO
GPIO11 G13 101 I/OL —
f
DVDD_GPIO0
n
UART RXD or SPI MOSI
GPIO12
GPIO13
F12
F13
91
102
I/OL
I/OL
—
—
Co
DVDD_GPIO0
DVDD_GPIO0
UART TXD or SPI CS_L
Reset input for JTAG
s interface

ero
GPIO14 D12 94 I/OL — DVDD_GPIO1 UART CTS
GPIO15 D13 103 I/OL
t h
— DVDD_GPIO1 UART RTS

:A
GPIO16 C13 95 I/OL — DVDD_GPIO1 -
GPIO17 C12 104 I/OL — DVDD_GPIO1 -

ry
Digital Test (EJTAG_SEL and TRST_L are Mux’d with the GPIO Signals)
a
in
TCK M9 59 IH — DVDD_SDIO JTAG TCK input
TDI N9 58 IH — DVDD_SDIO JTAG TDI input
TDO
l i m
M10 68 OL — DVDD_SDIO JTAG TDO output

Pr e
TMS M8 48 IH — DVDD_SDIO JTAG TMS input

Table 6-3. Pin/Bump Mapping for Power

Supplies
Symbol BGA Pin CSP Bump Type Voltage Description
Power
DVDD12 N1,M4,N8, 24, 32, 40, 80, P Digital 1.2V core supply
L12,J13,H13, 81, 82, 83
B13
VDD12_SYNTH F2 25 P Analog 1.2V core supply
VDD12_TX5 F1 26 P Analog 1.2V core supply
VDD12_FE C2 27 P Analog 1.2V core supply
VDD12_LNA B4 45 P Analog 1.2V core supply
VDD12D_SYN B9 66 P Analog 1.2V core supply

50 • AR6002 MAC/BB/Radio for Embedded WLAN Applications Atheros Communications, Inc.

50 • April 2008 PRELIMINARY: ATHEROS CONFIDENTIAL
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Symbol BGA Pin CSP Bump Type Voltage Description

VDD12_XTAL A10 75 P Analog 1.2V core supply
VDD12_BIAS B5 - P Analog 1.2V core supply
VDD12_BB B10 64, 76 P Analog 1.2V core supply
VDD18_FE B3 28 P Analog 1.8V I/O supply
VDD18_VCO E2 34 P Analog 1.8V I/O supply
VDD18_BIAS A9 65 P Analog 1.8V I/O supply
PA5BIASP D1 17 P Analog 1.8V I/O supply
VDD18_XTAL B11 84 P Analog 1.8V I/O supply
DVDD_SDIO N7,N10,L13 50, 69, 79 P SDIO I/O supply
DVDD_GPIO0 E13 92 P GPIO0 I/O supply
DVDD_GPIO1 E12 93 P GPIO1 I/O supply
DVDD_BT N4 23 P BT coexistence I/O supply
l
Bluetooth Coexistence

ia
I/O Supply
VCC_FEM H1 33 P Battery voltage LDO input
n t
Battery Voltage LDO

id e input (output is 3.0 V on

LDO_OUT)
VDD_ANT J2 14 P
n f
Antenna control I/O supply Antenna bias and

C o control (can be tied to

LDO_OUT)
s
ero
LDO_OUT H2 15 P Battery voltage LDO output LDO output (input is
VCC_FEM)
DVSS J5,L5,J6,L6, 41, 51, 60, 70, P
th Digital ground Digital Ground
J7,L7,J8,L8,
J9,L9,E9,F9,
71, 72, 73

: A
G9,H9,F11,
r y
ina
G11,H11,J11
AGND E5,F5,G5,H5, 42, 43, 44, 52, P Analog ground Analog Ground

l im
E6,F6,G6,
H6,E7,F7,G7,
53, 54, 61, 62,
63

P re
H7,E8,F8,
G8,H8,E3,F3,
G3,H3,J3,
M1,C5,C6,
C7,C8,C9,B2,
A1

Reserved Bumps
NC A7, A8, B7, B8 46, 47, 56, 57 RES — NOTE: For AR6002GZ,
bumps 6-8 are also No
Connect (NC).

Atheros Communications, Inc. AR6002 MAC/BB/Radio for Embedded WLAN Applications • 51

PRELIMINARY: ATHEROS CONFIDENTIAL April 2008 • 51
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ia l
n t
id e
n f
Co
ro s
h e
At
ry :
in a
l i m
Pr e

52 • AR6002 MAC/BB/Radio for Embedded WLAN Applications Atheros Communications, Inc.

52 • April 2008 PRELIMINARY: ATHEROS CONFIDENTIAL
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7. Package Dimensions ■ 7 x 7 mm, 0.5 mm pitch BGA or

■ 0.4 mm pitch WLCSP package information
BGA Dimensions available separately

The BGA drawing and measurements are

provided in Figure 7-1 and Table 7-1. The
AR6002 family is available in:

ia l
n t
id e
n f
Co
ro s
h e
At
ry :
in a
l i m
Pr e

Figure 7-1. BGA Drawing 7 x 7 mm Package

Atheros Communications, Inc. AR6002 MAC/BB/Radio for Embedded WLAN Applications • 53

PRELIMINARY: ATHEROS CONFIDENTIAL April 2008 • 53
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Table 7-1. BGA Dimensions

Dimension Label Min. Nom. Max. Unit. Min. Nom. Max. Unit.
A --- --- 1.00 mm --- --- 0.039 inches
A1 0.16 0.22 0.28 mm 0.006 0.009 0.011 inches
A2 0.61 0.67 0.72 mm 0.024 0.026 0.028 inches
c 0.17 0.21 0.25 mm 0.007 0.008 0.010 inches
D 6.90 7.00 7.10 mm 0.272 0.276 0.280 inches
E 6.90 7.00 7.10 mm 0.272 0.276 0.280 inches
D1 --- 6.00 --- mm --- 0.236 --- inches
E1 --- 6.00 --- mm --- 0.236 --- inches
e --- 0.50 --- mm --- 0.020 --- inches

ial
b 0.25 0.30 0.35 mm 0.010 0.012 0.014 inches

nt
aaa 0.10 mm 0.004 inches

ide
bbb 0.10 mm 0.004 inches
ddd 0.08 mm 0.003 inches
eee 0.15 mm
n f
0.006 inches
fff 0.05 mm
Co 0.002 inches

s
ero
MD/ME 13/13 mm 13/13 inches

Notes:
1. Controlling dimension: Millimeters.
t h
:A
2. Minimum clearance of 0.25mm between edge of solder ball and body edge.

a ry
m in
l i
Pr e

54 • AR6002 MAC/BB/Radio for Embedded WLAN Applications Atheros Communications, Inc.

54 • April 2008 COMPANY CONFIDENTIAL
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8. Ordering Information
The AR6002 may be ordered as follows:
■ AR6002G-AC1E (802.11b/g BGA)
■ AR6002GZ-BF1E-R (802.11b/g WLCSP)
■ AR6002X-AC1E (802.11a/b/g BGA)
■ AR6002XZ-BF1E-R (11a/b/g WLCSP)

ia l
n t
id e
n f
Co
ro s
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At
ry :
in a
l i m
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Atheros Communications, Inc. AR6002 MAC/BB/Radio for Embedded WLAN Applications • 55

PRELIMINARY: ATHEROS CONFIDENTIAL April 2008 • 55
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The information in this document has been carefully reviewed and is believed to be accurate. Nonetheless, this document is subject to
change without notice. Atheros assumes no responsibility for any inaccuracies that may be contained in this document, and makes no
commitment to update or to keep current the contained information, or to notify a person or organization of any updates. Atheros reserves
the right to make changes, at any time, to improve reliability, function or design and to attempt to supply the best product possible.

Document Number: 981-00059-001 MKG-0492 Rev. 4

Atheros Communications, Incorporated

5480 Great America Parkway
Santa Clara, CA 95054
t: 408/773-5200
f: 408/773-9940
www.atheros.com

COMPANY CONFIDENTIAL
Subject to Change without Notice

Datasheet pdf - http://www.DataSheet4U.net/