THE SIMULATION OF 6502 MICROPROCESSOR By: Alireza Kobari B.S. in Physics, Pars College; Tehran, Iran, 1978 Submitted to the Graduate Feculty in partial fulfillment of the requirement for the degree of Master of Science in Electrical Engineering Florida Institute of Technology 1981 The author grents permission to reproduce single copies : banAlireza Kobari Electrical Engineering Department ak ie Title: The Simulation of 65%2 Microprocessor Major Advisor: Mr, D. Gluntz ASM65 and KO65 are software programs written in BASIC- PLUS language end run on a PDP=11/34 computer. The ASM65 is an assembler and K065 is a simulator, ASM65 allows the user to create the 6542 assembly language source program, The system is equipped with helpful _ error messages, KO65 simulator will execute the 6502 operation code which is generated by the assembler. The simulator also allows the user to easily debug his program through features such as: tracing, single-stepping, and breakpoint. 77692 FLORIDA INSTITUTE OF TECHNOLOGY LIBRARYACKNOWLEDGEMENT The author would like to take this opportunity to express his sincere appreciation to his major advisor, Douglas Gluntz, for his support, guidance, and helpful sug- gestions during the preparation of this thesis. He would also like to express his, sincere appreciation to the other members of the oral examination committee, Dr. John Hadjilogiou, and Dr. J, Choi for their comments and sug- gestions. In addition, the author is indebted to Ms. Michel Serrano and Mr, Augustine Walter for their constructive suggestions and cooperation. Finally, a special note of thanks to Mrs. Carolyn Gatzulis for the neat typing of this manuscript. A. Kobari Florida Institute of Technology August, 1981TABLE OF CONTENTS PAGE NO. CHAPTER TI. INTRODUCTION ......ecceccecscceeces 1 II. 6582 MICROPROCESSOR AND PERIPHERAL DEVICE (6520) secsecceccsecessesers III. SIMULATOR SYSTEM (KO65) ........0e 24 IV. USER'S GUIDE FOR ASM65-K065 SYSTEMS se... - 33 vw CONCLUSIONS . Seeeeenees 55 APPENDIX A, 6502 ASSEMBLER CONVENTION ......... 56 APPENDIX B. ERROR MESSAGES 1. essecesessessssoee 63 APPENDIX ©, K065 and ASM65 PROGRAM LISTING .... 68 REFERENCES erereesy teeee 94CHAPTER I INTRODUCTION 4.4 BACKGROUND an assembly lengusge allows the user to be directly related to the hardware of a given computer, In addition to allowing the user to exploit the structure of the computer in developing efficient software, essembly languages also serve as an educational tool for a beginner to get acqueint- ed with the herdware of a given computer system. The suthor's experience with smell machines had indicated that running assembly language progrems on mini and microcomputers without well defined support software libraries, requires considerable insight into the hardware of the computer system being used. Lack of support software can prove extremely frustrating to the beginner who wishes to use assembly language in a small computer system.” The development and debugging of software for new processor-based systems is frequently done with the aid of a simulator, which is s program ‘running on a host computer having the property of simulating the instruction set and the programming model of the new or target processor. after the software is initially debugged using the simulator, further debugging of the software system is done with the aid of debug programs and various software facilities thatprovide breakpoint, single-stepping, and other capsbilities. A simlator of a microcomputer system that runs on a large machine has basic advantages. The large system should have extensive software support, In ill-configured micro- computer systems, hardware problems could cause programming errors. However, in the case of a simulator, if a user's program does not work, it is due to a programming error and not the fault of the host computer. Further, a good simula- tor possesses debug features that even the real microcom- puter system does not support. With the introduction of microprocessor development systems, a new tool has been made availeble to the designer in the form of the microprocessor simulator. Today's simulators combine many powerful software development tools into one convenient, easy-to-use system and greatly facili- tates the process of integrating the hardware end software components of newly developed microprocessor-based systems. The advantages of using a simulator include the ability to load the newly developed programs into the simulation memory and execute these programs in the develop- ment eycle. It also includes the ability to debug software under controlled conditions as it can run, halt, end single- step the processor as well es examine the register and memory contents. 4.2 OBJECTIVE The objective of this thesis is to simulate the 6502microprocessor using the BASIG-PLUS language software of the PDP-11/34, It will help users run 6582 assembly language by first creating the assembly source program in EDIT mode. The assembler, ASM65', will convert the assembly program to machine language and the simulator, K065, will execute the program, This feature will allow users to debug and study their programa. The ASM65 and KO65 software programs are written in BASIC-PLUS language and are compatible, with some modifice- tion, to any computer which has a BASIC interpreter and enough memory space. The interactive time sharing system RSTS/E operating system on PDP-11 model 34 was used for this design. The author used the EDIT software progran that already exists in the PDP-11 minicomputer as a matter of convenience and to increase the capability of debugging the source program. Thus, the user can easily create his pro- gram and in case of any error during assembly time he can correct the program, using EDIT mode. ASM65 is an assembler that has been modified due to the different BASIC Interpret- er of the PDP-11/34, The error messages have also been designed to inform the user of all syntax errors at the end of assembly time. The user will then go back to the ZDIT mode for error correction. The last part of this system is 1 copyright Sybex, Inc. Referenced with kind permission4 the KO65, which is » simulator. The simulator is a program which can accept different commands, such as: displey register and memory contents, single-step the program, etc., in order to execute the 6592 microprocessor instruction set.CHAPTER IT 6502 MICROPROCESSOR AND PERIPHERAL DEVICE (6520) 2.1 INTRODUCTION The past several yeers have seen the development of an exciting new concept in electrical design. The micro- computer started out as a relatively simple, difficult-to- use, programmable device capable of hendling simple control or computations) problems. However, it has since matured into 2 powerful, inexpensive, easy-to-use device capable of controlling all but the most complex of systems. Conventional system design is rapidly being revolu- tionized by the component that forms the heart of the micro- computer---the large scale, single-chip, programmable microprocessor (CPU), The success of the microprocessor is based on the fact that it permits the design engineer and programmer to apply their expertise in solving a multitude of design problems, A small number of lerge integrated circuits can be configured to solve design problems from the simplest to the most complex. 2.2 SIGNAL LINES Figure 2-1 summarizes the pinouts of the 6582 cPU. These pins and their uses in microcomputer systems are discussed separately below.2.2.1 ADDRESS BUS (AB@S-AB15) The Address Bus buffers on the 6582 microprocessor sre push/pull type drivers cepable of driving at least 130 PF and one standard TTL load. vss ——ie Roy ——» ——> 6, our @, our + +~—s0. — ~— 9,1 Ne. No. i ——> Ne. sync +——— ——> aw vee . 3 ‘e0 Bo . 2 a1 Bt ° ” 082 sz " om x» psa 83 ” 2h (~~ oes Aga 7 = pes ABs “ z 086 a8 1s = 087 ae7 " s ‘A818 age ” » Aas ase ” 2d (ass Ago ® 2 agi asi 2 x vss N.C. = Ne connection Figure 2-1 6502 Pinout Designation The addressing technique involves putting an address on the Address Bus which is known to be either in program sequence, on the same page in program memory, or st a known point in RAM. The address is valid 300 ns (at 1 MEZ clock rate) into the #1 clock pulse and remains stable until the next1 pulse. 2.2.2. DATA BUS (DB-DB7) All instruction and data transfers between the pro- cessor and memory take place over the bidirectional data lines. The buffers driving the data bus lines heve full "three-state" capability. Each data bus pin is connected to an input and an output buffer, with the output buffer remaining in the "floating" condition except when the processor is trans- ferring date into or out of one of the support chips. 2.2.3 READ/WRITE (R/W) The read/write line allows the processor to control the direction of data transfer between the processor and the support chips e.g, memory (ROM, RAM), I/O interface, etc. This line is high except when the processor is writing to menory or to a peripheral interface device. 2.2.4 READY (RDY) The RDY input delays execution of any cycle during which the RDY line is pulled low. . The primary purpose of the RDY line is to delay execution of a program fetch eyele until data are available from memory. The RDY function will not stop the processor in a cycle in which a WRITE operation is being performed.2.2.5 NON-MASKABLE INTERRUPT (WMT) The MAT input, when in the interrupted state, always interrupts the processor after it completes the instruction currently being executed, This interrupt is not “markable ©-8+, there is no way for the processor to prevent recogni- tion of the interrupt, The NMI input responds to a negative transition, The NMI signal must ve low for at least two clock cycles for the interrupt to be recognized, whereupon, new program count vectors are fetched, 2.2,6 INTERRUPT REQUEST (IRQ) The interrupt request (IRQ) responds in much the same manner as NMI. However, this function can be enabled or disabled by the interrupt inhibit bit in the processor status register, As long as the I flag (interrupt inhibit flag) is a logic 1, the signal on the TRO pin will not affect the processor. The TRG pin is not edge-sensitive. Instead, the Processor will be interrupted as long as the I flag is a logic "0" and the signal on the IRQ input is at GND. Because of this, the TRO signal mist be held low until it is recognized. To assure that the processor will not rec- ognize: the interrupt more than once, the I fleg is set automatically during the last machine cycle before the processor begins executing the interrupt software, begin- ning with the fetch of progrem count.2.2.7 RESET (RES) The RES line is used to initialize the microprocessor from a power-down condition. It may also be used to reset the system after power-up time. During the power-up time this line is held low internally, and writing from the micro~ processor is inhibited. When the line goes high, the micro- processor will delay 6 cycles and then fetch the new program count vector from specific location in memory. This is the start of the user's code, 2.2.8 SYNCHRONIZATION SIGNAL (SYNC) In the 6592, a SYNC signal is provided to identify those cycles in which the processor is doing an Opcode fetch, The SYNC line goes high during phase 1 clock pulse of an Opeode fetch end stays high for the remainder of that cycle. 2.2.9 SET OVERFLOW (S.0.) This pin sets the overflow flag on a negative tran- sition from TL one to TTL zero, This is designed to work with a future 1/0 part and should not be used in nommal applications. 2.2.10 POWER LINES (Vec, Vss) The Vee and Vss pins are the only power supply con- nections to the chiv, The supply voltage is + 5.0V DC + 5%, 2.3 FUNCTIONAL FEATURES OF THE 6502 MICROPROCESSOR10 A block diagram of the basic architecture is shown in Figure 2-2. This section begins with an enalysis of this dlock diagram, discussing the function of the various regis- ters, data paths, etc, A detailed discussion of the opera- tion of the various pins on the chip has been described. The internal organizetion of the processor can be split into two sections, In general, the instructions obtained from program memory ere executed by implementing a series of data transfers in one section of the chip (register section). The control lines which actually cause the data transfers to teke Place are generated in the other section (control section), Instructions enter the processor on the data bus, are latched into the instruction register, and are then decoded along with timing signels to generate the register control signals. The timing control unit keeps track of the apecific cycle being executed. This unit is set to "T" for each instruction fetch cycle and is advanced st each phase one clock pulse. Hach instruction starts in "?9" and goes to 71, 2,13, ete, for as many cycles as are required to complete execution of the instruction. Esch data transfer, etc., which takes place in the register section is caused vy decoding the contents of both the instruction register and the timing counter, Additional control lines which affect the execution of the instructions are derived from the Interrupt logic and from the Processor Status register. ‘The Interrupt logic4 ——-nrastin sterion comin section ema a Weae mb wmermucien Loe} euitSaion [S885 ‘ea Soren eaten irene Figure 2-2 6592 Internal architecture controls the processor interface to the interrupt imputs to assure proper timing, enabling, sequencing, etc. which the processor recognizes and services.42 The Processor Status register contains a set of latches which serve to control certain aspects of the pro- cessor arithmetic and logic operations, and to indicate the status of data either generated by the processor or trans- ferred into the processor from outside. Since the real work of the processor is carried on in the register section of the chip, a detailed study will be made of this section. It comprises the following com- ponents: * Data Bus Buffers * Input Data Latch (DL) * Program Counter (PCL,PCH) * Accumulator (A) * Apithmetic Logic Unit (ALU) * stack Pointer (Ss) * Index Registers (X,Y) * Address Bus. Latches (ABL, ABH) * Processor Status Register (P) Figure 2-3 summarizes the Processor Programming Model for the 6542. a acer TTF otrmeasren + 2 ' mdaeadead | | CU imooisase ve orsaace CSF met Co on COEF secre Preston shoe Figure 2-3 Programming Model 650213 At 1 MHZ, the data which goes into the processor from the progrem memory, the data memory, or from peripheral Gevices, appear on the data bus during the last 100 ns of phase 2 clock pulse. No attempt is made to actually operate on the data during this short period, Instead, it is simply transferred into the input data latch for use during the next eycle. The data latch serves to trap the data on the data bus during each phase 2 clock pulse, The data can then be transferred onto one of the internal busses, and from there into one of the internal registers. If an arithmetic or logic operation is to be performed, using the data from memory and the contents of the accumulator, data at the inpat data latch will be transferred onto the internal data bus as previously described. From there it will be trans- ferred into the ALU. At the same time, the contents of the accumlator will be transferred onto a bus in the register section and from there into the second input to the ALU. The results of the arithmetic or logic operation will be transferred beck to the accumulator on the next machine cycle by trensferring first onto the bus and then into the accumulator, All of these data transfers teke place during the phase 1 clock pulse, The program counter (PCL,PCH) provides the addresses Which step the processor through sequential instructions in the program. Each time the processor fetches an instruction from program memory, the contents of PCL are placed on’ the low-order 8 bits of the address bus and the contents of PCH14 are placed on the high-order 8 bits. This counter is incre- mented each time an instruction or data is fetched from program memory. The Accumlator is a general-purpose 8 bit register which stores the results of most arithmetic and logic opera- tions. In addition, the Accumulator usually contains one of the two data words used in these operations. ‘Siac Poin sx sta Src sty ed Tay, ae Pu tau niv| [efolifzle Figure 2-4 6502 Data Path : All logic and arithmetic operations take place in the ALU; this includes incrementing and decrementing of internal registers (except PCL and PCH). However, the ALU cannot store data for more than one machine cycle; if data are placed on the inputs to the ALU at the beginning of one cycle, the result is always gated into one of the storage registers or to external memory during the next machine cycle. Each bit of the ALU has two inputs. These inputs15 can be tied to various internal busses or to a logic zeros the ALU then generates the SUM, AND, OR, BTC. function using the data on the two inputs. The Stack Pointer (S) and two Index Registers (X and ¥) each consist of 8 simple latches. These registers store data which are to be used in calculating addresses in date memory, The date path of the 6592 is given in Figure 2-4, The Address Bus Buffers (ABL,ABH) consist of a set of latches end also TTL compatible drivers. These latches store the addresses which are used in accessing the periph- eral devices (ROM,RAM, and I/O). 2.4 DEVICE TIMING (TIME-BASE GENERATION) The 6592 can be used with en externally generated time base consisting of either a TTL-level single-phase clock, crystal oscillator, or RC network. Figures 2.5, 6 end 7 show the configuration for set--. ting the frequency of oscillation with a crystal or with an RC network, 7404 2” SYSTEM @, Pin 37 Qin 6502 Di cove 39 Op out Figure 2-5 6592 Parallel Mode Crystal Controlled Oscillator7408 SYSTEM 9, 2 ow 6502 v Figure 2~6 6592 Series Mode Crystal Controlled Oscillator SYSTEM 0, in out Figure 2-7 6582 Time Base Generator-RC Network 2.5 INSTRUCTION SET Table 2-1 is a summery of the 6562 Instruction Set in alphabetical order. 1617 TABLE 2-1 6592 MICROPROCESSOR INSTRUCTION SET ALPHABETIC SEQUENCE ‘ADC Add Mery o Accumulator with Camry JS Sompto.New Location Saving Return Addces8 AO. “AND” Memory with Accumulator ‘ASL Shift Lt One Bit (Memory or Accumalator) LOA Load Accumulator with Memory LOK Load index X with Merry Branch on Carry Gear LOY Load Index ¥ with Memory Branch on Cay Set SR. Shift Right One Bit (Memory or Accumulator) Branch on Reslt Zero ‘Tes Bitsin Memory with Accumulator NOP_No Operation ch on Reslt Minus ranch on Reselt not Zero ORA “OR” Memory with Accumator Branch on Result Pies Force Bresk BVC Branch on Overflow Clear Push Processor Status on Stick BVS Branch on Ovesflow Set PLA Pull Accumulator from Stack PLP Pull Processor Status from Stack GLC Gene Carry Fig CLD Gest Decimal Mode ROL Rotate One Bit Left (Memory of Accumulator) CLE Gear Interrupt Disable Bit Rot CLV. Glee Orfow Flag [EMP Compare Memory and Accumulator ‘CPX Compare Memory and Index X GPY Compute Memory and Index Y SBC Subsract Memory fom Accumlator with Borrow SEC Set Carry Fag SED Set Decimal Mode DEC Decrement Memory by One SEI Set tnterupt Disable Status BEX Decrement laden X by One STA. Store Accumulator in Memory DEY Decrement index ¥ by One STX Store ladex X in memory SEY Store index ¥ ia memory OR “Exclusv-O7" Memory with Accumulator ‘TAX Transfer Accumulator to tndex X INC Incremeat Neary by One TAY Teanser Accumulator o index Y INX Increment Index X by One TSX Transfer Stack Pointer to Index X INY Increment index ¥ by One THA Transfer Index X to Accumulator ‘TXS Tearser Index X to Stack Pointer IMP Jump toNew Lovation TVA Transfer index ¥ 0 Accumulator 2.6 6520 PERIPHERAL INTERFACE ADAPTER (PTA) The 6520 is a versatile I/O chip which is celled a Peripheral Interface Adapter, or PIA. It acts es an inter face between the microprocessor and peripherals such as printers, displays, keyboards, etc. The prime function of the 6520 is to respond to stimuli from each of the two worlds it is serving, On the one side, the 6520 is interfacing with peripherals via to 8 bit bidirectional peripheral data parts. On the other side, the device interfaces with the micropro-18 cessor through an 8 bit data bus, It is, therefore, simplest to view the basic function of the 6520 using Figure 2-8. In addition to the lines described, the 6520 provides four inter- rupt input/peripheral control lines and the logic necessary for simple, effective control of peripheral interrupts. I= cowraon, tor haw ota tus Kosher] senenennn sacnormocessons tener nee mates. por | DSMAYS, ere ‘conrrot. <—>} K—> oata vor —— Figure 2-8 6520 Interface Diagram Figure 2-9 shows the 6520 pinout designations for the Pe- ripheral Interface Adapter. Tne functionel configuration of the 6520 is pro- gramned by the microprocessor during system initialization. Hach of the peripheral date lines is progremmed to ect as an input or output, and each of the four control/interrupt lines may be programmed for different possible control modes. This allows a high degree of flexibility in the overall operation of the interface. Some of the more important features of the 6520 arevss q Pao = (3 aa dq PAS q Pas dq os d Pas m= 49: =) P20 a x oz Pez ” at (7 04 Pea 2 ™ os poe “ » 06 Pas ds * o7 Pas q« shp+— a, a7 qe » f+ cs cei —+cj 6 ape & coo ++] 2s or vee » 2+ av Figure 2-9 6520 Input Designation (PIA) the following: * Compatibility with the 6542 microprocessor (CPU) Eight-bit bidirectional data bus for communi- cation with the microprocessor, Two 8 bit bidirectionsl parts for interface to peripheral. Two progremmsble Control Registers. Two programmable Data Direction Registers. Four individually controlled interrupt input20 Lines; two usable as peripheral control outputs. * Handshake control logic for input and output peripheral operation, * High-impedance three-state and direct tran- sistor drive peripheral lines. * Program-controlled interrupt and interrupt mark capebility. 2.7 6520 ORGANIZATION Figure 2-10 contains a block diagram of the 6520 showing the internel registers and data path and the verious inputs and outputs on the device. This section contains a general description of the internal organizetion of the device, along with a discussion of how the various registers affect one another, The 6520 is‘ orgenized into two independent sections referred to as the "A side" end the "B side." Each section consists of a Control Register (CRA,CRB), Data Direction Register (DDRA,DDRB), Output Register (ORA,ORB), Interrupt Status Control and the buffer necessary to drive the Periph- eral Interface busses, 2.7.1 DATA INPUT REGISTER When the microprocessor writes data into the 6520, the date appearing on the data bus during the phase 2 clock pulse is latched into the Data Input Register, It is then transferred into one of six internal registers of the 6520 after the trailing edge of phase 2.21 TROA Toverrupt Stanit cat Control az Control P| Register 8 Data Oi Ltcral_| Register A (o0aA) Output Bus Pag - PAI Peripheral Peripheral Paz ‘ourout Interface Pas Register A Butter Pad (ORA) 7 Pas PAG PA P30 Peripheral Pat La} output Perioheral P92 P| Resistr 8 vacertace P83 (ORB) Butter Pea 8 P85 P86 87 Input Bue (cra) lnverrupt Stacus cat TAG. Control a Figure 2-10 6520 Internal architecture 2.7.2 CONTROL REGISTERS (CRA and CRB) The Control Registers allow the microprocessor to control the operation of the interrupt lines (CA1,CA2,CB1, CB2), and peripheral control lines (CA2,CB2). A single bit in each register controls the addressing of the Data Direct- tion Registers (DDRA,DDRB) and the Output Registers (ORA, ORB) discussed below. In addition, two bite are provided22 in each control register to indicate the status of the interrupt input lines (CA1,CA2,CB1,0B2). These interrupt status bits (TRQA,IRQB) are normally interrogated by the microprocessor during the interrupt service program to determine the source of an active interrupt. These: inter- Tupt lines drive the interrupt input (IRQ,NMI) of the micro~ processor. 2.7.3 DATA DIRECTION REGISTERS (DDRA,DDRB) The Date Direction Registers allow the processor to program each line in the 8 bit peripheral 1/0 port to act as either an input or an output, Each bit in the DDRA controls the corresponding line in the peripheral A port, and each bit in the DDRB controls the corresponding line in the peripheral B port, Placing a "$" in the Data Direction Register causes the corresponding peripheral I/O line to act as an input, while a "1" causes it to act as an output, - The Data Direction Registers are normally programmed only during the system initialization routine which is per- formed in response to a Reset signal; however, the contents of these registers can be altered during system operation. This allows very convenient control of some peripheral devices such as keyboards. 2.7.4 PERIPHERAL OUTPUT REGISTERS (ORA,ORB) The Peripheral Output Registers store the output data which appears on the peripheral I/0 port, Writing an "g* into a bit in ORA causes the corresponding line on the Peri-23 eral A port to go low if that line is programmed to act as an output. A "1" causes the corresponding output to go high. The lines. of the Peripheral B port are controlled by ORB in the same manner, 2.7.5 INTERRUPT STATUS CONTROL The four interrupt/peripheral control lines (CA1,CA2, 0B1,CB2) are controlled by the Interrupt Status Control (A,B). This logic interprets the contents of the corresponding Con- trol Register, detects active transitions on the interrupt inputs and performs those operations necessary to assure proper operation of these four peripheral interface lines. 2.7.6 PERIPHERAL INTERFACE BUFFERS (A,B) AND DATA BUS BUFFERS (DBB) The Buffers drive the peripheral I/0 ports and the data bus to provide the current and voltage drive necessary to ensure proper system operation and to meet the device specifications.CHAPTER III SIMULATOR SYSTEM (KO65) 3.1 INTRODUCTION The most useful feature of this system is that it can help the user to debug his program by single-stepping and tracing. Also useful is the system's feature allowing the user to exemine the contents of memory and registers at any time. The K065 system is comprised of the following parts: 1) Loader 2) Addressing Mode 3) Instruction Set Decoder 4) Internal Register Simulator 5) Memory Simulator 6) Internal Register Simulator for the 6520 (1/0 Device Peripheral Interface Adapter) 3.2 LOADER The loader takes the object code previously generated by the ASM65 assembler program and loads it on top of the simulated memory. This will enable the system to execute each instruction. Figure 3.1 illustrates the flowchart for the loader progrem. As illustreted by the flowchart, the first line of object code will be read. The Progrem Counter recognizes each address and its corresponding object code snd dataine Input From Object File Take Address in Hex Convert To Decimal Set Counter with this Address Take Opcode in Hex Convert to Decimal and Relocate in Menory Space Increment Counter Take First Byte and Relocate in Menory Space Tnorement Counter Take Second Byte and Relocate in Memory Space Figure 3.1 Flowchart for Losder Program26 (2 dytes or 3 bytes instruction) will be located in certain memory space. This process continues until all object codes and data are relocated in the simulated memory. 3.3 ADDRESSING MODE The 6592 offers eleven basic eddressing modes: 1) Memory - immediate 2) Memory - absolute or direct, non-zero page 3) Memory - zero page (direct) 4) Implied or inherent 5) Accumulator 6) Pre-indexed indirect 7) Port-indexed indirect 8) Zero page, indexed (also called base page, indexed 9) Absolute indexed 10) Relative 41) Indirect There are tremendous variations in terms of which methods are allowed with which instructions. : The author wrote a subroutine for the eleven differ- ent 6502 addressing modes that can be called each time by the main program for the purpose of executing instructions, This avoids repetition of addressing modes during execution time. Figure 3.2 is a flowchart illustrating this subroutine. For simplicity, each addressing mode has a code number from one to eleven (decimal) assigned to variable 4 throughout the main program. M has a different number when-27 Tnorement Counter Take Two Byte in Hex and Convert to Decimal Numbex in Hex and Convert to Dec For Indirect Addressing Replace Variable} Figure 3.2 Flowchart for Addressing Mode Program28 ever the main program calls this subroutine. The subroutine recognizes the number as a specific addressing mode. ‘The corresponding operand or address will be fetched out of the memory and used by the simulator to execute the instruction. 3.4 INSTRUCTION SET DECODER The author used each Opcode for decoding instructions, First, he started with the arithmetic operations such as: ADC, ORA, EOR, CMP, and SBC. All of these instructions have the same number (1,5,9, or D) as their first digit. This is also true for STA and LDA (data transfer operation). The rotating instruction set (ASL, LSR, ROL, ROR) and Increment, Decrement instructions (INC, DEC) have the same number (6 or E) in the first digit of the Opcode. In this way we can easily separate them for the purpose of decoding. Table 3.1 illus- trates 6592 Instruction Object Codes. The next instructions are conditional branch (BCC, BCS, BEQ, BMI, BNE, BPL, BVC, BVS) which have g as the common first digit between them, The rest of the instructions have been decoded with their specific Opcode in hex notation. There are seven status flags associated with the execution of instructions. ‘These flags are: Sign or Negative status Overflow status Break status Decimal Mode status How 4 Interrupt Diseble statusTABLE 3.1 6562 Instruction Object Codes Opsect Instruction Opsact Instruction Sf 00 BRK 68 PLA 01 ORA = (addr, X) 69 ADC data 05 ORA addr 6A ROR A 06 ASL addr 60 SMP (abel) 08. PHP 6D ADC addr 16 09 ORA = date 6E ROR addr 16 OA ASL A 70 BVS disp oD ORA addr 16 m1 ADG (addr) j¥ Oz ASL addr 16 15 ADC addr, X~ 10 BPL disp 76 ROR addr, X 14 ORA (addr) ,¥ 78 SEL 15 ORA = addr, x 79 ADC = addr 16, 16 ASL addr, X 2D ADC addr 16, 18 oL¢ 1B ROR addr 16,x| 19 ORA addr 16, 81 sta (addr, x} 1D ORA = addr 16, 84 sTY addr 1B ASL addr 16,X 85 STA addr 20 JSR label 86 sTX addr 24 AND (addr, X) 88 DEY 24 BIT addr 8A TxA 25 AND addr 8c STY addr 16 26 ROL addr. 8D STA addr 16 28 PLP 8E STX addr 16 29 AND data 90 BCC disp 2a ROL A 94 sta (addr) ,¥ 2¢ BIT addr 16 94 sTY addr, X 2D AND addr 16 95 STA addr, X 2 ROL addr 16 96 STX addr, ¥ 30 BMI disp 98 TYA 31 AND (addr) ,¥ 99 STA addr 16,Y 35 AND edar,X 9A TxXS 36 ROL = addr, X 9D STA addr 16, 38 SEC AO LDY = data 39 AND addr 16,¥ A LDA (addr, X) 3D AND addr 16,X a2 LDX data 3E ROL addr 16,X a4 DY = addr 40 RIT AS LDA addr 41 EOR (addr, X) AG LDX addr 45 BOR addr a8 TAY 46 LSR addr Ag LDA data 48 PHA AA TAL 49 EOR data AC LDY = addr 16 4a LSR A aD LDA addr 16 4c cMP label. AE LDX = addr 16 4D EOR addr 16 BO BCS disp 4 ISR addr 16 Bt LDA (addr) ,¥ 50 BVC disp B4 WY addr, X oC | EEE 1 2930. TABLE 3.1 6582 Instruction Object Code (Cont. ) Ondect Instruction 51 BOR (addr),¥ addr, X 55 BOR addr, X addr,¥ 56 LsR addr, X BB 58 CLI BO addr 16,Y 59 EFOR addr 16,¥ BA ‘BSx 5D EOR addr 16,X BC LDY = addr 16,X 5E LSR addr 16,X BD LDA addr 16,X 60 RIS BE LDX = addr 16,¥ 61 ADC (addr, X) co CPY data 65 ADC addr 1 CMP (addr, X) 66 ROR addr 04 cPY = addr. c5 MP eda. BA CPX addr 06 DEC = addr. BS SBC addr cs INY 6 addr 09 MP date ES cA DEX 59 data cc CPY = addr 16 BA oD OP addr 16 EG addr 16 cE DEC addr 16 ED SBC addr 16 DO BNE disp EE INC addr 16 D1 uP: (addr) ,¥ FO. BEQ disp DS CMP addr, X rt SBC (addr) ,¥ Dé DEC addr, X #5 SBC addr, X De LD 5 INC addr, X D9 CMP addr 16,¥ FB DD CMP addr 16,X FO addr 16,¥. DE DEC addr 16,X YD SBC addr 16,X - EO CPX data FE INC addr 16,X' EV SBC (addr, X) 2 Zero status c Carry status Each instruction has a different effect on the flags. The flag subroutine (Appendix C) was written for this purpose. During the execution of each instruction, the main program will call this subroutine in order to change the proper fleg. For the conditional branch operation, thie subroutine is called before execution to branch to enother part of the program.34 3.5 INTERNAL REGISTER SIMULATOR The 6592 microprocessor has two Index Registers, (X and ¥), one Accumulator (A), Program Counter (PC), Stack Pointer (SP), and Status Register (P), All these registers are considered as internal registers, The P Register was discussed above. The author has assigned certain variables to the internel registers as follows: A% = Accumulator A X = Index Register ¥ = Index Register ¥ © = Program Counter PC S = Stack Pointer sP P = Statis Register P All internal registers are simulated for future use during program execution. 3.6 MEMORY SIMULATOR The PDP-11/34 has a 16K user memory, 13.5 K of which is occupied by the K065 software program with 2.5 K remaining for the simulated memory, The addressable memory location for this system is between 690016 and 949416. Memory contents are visible to the user. 3.7 INTERNAL REGISTER SIMULATOR FOR THE 6520 (1/0 DEVICE) The internal registers of the 6520 are simulated by assigning memory locations as follows: @9FB = CRA (Control Register A)32 @9FC = ORA (Output Register A) @9FD = DDRA (Data Direction Register A) O9FE GOFF = ORB (output Register B) AGO = DDRB (Data Direction Register B) CRB (Control Register B) In this case, the user has the capability of alter- ing end viewing the contents of these internal registers of. the 6520 (1/0 Device). 3.8 SUMMARY The information in this chapter should give the reader an overview of how the 6502 microprocessor has been simulated by the K065 system, The detailed commands of this simulator system will be discussed in the next chapter.CHAPTER IV USER'S GUIDE FOR ASM65-KO65 SYSTEMS 4.1 INTRODUCTION The KO65 Simulator is a software program running on the PDP-11/34 minicomputer and having the property of simu- lating the instruction set of the 6592 based microcomputer system and behaving in every respect as the real machine. Tho ASM65 assembles the 6502 assembly language source file, generates the object file for the K065 system, and furnishes error messages as and when required, The K065 also possesses advanced features, such as: trace, single-step, trap, internal registers, and memory inspection that enables the user to efficiently develop and debug software for the 6502 . microcomputer system. 4.2 USER STEPS (SUMMARY) 1. Log on the RSTS/E Operating System (PDP-11/34) 7 (HELLO) 2. Log on the EDITOR (=Dt) 3. Create a new file user defined name (name of the file to be assembled) 4. Log on the ASM65 System (Assembler) (RUN ASM65) 5. Create object file and symbol table by the ASN65 (name of the object file to be used by K065 System)34 6. Log on the K065 System (simulator) (RUN K065) 7. Load the object file (Load) 8. Enable trace mode (TRA) 9. Reset trace mode (wor) 10. Enable single-step mode (sIN) 41, Reset single-step mode (ros) 42, RUN the program (ao) 13. Trap the program (TRP) 14, Reset the trap (NTP) 15. Display memory, registers, symbol table (DIS) Peripheral Interface Adapter (PIA) 16, Set registers, program counter (PC) and stack pointer (SP) (SET) 17, Clear internal registers, PC and SP (CLR CPU) 18. Set PIA (SPTA) 19. Exit from KO65 System (exrr) 20. Log off from RSTS/E System (BYE). 4.3 LOGGING ON THE RSTS/E OPERATING SYSTEM-(PDP-11/34) Turn on the terminal, type the command HELLO and strike the RETURN key, This informs thé computer that you are now joining the system. The computer prints a heading, identifying itself; your job number; the date; and time, On the next line it types a number sign (#) and then waits for you to type in your user number, After you have typed in your number and struck the return key, the computer prints:35 PASSWORD: Type your password, but as 2 security measure the computer does not print out the password on the terminal. Again strike the RETURN key. By now it should be spparent thet all entries are followed by a RETURN. Failure to hit the RETURN key results in the computer not recording your entry. If either the user number or password is incorrect, the ccm- puter prints the error message: INVALID EVURY--TRY AGAIN # and allows you to reenter your user number and password, The following is a semple log in: HELLO RSIS V66C 21-APR-18 11:44 aM #35,8 PASSWORD: Announcements (if any) will eppear on the screen. The READY prompt following announcements is first printed when the user is successfully logged onto the system: READY The user is now ready to enter any valid command. If an invalid command is entered, response of the RTST/E will be: 2 WHAT ? There is a faster way to log on the RSTS/E system by typing: I (User Account number) For example: 135/8 The RSTS/E now responds with: PASSWORD:36 Note that in the preceding example, the user types a slash (/) in the Account No. and not a comma. 4.4 LOG ON THE EDITOR To use TEDIT, enter the command EDT file name where the file name is the neme of the source file to be edited and then assembled by ASM65 system, TEDIT will respond with some statistics and then the prompt EDIT> after which you msy enter the editor commands. If the file does not exist, a suitable message is printed and the file is created for the user. 4.4.1 COMMAND SUMMARY The following is a listing of important commands syntax; = ADD OR A (short form) This permits the user to add more lines to the end of the file from the keyboard, For.example: . EDIT) ADD Type CTRL/Z to stop insertions 34) In the example above, the user may add new lines to the file starting at number 34 (last line of previous file = 33).37 4.4.2 CHANGE The change command allows the user a combination of delete arid insert commands. This command will delete a line (S) specified and start inserting new lines at that point. To end this command enter CTRL/Z immediately after the line number. The CTRL/Z will not be inserted in the file, After the changes have been made, EDIT renumbers the line numbers consecutively. CHANGE n OR Cn (short form) This deleted line number n; then EDIT allows the user to insert any number of lines in place of line number n, After entering CHANGES 45, line 45 will be deleted and any number of new lines may be inserted in place of line number 45. CHANGE nym OR C n,m This deleted line numbers n through m inclusive end inserts any number of new lines in place of those lines deleted. After entering CHANGE 20,25; line number 20 through 25 inclusive will be deleted and new lines will be inserted in place of them. 4.4.3 DELETE OR D (short form) The delete command allows the user to delete a line (S) from the file. If the user attempts to delete more than 15 lines, EDIT will come back and ask for confirmation of the command, DELETEn OR Dn38 This deletes line number n only, Line 19 of the file will be deleted after DELETE 1 is entered. DELETE nym OR D n,m This deletes line number n through m inclusive. After entering DELETE 4,8; lines 4 through 8 inclusive will be deleted from the file. DELETE 1,20 This deletes the first 20 lines after a confirmation of yes. EDIT) D 1,20 ARE YOU SURE (NO>? YES The question "ARE YOU SURE REPLACE 16 OLD String ? 2 NEW String ? 4 This replaces every occurrence of the character "2" in line number 19 with the character "4".