Types of ASIC
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General Classification of IC ‘s
ICs
Standard IC’s ASSP ASICs
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Standard IC’s
A standard IC is one that can be purchased by quoting
a part number from the market.
Examples of standard ICs are logic gates, flip flops,
counters, R A M and Microprocessors .
A standard IC will always be listed in a data manual.
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Application Specific Integrated Circuit
• ASIC is an integrated circuit designed and developed to
meet a specific application.
• Not a standard part or standard IC.
• ASICs typically implements a custom function according to
given description.
• ASICs are not listed as part of a data manual
• Also known as custom ICs.
• ASICs are made up of cells - N A N D, NOR, Flip-flops,
multiplexers, ALUs, R A M blocks ...
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Application Specific Standard Product
• As a general rule, if you can find a design in a data book,
then it is probably not an ASIC, but there are some exceptions.
• For example, two ICs that might or might not be considered
ASICs are a controller chip for a PC and a chip for a modem.
• Both of these examples are specific to an application (shades
of an ASIC) but are sold to many different system vendors
(shades of a standard part).
• ASICs such as these are sometimes called Application-
Specific Standard Products ( ASSPs )
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When to go for an ASIC ?
• An ASIC should be designed only if a functionally
equivalent standard off the shelf component is not
available from the market.
• ASIC can be designed for
– an IC used in a smart card.
– an IC used in a camera
– an IC used for a hand held toy ...
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ASIC Advantages
• Miniaturization
– ASIC can replace the functions realized by a number
of PCBs resulting in size reduction.
• Lesser Inventory
– The reduced number of components per system
reduces the inventory.
• System Reliability
– Lesser number of components are used. Hence lesser
failures.
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ASIC Advantages
• Lower Power Consumption
– Most ASICs are based on C M O S technology.
– Lesser number of components reduces the power
consumption.
• Proprietary Nature
– Extremely difficult to copy an ASIC based design.
– R&D investments are protected.
• Performance
– Usage of ASIC will improve system performance like
high speed, more functionality
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Risk of using an ASIC
• Higher Cost
– The cost per gate of an ASIC is very high
– Turn around time for an ASIC based design is high
– ASIC design requires more time for design and
development.
• Time to market
– The product lead time will be more for an ASIC
based design
– The right product should be introduced into the
market at the right time.
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ASIC Classification
Classified based on the number of mask processes
required for fabrication
Full Custom
Semi Custom
Programmable ASICs
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ASIC Classification
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Full-Custom ASIC
An engineer designs all or most of the logic cells,
circuits, or layout needed for that ASIC right from the
scratch.
The designer has to define the characteristics of all the
cells and circuits.
All the logic cells and mask layers are customized.
The fabrication of a Full Custom ASIC involves all the
mask processes.
A microprocessor is a good example.
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Full-Custom ASIC
The most rigorous full custom design can be the design
of a memory cell -
static or dynamic.
In a full-custom layout, the geometry, orientation and
placement of every transistor is done individually by
the designer.
Design productivity is usually very low.
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Full Custom ASIC
Necessity of Full-custom ASICs
if the ASIC technology is new,
specialized that there are no existing cell libraries,
the existing cell libraries are not fast
high volume products such as memory chips, high
performance microprocessors
the logic cells consume more power.
some circuits must be custom designed.
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ASIC Classification
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Semi Custom ASICs
The designer uses the pre-characterized and pre-fabricated
logic cells.
Most of the mask layers are customized - transistors and
interconnect
Reduces the design time and turn around time of the ASIC
First time success is more than the Full Custom approach.
Manufacturing lead time is around 8 weeks.
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Standard Cell - Based ASICs
• Cell based ASIC (CBIC)
• It uses predesigned and pre-characterized logic cells known
as Standard cells.
• The standard cell library includes from simple logic gates
and functions like NAND, XOR, FF, ADDER, Comparators,
ALU to complex functions like microprocessor core, RAM,..
• Standard cells are constructed using full-custom design
methods.
• Designers defines only the placement of the standard cells
and interconnect in CBIC.
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Standard -cell- based ASIC
Advantages
Designers save time, money, and reduce risk by using a
predesigned, pretested, and precharacterized standard-cell
library.
Each standard cell can be optimized individually.
Disadvantages
The time or expense of designing or buying the standard-
cell library
The time needed to fabricate all layers of the ASIC for each
new design
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Standard -cell- based ASIC
• To customize the chip,
the designer defines
the floor planning and
interconnects.
• Standard cells are
designed to fit like
bricks in a wall.
• Groups of standard
cells fit horizontally
together to form
rows.
• CBIC are built of rows
of standard cells.
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Standard Cell - Based ASICs
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Expanded view of Flexible block
Feed through
• Connections that need to cross over standard cells uses feedthrough.
• Feedthroughs in cell A14 and A23 (space or metal)
Spacer cells and row end cells
• Standard cell uses metal1 for power rails(Vdd and gnd)
• Width of each row of standard cells is adjusted so that they aligned using spacer cells.
• Power rails are connected to additional vertical power rails using row-end cells at aligned end of each
standard block.
Power cells
• If rows of standard cells are long, then vertical power rails can also be run in metal2 through the cell rows
using special power cells that just connect to VDD and GND.
• Designers manually control the number and width of vertical power rails connected to standard cell blocks
during physical design.
Full Custom Vs Semi Custom
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ASIC Classification
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Gate Array based ASICs (MGA)
Uses predefined and pre-characterized cells.
The cells are not only pre-characterized but also prefabricated.
The first step of Gate array implementation results in an array of
uncommitted transistors on each GA chip.
Base cell - The smallest element that is replicated to make the
base array.
Base array - The predefined pattern of transistor on a gate array.
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Gate Array based ASICs
The user cannot change the transistor size or optimize the
speed or performance of the cells.
All the transistor sizes and placements are fixed.
The logic cells in a Gate Array library are referred to as
macros
The designers job is to interconnect the macros to realize
the function.
The macros include the basic gates, FF and functions like
memory.
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Types of Gate-array-based ASICs
Channeled gate arrays.
Channel less gate arrays.
Structured gate arrays.
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Channeled Gate Array
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Channeled Gate Array
The rows of macros are separated by fixed
height routing channels used to
interconnect the macros.
Channeled Gate Arrays have alternate
rows of transistors and wiring channels.
The widths of the wiring channels are
fixed.
The transistors(macros) are interconnected
to achieve logic functions using these
wiring channels.
Only interconnects are customized.
Manufacturing lead time is between
two days to two weeks
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Channeless Gate Array
I / O Blocks
Array
element
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Channeless Gate Array (Sea - of - Gates)
Do not have predefined channels for interconnect.
The interconnections are done over the top of the
prefabricated logic devices by customizing the metals
using masks.
The Sea-of-gates(SOG) occupies the entire core of the
chip.
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Channel less Gate Array (Sea - of - Gates)
The number of array of elements has been increased by a factor
of about 2
The net result is that the SOG architecture allows a large number
of array elements to be utilized than a channeled structure for
the same size of die.
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Structured gate Array
• Only the interconnect is
customized.
• Custom blocks (the same for
each design) can be
embedded.
• Manufacturing lead time is
between two days and two
weeks.
Structured Gate Array
These arrays are also known as embedded or master slice or master
image gate arrays.
This type of gate array will have some sort of embedded mega functions
like memory in it.
It combines some features of CBICs and MGA(masked gate array).
Only the interconnect is customized, Custom blocks can be embedded.
It gives improved area efficiency and increased performance of a CBIC but
with the lower cost and faster turnaround of an MGA.
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CBIC Vs G A
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ASIC Classification
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Programmable Logic Devices (PLD)
PLDs may be configured or programmed to create a part
customized to specific application & so they belong to family
of ASICs.
No customized mask layers or logic cells
Fast design turnaround
A single large block of programmable interconnect
A matrix of logic macrocells that usually consists of
programmable array logic followed by a flip-flop or latch.
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Programmable Logic Devices (PLD)
macrocell
programmable
interconnect
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Types of PLDs
Read-only memory (ROM)
Programmable RO M (PROM)
Electrically programmable RO M (EPROM)
Electrically erasable PROM (EEPROM)
UV-erasable PROM (UVPROM)
Masked-programmable RO M (Masked ROM)
Programmable Array logic (PAL)
Programmable logic array (PLA)
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Why programmable logic?
Fast time to market
Proprietary design
Small physical design
Low power consumption
High reliability
No Re-engineering
No ASIC type risk.
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IP COREs
IP Cores are ready-made logic blocks
Advantages
No re-invention
Reduced design time
Fast time to market
Fully verified proven blocks
Lowest design risk.
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IP COREs
Typically cores are available for
• Bus interfaces (PCI,PCMCIA, USB)
• Memory interfaces
• Processors
• DSP
• Communication functions.
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FPGAs
FPGAs are the most popular PLDs.
All the logic elements are prefabricated and pre-
metalized.
Individual blocks are connected through the use of
fuses, anti-fuses, SRAM cells or other technologies.
Newer FPGAs have a gate capacity of well over 700 K
gates with embedded memory function.
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FPGAs
FPGAs have a faster turn around time and lower NRE
expenses compared to Gate Arrays.
Widely used for low volume production and for design trials
before going for G A or Standard cell ASIC.
FPGAs lag behind G A technology in gate utilization, speed,
volume production, embedded functions and delay
predictability.
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Characteristics of an FPGA
None of the mask layers are customized.
A method for programming the basic logic cells and the
interconnect.
The core is a regular array of programmable basic logic cells
that can implement combinational as well as sequential
logic(flip-flop).
A matrix of programmable interconnect surrounds the basic
logic cells.
Programmable input/output cells surround the core.
Design turnaround is a few hours.
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FPGA Structure
IO
CLB
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Comparison
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