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Cmos Process Flow 1

The document describes the key steps in fabricating CMOS integrated circuits using different process flows. It discusses wafer preparation, oxidation, lithography, etching, and metallization. Specifically, it covers growing silicon crystals with controlled doping, oxidizing silicon to form insulating silicon dioxide layers, using photolithography to pattern circuits, and constructing CMOS inverters using N-well, P-well, and twin-tub processes. The fabrication process involves carefully controlling multiple steps to build up functional transistors and logic gates on a silicon wafer.

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88 views41 pages

Cmos Process Flow 1

The document describes the key steps in fabricating CMOS integrated circuits using different process flows. It discusses wafer preparation, oxidation, lithography, etching, and metallization. Specifically, it covers growing silicon crystals with controlled doping, oxidizing silicon to form insulating silicon dioxide layers, using photolithography to pattern circuits, and constructing CMOS inverters using N-well, P-well, and twin-tub processes. The fabrication process involves carefully controlling multiple steps to build up functional transistors and logic gates on a silicon wafer.

Uploaded by

barnwaldivyanshu7
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Fabrication Processes

Wafer Processing & Preparation


Oxidation
Epitaxy
Diffusion
Ion Implantation
Lithography
Etching
Metallization
Darshana Sankhe, DJSCE
CMOS Process Flow for N-well, P-well & Twin Tub
Fabrication Steps :
 Refining of Si
 Crystal growth and wafer preparation
 Epitaxy
 Oxidation
 Diffusion
 Ion Implantation
 Lithography
 Etching
 Metallization

Darshana Sankhe, DJSCE


Darshana Sankhe, DJSCE
Crystal growth :
 Growing of single crystal Si from fine granules of Si (EGS) under
controlled doping of impurities at a temperature ≥1000°c

 Impurities added to Si are


 P type Si – Boron (B2H6 i.e. diborane )
 N type Si – phosphorous (PH3 i.e. phosphene)
 Doping concentration – 1015 to16 /cm3

 CZ Process – Subsystems
 Furnace
 Crystal pulling system
 µp based Control system
 Temperature, speed of rotation, pull rate, flow rate, crystal
Darshana Sankhe, DJSCE
diamensions, gas source and exhaust system….
Crystal growth : CZ Process (Czochralski)

Darshana Sankhe, DJSCE


Oxidation : LOCOS – Reaction of Si with O2 to form SiO2
 Surface protection
 Dielectric for MOS structure (thin SiO2)
 Mask against diffusion / ion implant
 Device isolation (thick SiO2)
 Isolation for multilevel metallization

Darshana Sankhe, DJSCE


Oxidation :

 Grow SiO2 on top of Si wafer at 900 – 1200 C with H2O or O2


in oxidation furnace
SiO2

p substrate

Darshana Sankhe, DJSCE


Oxidation:

Darshana Sankhe, DJSCE


Photolithography :Process of transferring
the pattern from mask to substrate

Darshana Sankhe, DJSCE


Darshana Sankhe, DJSCE
Diffusion Profile:

Darshana Sankhe, DJSCE


Diffusion Profile:

Darshana Sankhe, DJSCE


Ion Implantation :

Darshana Sankhe, DJSCE


Darshana Sankhe, DJSCE
CMOS Inverter Fabrication :
 N-well process
 P-well process
 Twin tub process

Darshana Sankhe, DJSCE


CMOS Inverter using N-well Process:

Darshana Sankhe, DJSCE


CMOS Inverter using P-well Process:

N+ implant/diffusion

N+ mask

P+ N+ P

N-type substrate

Darshana Sankhe, DJSCE


CMOS Inverter using Twin-Tub Process:

Darshana Sankhe, DJSCE


CMOS Inverter using N-well Process:

Darshana Sankhe, DJSCE


CMOS Inverter using N-well Process:

Darshana Sankhe, DJSCE


CMOS Inverter using N-well Process:

Darshana Sankhe, DJSCE


CMOS Inverter using N-well Process:

Darshana Sankhe, DJSCE


CMOS Inverter using N-well Process:

Darshana Sankhe, DJSCE


CMOS Inverter using N-well Process:

Darshana Sankhe, DJSCE


CMOS Inverter using N-well Process:

Darshana Sankhe, DJSCE


CMOS Inverter using N-well Process:

Darshana Sankhe, DJSCE


CMOS Inverter using P-well Process:

Darshana Sankhe, DJSCE


CMOS Inverter using P-well Process:

Darshana Sankhe, DJSCE


CMOS P-well INVERTER:

Darshana Sankhe, DJSCE


CMOS Fabrication Mask :
1. Define window in oxide region/ well mask

2. Pattern poly mask

3. Diffusion mask(n-diffusion & p-diffusion)

4. Contact cut mask

5. Metal layer pattern

6. Over glass layer mask for bonding pads


Darshana Sankhe, DJSCE
CMOS Inverter using Twin-Tub Process:

Darshana Sankhe, DJSCE


CMOS Inverter using Twin-Tub Process:

Darshana Sankhe, DJSCE


CMOS Inverter using Twin-Tub Process:

Darshana Sankhe, DJSCE


CMOS Inverter using Twin-Tub Process:

Darshana Sankhe, DJSCE


CMOS Inverter using Twin-Tub Process:

Darshana Sankhe, DJSCE


CMOS Inverter using Twin-Tub Process:

Darshana Sankhe, DJSCE


CMOS Inverter using Twin-Tub Process:

Darshana Sankhe, DJSCE


CMOS Inverter using Twin-Tub Process:

Darshana Sankhe, DJSCE


CMOS Inverter using Twin-Tub Process:

Darshana Sankhe, DJSCE


CMOS Inverter using Twin-Tub Process:

Darshana Sankhe, DJSCE


Thank You

Darshana Sankhe, DJSCE

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