Date EXP.N0. Page No.
SYNTHESIS OF FLIPFLOPS
AIM: To design synthesis of flip flops.
COMPONENTS :
1) Sequential Circuits(RS Flip flop, JK Flip flop, D Flip flop, T
Flip flop)
• SR Flip flop-2 AND Gates +2 NOR Gates
• JK Flip flop-4 NAND Gates
• D Flip flop-4 NAND Gates
• T Flip flop-4 NAND Gates
2) Bit switches
3) Clock pulse
4) Bit Display
5) Connecting Wires
THEORY :
A flip-flop is a sequential digital electronic circuit having two stable states that
can be used to store one bit of binary data. Flip-flops are the fundamental
building blocks of all memory devices. A digital flip flop constructed using four
NAND or four N0R gates.
TYPES OF FLIP FLOPS:
1) SR Flip flop
2) JK Flip flop
3) D Flip flop
4) T Flip flop
SR FLIP FLOP:
SR Flip-flop is the most basic sequential logic circuit also known as SR latch. It has
two inputs known as SET and RESET. The Output “Q” is high if the input as SET is high (when
the clock is triggered). If the input RESET is high when the clock is triggered, the Output “Q”
would be “LOW”. Note that both the Inputs i.e. SET and RESET should not be “High” when the
clock is triggered as it is considers as invalid input condition which leads to unpredictable
output result.
J.N.T.U.A College of Engineering (Autonomous), Pulivendula Department of Computer Science and Engineering
Date EXP.N0. Page No.
CIRCUIT DIAGRAM:
CHARACTERISTICS TABLE:
TRUTH TABLE:
JK FLIP FLOP:
The Jk flip flop is used to remove the drawback of the S-R flip flop, i.e., undefined states.
The JK flip flop is formed by doing modification in the SR flip flop. The S-R flip flop is improved
in order to construct the J-K flip flop. When S and R input is set to true, the SR flip flop gives an
inaccurate result. But in the case of JK flip flop, it gives the correct output.
J.N.T.U.A College of Engineering (Autonomous), Pulivendula Department of Computer Science and Engineering
Date EXP.N0. Page No.
CIRCUIT DIAGRAM:
CHARACTERISTIC TABLE:
TRUTH TABLE:
D FLIP FLOP:
In a D flip-flop, the output can only be changed at positive or negative clock
transitions, and when the inputs changed at other times, the output will remain unaffected.
The D flip-flops are generally used for shift-registers and counters. The change in output state
of D fli flop depends upon the active transition of clock. The output (Q) is same as input and
changes only at active transition of clock
J.N.T.U.A College of Engineering (Autonomous), Pulivendula Department of Computer Science and Engineering
Date EXP.N0. Page No.
CIRCUIT DIAGRAM:
CHARACTERISTIC TABLE: TRUTH TABLE:
T FLIP-FLOP:
A T flip-flop (Toggle Flip-flop) is a simplified version of JK flip-flop. The T
flop is obtained by connecting the J and K inputs together. The flip-flop has one
input terminal and clock input. These flip-flops are said to be T flip-flops because
of their ability to toggle the input state. Toggle flip-flops are mostly used in
counters.
CIRCUIT DIAGRAM:
J.N.T.U.A College of Engineering (Autonomous), Pulivendula Department of Computer Science and Engineering
Date EXP.N0. Page No.
CHARACTERISTIC TABLE:
PROCEDURE :
1) Start the simulator and use the required logic gates to construct the
sequential circuits (flip flops).
2) Now take the required components from the palette and click on the
editor window where you want to add it.
3) To connect any two components select connection menu of the pallete
and then click on source terminal to target terminal connect all the
components.
4) To know about pin configuration goto toolbar and click on the pin-
config and you will see it.
5) To see the circuit working, click on the selection tool in the palette,
then give input by double clicking on the bit switch.
6) Now in the toolbar select start clock to change clock pulse and by
giving input see the output.
7) Hence, by giving all inputs check the output of each flip flop.
8) Stop the simulator.
J.N.T.U.A College of Engineering (Autonomous), Pulivendula Department of Computer Science and Engineering
Date EXP.N0. Page No.
OUTPUT:
1) RS FLIP FLOP:
CIRCUIT DIAGRAM:
Input: CP=1, R=1, S=0 Output: Q=0, Q=1
Input: CP=1, R=0, S=1 Output: Q=1, Q=0
J.N.T.U.A College of Engineering (Autonomous), Pulivendula Department of Computer Science and Engineering
Date EXP.N0. Page No.
Input: CP=1, R=0, S=0 Output: Q=1, Q=0
Input: CP=0, R=0, S=0 Output: Q=1, Q=0
J.N.T.U.A College of Engineering (Autonomous), Pulivendula Department of Computer Science and Engineering
Date EXP.N0. Page No.
Input: CP=0, R=1, S=1 Output: Q=1, Q=0
Input: CP=1, R=1, S=1 Output: Q=0, Q=0
JK FLIP FLOP:
CIRCUIT DIAGRAM:
J.N.T.U.A College of Engineering (Autonomous), Pulivendula Department of Computer Science and Engineering
Date EXP.N0. Page No.
Input: CP=1, J=1, K=0 Output: Q=1, Q=0
Input: CP=1, J=0, K=1 Output: Q=0, Q=1
Input: CP=1, J=0, K=0 Output: Q=0, Q=1
J.N.T.U.A College of Engineering (Autonomous), Pulivendula Department of Computer Science and Engineering
Date EXP.N0. Page No.
Input: CP=0, J=0, K=0 Output: Q=0, Q=1
Input: CP=0, J=1, K=1 Output: Q=0, Q=1
Input: CP=1, J=1, K=1 Output: Q=1, Q=0
J.N.T.U.A College of Engineering (Autonomous), Pulivendula Department of Computer Science and Engineering
Date EXP.N0. Page No.
D FLIP FLOP:
CIRCUIT DIAGRAM:
Input: CP=1, D=1 Output: Q=1, Q=0
Input: CP=1, D=0 Output: Q=0, Q=1
J.N.T.U.A College of Engineering (Autonomous), Pulivendula Department of Computer Science and Engineering
Date EXP.N0. Page No.
Input: CP=0, D=1 Output: Q=0, Q=1
Input: CP=0, D=0 Output: Q=0, Q=1
T FLIP FLOP:
CIRCUIT DIAGRAM:
J.N.T.U.A College of Engineering (Autonomous), Pulivendula Department of Computer Science and Engineering
Date EXP.N0. Page No.
Input: CP=1, T=1 Output: Q=1, Q=0
Input: CP=0, T=0 Output: Q=0, Q=1
Input: CP=0, T=0 Output: Q=1, Q=0
J.N.T.U.A College of Engineering (Autonomous), Pulivendula Department of Computer Science and Engineering
Date EXP.N0. Page No.
Input: CP=0, T=1 Output: Q=1, Q=0
RESULT:
To design synthesis of flip flops was executed successfully.
J.N.T.U.A College of Engineering (Autonomous), Pulivendula Department of Computer Science and Engineering
