Multiple Choice (10%) Fill Blank (5%)
1. C
1. C0000H
2. C
2. 20 bits
3. A
16 bits
4. B
3. 32 bits
5. A
4. AL = FFH
6. C
CF = Unaffected
7. D
8. C
9. F
10. F
Descriptive Questions (15%)
1. Pointers and Index registers are used to keep offset addresses.
a. Index Registers
I. SI-Source Index Register: By default, it keeps offset address relative to DS.
In string operations, it points to memory location in the data segment which
addressed by the DS register.
II. DI-Destination Index Register: By default, it keeps offset address relative to
DS. However, in string operations, DI points to memory location in the extra
segment which is the destination segment in string operations addressed by ES
register.
b. Pointer Registers
I. BP- Base Pointer Register: keeps offset address relative to SS.
II. SP- Stack Pointer Register: Keeps offset address relative to SS. It always
points to top item on the stack. For empty stack, SP will always have FFFEH
value.
2. Main components of Execution Unit are:
a. Instruction Decoder: Translates instructions fetched from memory into a series of
actions which EU carries out.
b. Control System: Generates timing and control signals to perform the internal
operations of the microprocessor (Directs the internal operations)
c. Arithmetic Logic Unit: EU has a 16-bit ALU which can ADD, SUBTRACT, AND,
OR, increment, decrement, complement or shift binary numbers.
d. Register Organization:
I. General Purpose Registers: AX, BX, CX, DX:
are used to store temporary data in the time of different operations in
microprocessor (AX, BX, CX, DX).
Can also be used as a Counter (CX).
Used for storing offset addresses for some particular addressing modes
(BX).
II. Pointers and Index Registers: see above
III. Flag Register: a flip-flop which indicates some condition produced by the
execution of instruction or controls certain operations of the EU (Execution
Unit)
Conditional flags: six flags, set or reset by EU on the basis of results
of some arithmetic operations
Control flags: three flags, used to control certain operations of the
processor
3. Machine Language Vs. Assemble Language, Sr. No 1, 5 and 6.
4. Macros Vs. Procedure
5. Program addressing mode is required for instructions that cause a branch in the program
(JMP & CALL instructions)
Types of program addressing Mode:
a. Intrasegement addressing mode: If the branch is within the segment, it is called
as an Intra-Segment Branch or a Near Branch. only IP changes, CS doesn’t
change. Two types of Intrasegment modes
I. Intra-Segment Direct Addressing Mode: Address where to transfer
program control is specified directly in the instruction as an 8-bt (16-bit)
displacement.
II. Intra-Segment Indirect Addressing Mode: Address where to transfer
program control is specified indirectly in the instruction through a register
or a memory location (in DS only)
b. Intersegment addressing mode: If the branch is in a different segment, it’s
called as an Inter-Segment Branch or a Far Branch. Both CS and IP get new
values.
I. Inter-Segment Direct Addressing Mode: The new branch location is
specified directly in the instruction.
II. Inter-Segment Indirect Addressing Mode: The new branch location is
specified indirectly in the instruction through a register or a memory
location (in DS only)
Workout (20%)
1. Givens:
CX: Undefined
Data Segment and Stack Segment
Therefore, for the instructions:
a. PUSH [BX]: This instruction pushes the value in the data segment memory
pointed by the offset address in BX into the top the stack.
SS: [SP-1] 12H, SS: [SP-2] 34H
Therefore, the stack segment will be modified as follows:
b. MOV CX, [BX]: This instruction copies the value in the data segment memory
location with offset address in BX into register CX. CX 1234H
2. Result AX = 4897H
Flags: AF = 1, PF = 0, SF = 0, CF = 0, OF = 0, ZF = 0.
3. To analyze the program, we need to go through program line by line.
Given program:
I. MOVAX, 9876h
II. MOV BX, 5432h
III. ADD BX, AX
IV. MOV CL, 03h
V. AND AL, BL
VI. OR BH, AH
VII. XOR CL, BH
The analysis steps are:
I. MOVAX, 9876h AX = 9876H
II. MOV BX, 5432h BX = 5432H
III. ADD BX, AX BX = ECA8H, SF = 1, other conditional flags = 0
IV. MOV CL, 03h CL = 03H
V. AND AL, BL; AL = 76 H form I, BL = A8H form III, Hence AL = 20H
VI. OR BH, AH; AH = 98H from I, BH = 54H from III, Hence BH = FCH
VII. XOR CL, BH; CL = 03H form IV, BH = FCH form VI, Hence CL = FFH
4. As number 3, we need to go through all lines
Given Program: CF = 0
I. MOV BX, 1ABCh
II. MOV CL, 04h
III. RCL BL, CL
IV. RCR BL, 03
The analysis steps are:
I. MOV BX, 1ABCh BX = 1ABCH
II. MOV CL, 04h CL = 04H
III. RCL BL, CL; BL = BCH form I, and CL 04H form II, CF = 0, see table below
IV. RCR BL, 03; from III, BL = C5H, and CF = 0, see table.
For III: the analysis can be depicted based For IV: the analysis can be depicted based
on the following table. on the following table.
5. Form Question: DS = 2ABCH, DI = 0032H; SS = 3ABCH, SP = 0678
a. The instruction MOV [DI], CX refers the data segment memory
Therefore;
I. Logical Address : DS:DI 2ABC: 0032
II. Physical address: DS * 10 H + 00032 2ABC0H+ 0032H = 2ABF2H
III. Lower range: when DI = 0000H, LR = 2ABC0H + 0000H = 2ABC0H
IV. Upper range: when DI = FFFFH, UR = 2ABC0H + FFFFH = 3ABBFH
b. The instruction PUSH AX refers the stack segment memory
Therefore;
I. Logical address: SS:SP 3ABC:0678
II. Physical address: SS * 10H + SP = 3ABC0H+ 0678H = 3B328H
III. Lower range: when SP = 0000H, LR = 3ABC0H + 0000H = 3ABC0H
IV. Upper range: When SP = FFFFH, UR = 3ABC0H + FFFFH = 4ABBFH
6. To show the steps clearly we need to go through all lines one by one.
Given Program:
I. MOV AX, 39h
II. MOV BX, 35h
III. ADD AX, BX
IV. AAA
The steps:
I. MOV AX, 39h AX = 0039H
II. MOV BX, 35h BX = 0035H
III. ADD AX, BX 006EH
IV. AAA AX = 0104H AX = 14 in decimal, AF = 1, CF =1
Therefore, AX = 0104H unpacked BCD. CF = 1 indicates that the result is 14 in decimal.
