Verilog Design of Sequential Logic 2023/2024

VERILOG DESIGN of
SEQUENTIAL LOGIC
Dr. Ahmad Fariz Bin Hasan
Electronic Engineering Programme, FKTEN

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Verilog Design of Sequential Logic 2023/2024

• Synchronous sequential logic circuits rely on storage elements for

their operations.
• Flip-flops (FFs) and latches are two commonly used one-bit
storage elements.
• Others as registers, shift registers, and counters.
• Only synchronous sequential logic is considered.

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Verilog Design of Sequential Logic 2023/2024

Latches & Flip-flops

• A latch is a level sensitive memory device (transparent).

o As long as the pulse remains at the active high level, any

changes in the data input will change the state of the latch.
o A flipflop (FF) is an edge-triggered memory device.

• An edge-triggered FF ignores the pulse while it is at a constant

level (non-transparent).
o Triggers only during a transition of the clock signal.

o Could on the positive edge of the clock (posedge), or

negative edge (negedge).

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Verilog Design of Sequential Logic 2023/2024

D Latch

always @ (S or Data_In) Data_in D

latch Q Data_out
if ( S )
s en
Data_out = Data_In;
…

• A latch is inferred because the IF statement is incomplete.

• The notion of implied memory is instantiated in this case.

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Verilog Design of Sequential Logic 2023/2024

Signal Edge Detection in Verilog

• The always blocks are sensitive to the levels of the signals that
appear in the sensitivity list.
• FF changes only as a result of a clock transition of the clock
signal, rather than its level.
• Verilog uses event qualifier posedge and negedge
o E.g. always @ (posedge clock).

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Verilog Design of Sequential Logic 2023/2024

Edge-triggered circuits are described using a sequential

always block
Verilog Design of Sequential Logic 2023/2024

Basic positive-edge triggered D flipflop:

module FF (CLK, d, q) ;
input CLK, d ;
output q ; d D
reg q ; f/f Q q
CLK
always @ (posedge CLK) q
=d;
endmodule

Note: Synthesis tools do not support mixed sensitivity, for example:

always @ (posedge clock or reset).
Verilog Design of Sequential Logic 2023/2024

Blocking and Non-Blocking Assignments

• In a sequential block, blocking assignment statements (=) are

evaluated immediately in the order they are specified.
• Called blocked assignments because a statement must complete
execution (i.e. update memory) before the next statement can
execute.

module shiftregY (A, B, C, D, clk) ;

input D, clk ;
output A, B, C ;
reg A, B, C ; D d q A
always @ (posedge clk) begin
C=D;
B=C; clk
A=B;
end
endmodule

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Verilog Design of Sequential Logic 2023/2024

• A nonblocking assignment (<=) is called concurrent procedural

assignments.
• Allows scheduling of assignments without blocking execution of
the statements that follow.

module shiftregX (A, B, C, D, clk) ; module shiftregY (A, B, C, D, clk) ;

input D, clk ; input D, clk ;
output A, B, C; output A, B, C;
reg A, B, C ; reg A, B, C;

always @ (posedge clk) always @ (posedge clk)

begin begin
A <= B ; C <= D ;
B <= C ; B <= C ;
C <= D ; A <= B ;
end end
endmodule endmodule

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Verilog Design of Sequential Logic 2023/2024

• Executed concurrently rather than sequentially.

• The order has no effect.
• The statements are evaluated using the values when the always
block is entered.
• The result of each non-blocking assignment is not seen until the end
of the always block.

D C B A
d q d q d q

clk

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Verilog Design of Sequential Logic 2023/2024

Recommendation:

When modelling logic that includes edge-triggered register transfers:

• The synchronous (i.e. edge-sensitive) operations be described by
non-blocking assignments
• The combinational logic be described with blocking
assignment statements.

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Verilog Design of Sequential Logic 2023/2024

Example: D flip-flop with asynchronous reset.

module FF2 (CLK, Data_in, RST, Data_out);

input CLK, Data_in, RST; Data_in D
output Data_out; f/f Q Data_out
reg Data_out; clr

always @ (posedge RST or posedge CLK) RST

if ( RST ) Data_out <= 0 ;
else Data_out <= Data_in ;
endmodule

Exercise: Modify to include active-low asynchronous reset (RST) and

preset (PST) inputs.

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Verilog Design of Sequential Logic 2023/2024

Example: Flip-flop with a tristate output

module tri_DFF (CLK, EN, OE, Data_In, Data_Out );

input CLK, EN, OE, Data_in;
output Data_Out ;
Data_In D
reg Temp ; Q
Data_out
EN f/f

CLK
always @ (posedge CLK) C

if (EN) Temp <= Data_In;

OE
assign Data_Out = OE ? Temp : 1‘bz ; // tristate function

endmodule

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Verilog Design of Sequential Logic 2023/2024

Registers

• Registers are just n-bit (n >1) structures consisting of FFs.

• A common clock is used for each FF in the register.

UniMAP-Intel FPGAFlagship Program 14

Verilog Design of Sequential Logic 2023/2024

module reg8 (clock, load, rst, pst, data, Q);

input clock, load ;
input rst, pst ;
pst
input [7:0] data ;
output [7:0] Q ; pre
8
D
reg [7:0] Q ; data
8
load en reg8 q Q
always @ (posedge rst or posedge pst or negedge clock clk
clr
clock)
if (rst) Q <= 0 ;
rst
else if (pst) Q <= 1 ;
else if (load) Q <= data ;
endmodule

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Verilog Design of Sequential Logic 2023/2024

The timing diagram? always @ (posedge rst or posedge pst or negedge

clock)
if (rst) Q <= 0 ;
else if (pst) Q <= 1 ;
else if (load) Q <= data ;

clk

pst
rst

load

data data 1 data 2 data 3

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Verilog Design of Sequential Logic 2023/2024

Shift registers

module shiftLreg8 (clk, rst, en, ldsh, w, always @ (negedge rst or posedge clk)
d, q) ; begin if
input [7:0] d ; ( !rst )
input clk, rst, en, ldsh, w ; q <= 0 ;
output [7:0] q ; else if ( en )
integer k; if ( ldsh )
q <= d;
.... else
begin
q[0] <= w;
for ( k = 1; k <8; k = k+1 )
q[k] <= q[k – 1];
end
end
endmodule

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Verilog Design of Sequential Logic 2023/2024

If replaced with this code, what is now the shift direction?

...
for ( k = 0; k < 7; k = k+1 )
q[k] <= q[k + 1] ;
q[7] <= w ;
...

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Verilog Design of Sequential Logic 2023/2024

Example: 4-bit Universal Shift Register

...
module univShiftReg (MSBin, LSBin, always @ (negedge clock)
s1, s0, clock, rst, DataIn, MSBout, begin
LSBout, DataOut) if ( rst ) // synchronous reset
input MSBin, LSBin, s1, s0 ; DataOut <= 0 ;
input clock, rst ; else
input [3:0] Datain ; case ( {s1, s0} )
output MSBout, LSBout ; 2’b00 : DataOut <= DataOut ; // hold
output [3:0] Dataout ; // shift right
2’b01 : DataOut <= { MSBin,DataOut[3:1] } ;
reg [3:0] Dataout ; // shift left
2’b10 : DataOut <= { DataOut[2:0], LSBin };
assign MSBout = DataOut[3] ; 2’b11 : DataOut <= DataIn ; // parallel load
assign LSBout = DataOut[0] ; endcase
... end
endmodule

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Verilog Design of Sequential Logic 2023/2024

Exercise:
⋅

• Sketch the I/O block diagram of this universal shift register

• Obtain its functional block diagram in terms of FFs and the
associated glue logic.

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Verilog Design of Sequential Logic 2023/2024

Synchronous Counters

Example: A 5-bit upcounter with a parallel load

module upcount5 ( data, Q, clk, rst, ld, inc) ;

input [4:0] data ;
output [4:0] Q ;
input clk, rst ;
input ld, inc ;
reg [4:0] Q ;

always @ ( posedge rst or posedge clk )

if ( rst ) Q <= 0 ;
else if ( ld ) Q <= data ;
else if ( inc ) Q <= Q + 1;
endmodule

UniMA-Intel FPGAFlagship Program 22

Verilog Design of Sequential Logic 2023/2024

Load Reset Load Counting Load Counting

Exercise: Provide the I/O block diagram, and derive the operations
table for this counter.

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Verilog Design of Sequential Logic 2023/2024

Example:

module U_D_counter ( data, count, clk, rst, dir ) ;

input [7:0] data ;
output [7:0] count ;
input clk, rst ;
input [1:0] dir ;
reg [7:0] count ;

always @ ( negedge rst or negedge clk )

if ( rst == 0 ) count <= 8’b00000000 ;
else if (dir == 2’b00 || dir == 2’b11) count <= count ;
else if ( dir == 2’b01 ) count <= count + 1;
else if ( dir == 2’b10 ) count <= count 1;
endmodule
⋅

Explain the counter.

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Verilog Design of Sequential Logic 2023/2024

Simple Sequential Logic

Example:

module PULSER (CLK, PB, PB_Pulse) ;

input CLK, PB ;
output PB_Pulse ;
reg Q1, Q2 ; PB
Q2

always @ (posedge CLK) CLK

begin
Q1 <= PB; PB_Pulse

Q2 <= Q1;
end

assign PB_Pulse = ~ ( ~Q1 | Q2 ) ;

endmodule

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Verilog Design of Sequential Logic 2023/2024

Example: Derive the circuit synthesized from this Verilog code

fragment.

module circuit4_12 (S1, CLK, A, B, C, S3, S2, OU) ;

input S1, CLK ;
input [7:0] A, B, C, S3 ;
output [7:0] S2, OU ;
reg [7:0] S2, OU ;
wire [5:0] TEMP1, TEMP2 ; // internal signals

always @ (posedge CLK)

if ( S1 )
if (TEMP1 < 8) S2 <= A + B;
else S2 <= C;

always @ (TEMP2 or TEMP1 or S3 or A)

if (TEMP2 > TEMP1) OU <= S3 + A;
...
endmodule

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Verilog Design of Sequential Logic 2023/2024

• It is important that the designer have good knowledge on

hardware mapping.
• Depending on the resource constraints, the logic synthesis
will generate one or two adders to execute the two addition
operations.
• A circuit for comparing a variable and a constant is different from
a circuit for comparing two variables.

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