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VLSI Design Assignment-1

This document contains an assignment for a VLSI Design course given to third/fourth year students. It includes 5 questions related to NMOS and PMOS fabrication processes, MOS transistor electrical characteristics, CMOS scaling rules, device scaling factors, sheet resistance, and gate capacitance values for different technology nodes. The assignment is worth a total of 5 marks and is due on January 27th, 2024. It relates to course outcomes about understanding fabrication processes and applying circuit concepts in different technologies.

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177 views1 page

VLSI Design Assignment-1

This document contains an assignment for a VLSI Design course given to third/fourth year students. It includes 5 questions related to NMOS and PMOS fabrication processes, MOS transistor electrical characteristics, CMOS scaling rules, device scaling factors, sheet resistance, and gate capacitance values for different technology nodes. The assignment is worth a total of 5 marks and is due on January 27th, 2024. It relates to course outcomes about understanding fabrication processes and applying circuit concepts in different technologies.

Uploaded by

educational9hub
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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SIR C R REDDY COLLEGE OF ENGINEERING, ELURU

DEPARTMENT OF ELECTONICS & COMMUNICATION ENGINEERING


ASSIGNMENT-I
nd
Class: III/IV, II sem , ECE-A,B,C A.Y: 2023-24
Max. Marks: 5. Subject : VLSI Design (R2032043)
Date: 12-01-2024. Submission date: 27-01-2024

S.No. QUESTION MARKS CO RBT


Q1 Explain the N-MOS and P-MOS fabrication process steps with neat
diagrams. 5 CO1 K1
Q2 Derive an Expression for drain current in both resistive region and
saturation region. 5 CO1 K1
Q3 Explain 2µm Double Metal, Double poly CMOS / BiCMOS Rules.
5 CO2 K2
Q4 What are the different scaling models and scaling factors? Derive scaling 5
factors for different device parameters. CO2 K2

Q5 Derive the expression for Sheet Resistance. Apply the concept to MOS
transistors and inverter. 5 CO2 K2
Evaluate the standard value of capacitance ( □𝐶𝑔)in different micron
technology
Technology 5µm(PF/µm2) 2µm (PF/µm2) 1.2µm (PF/µm2)
Gate-channel
capacitance 4x10-4 8x10-4 16x10-4

CO.No Course Outcomes Bloom’s Taxonomy Level


CO1 Understand the basic concepts of an various IC’s fabrication process Knowledge, Understand
methods and able to know about electrical properties of MOS device. (Level-1,2).

CO2 Understand and Apply the basic circuit concepts in different technologies. Knowledge, Understand ,
Analyze the impact of scaling parameters of MOSFETs
Apply (Level-1, 2).

CO3 Implement the basic building blocks of analog IC design. Knowledge, Understand
,Apply(Level-1,2,3)

CO4 Analyze the CMOS Combinational and Sequential logic circuit design. Knowledge, Understand (Level
1,2)
CO5 Understand FPGA and basic concepts of advance technologies of High-K Knowledge, Understand ,
,Metal gate, FinFET and TFET Apply, Create (Level -1,2,3,6)

KNOWLEDGE LEVELS (RBT)


REMEMBERING UNDERSTANDING APPLYING ANALYZING EVALUATING CREATING

K1 K2 K3 K4 K5 K6

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