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V
I
T Module 5 - Digital Systems

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DIGITAL/ANALOG SIGNALS
V
 Analog Circuits
I  The continuously changing input voltage produces a continuously changing
T output voltage.
 Analog device
 The one in which data is represented by physical variables.
 Digital circuits
 Designed for two-state operation
 The output voltage has only two states (values), either LOW or HIGH.
 Digital operation is with a square-wave input
 Digital device
 The one in which data is represented by numerical quantities.

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DIGITAL/ANALOG SIGNALS
V
 ADVANTAGES OF DIGITAL CIRCUITS.
I  Changes in component values have very little effect on digital signals.
T  The voltage anywhere in a digital circuit will always be in one state or the other, so that there is
 Noise and other interfering signals have very little effect on digital signals.

very little chance of confusion or error.

 Digital signals are ideally suited for logic use, and for counting in the binary scale.
 Information storage is easy.
 Operation can be programmed.
 More digital circuitry can be fabricated on IC chips.
 LIMITATIONS OF DIGITAL CIRCUITS
 Convert the real-world analog inputs to digital form (Analog-to-Digital conversion, ADC).
 Process (operate on) the digital information.
 Convert the digital outputs back to real-world Analog form (Digital-to-Analog conversion, DAC)

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V
I
T Number Systems

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Common Number Systems

V
I System Base Symbols
T Decimal 10 0, 1, 2, 3, 4, 5,6, 7, 8, 9
Binary 2 0, 1
Octal 8 0, 1, 2, 3, 4, 5,6, 7
Hexadecimal 16 0, 1, 2, 3, 4, 5,6, 7, 8, 9, A, B, C, D, E, F

WHY BINARY ?

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Quantities/Counting
V
I
Dec Bin Oct Hex Dec Bin Oct Hex Dec Bin Oct Hex
T
0 0 0 0 8 1000 10 8 16 10000 20 10
1 1 1 1 9 1001 11 9 17 10001 21 11
2 10 2 2 10 1010 12 A 18 10010 22 12
3 11 3 3 11 1011 13 B 19 10011 23 13
4 100 4 4 12 1100 14 C 20 10100 24 14
5 101 5 5 13 1101 15 D 21 10101 25 15
6 110 6 6 14 1110 16 E 22 10110 26 16
7 111 7 7 15 1111 17 F 23 10111 27 17

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Conversion Among Bases

V
I
T • The possibilities:

Decimal Octal

Binary Hexadecimal

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Quick Example
V
I
T

2510 = 110012 = 318 = 1916

Base

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V Decimal Numbers
I
T Weight

12510 => 5 x 100= 5

2 x 101= 20
1 x 102= 100
125

Base

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V Decimal to Binary
I • Technique 12510 = ?2
T • Divide by two, keep track
of the remainder 2 125
62 1
• First remainder is bit 0 2
(LSB, least-significant bit) 2 31 0

• Second remainder is bit 1 2 15 1

2 7 1
• Etc.
2 3 1
1 1
2
0 1

12510 = 11111012

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V Binary to Decimal
I
Bit “0”
T • Technique
• Multiply each bit by 2n,
where n is the “weight” of
the bit 1010112 => 1 x 20 = 1
1 x 21 = 2
• The weight is the position of
the bit, starting from 0 on 0 x 22 = 0
the right 1 x 23 = 8
• Add the results 0 x 24 = 0
1 x 25 = 32
4310

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Decimal to Octal
V
I
T • Technique 123410 = ?8

• Divide by 8
• Keep track of the remainder 8 1234
8 154 2
8 19 2
8 2 3
0 2

123410 = 23228

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V Octal to Decimal
I
T • Technique n 7248 => 4 x 80 = 4
• Multiply each bit by 8 , where n is
2 x 81 = 16
the “weight” of the bit 7 x 82 = 448
• The weight is the position of the 46810
bit, starting from 0 on the right
• Add the results

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V Decimal to Hexadecimal
I
T • Technique 123410 = ?16

• Divide by 16
• Keep track of the 16 1234
remainder 77 2
16
16 4 13 = D
0 4

123410 = 4D216

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Hexadecimal to Decimal
V
I
T • Technique
• Multiply each bit by 16n,
where n is the “weight” of the
ABC16 => C x 160 = 12 x 1 = 12
bit B x 161 = 11 x 16 = 176
• The weight is the position of A x 162 = 10 x 256 = 2560
the bit, starting from 0 on the 274810
right
• Add the results

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V Octal to Binary
I
T • Technique 7058 = ?2

• Convert each octal digit to

a 3-bit equivalent binary 7 0 5
representation

111 000 101

7058 = 1110001012

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V Binary to Octal
I
10110101112 = ?8
T • Technique
• Group bits in threes,
1 011 010 111
starting on right
• Convert to octal digits

1 3 2 7

10110101112 = 13278

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V Hexadecimal to Binary
I
T • Technique 10AF 16 = ?2

• Convert each hexadecimal

digit to a 4-bit equivalent 1 0 A F
binary representation

0001 0000 1010 1111

10AF16 = 00010000101011112

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V Binary to Hexadecimal
I
T• Technique
10101110112 = ?16

• Group bits in fours, starting on right

• Convert to hexadecimal digits 10 1011 1011

2 B B

10101110112 = 2BB16

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V Octal to Hexadecimal
I
T • Technique 1076 8 = ?16

• Use binary as an
intermediary 1 0 7 6

001 000 111 110

2 3 E

10768 = 23E16

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V Hexadecimal to Octal
I 1F0C16 = ?8

T • Technique
• Use binary as an intermediary 1 F 0 C

0001 1111 0000 1100

1 7 4 1 4

1F0C16 = 174148

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V Exercise – Convert ...

I Hexa-
T Decimal Binary Octal decimal
33
1110101
703
1AF

Don’t use calculator!

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V Answer

I Hexa-
T Decimal Binary Octal decimal
33 100001 41 21
117 1110101 165 75
451 111000011 703 1C3
431 110101111 657 1AF

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V Fractions
I
T • Decimal to decimal (just for logic)

3.14 => 4 x 10-2 = 0.04

1 x 10-1 = 0.1
3 x 100 = 3
3.14

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V Fractions
I
T • Binary to decimal
10.1011 => 1 x 2-4 = 0.0625
1 x 2-3 = 0.125
0 x 2-2 = 0.0
1 x 2-1 = 0.5
0 x 20 = 0.0
1 x 21 = 2.0
2.6875

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V Fractions
I • Decimal to binary .14579

T 3.14579
x
0.29158
2

x 2
0.58316
x 2
1.16632
x 2
0.33264
x 2
0.66528
x 2
1.33056
11.001001...
etc.

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V Exercise – Convert ...

I Hexa-
T Decimal Binary Octal decimal
29.8
101.1101
3.07
C.82
Don’t use calculator!

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V Answer

I Hexa-
T Decimal Binary Octal decimal
29.8 11101.110011… 35.63… 1D.CC…
5.8125 101.1101 5.64 5.D
3.109375 11.000111 3.07 3.1C
12.5078125 1100.10000010 14.404 C.82

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V
Binary-Coded Decimal (BCD), Excess 3 Code
I Digit Bit pattern Excess 3
T • Four bits per digit 8421 Code
0 0000 0011
Note: the following Note: the following 1 0001 0100
bit patterns are not bit patterns are not
used for BCD: used for Excess 3: 2 0010 0101
1010 0000 3 0011 0110
1011 0001 4 0100 0111
1100 0010
1101 1101 5 0101 1000
1110 1110 6 0110 1001
1111 1111
7 0111 1010
8 1000 1011
9 1001 1100
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Other Weighted Binary Codes

V
I Digit 2421 84-2-1

T 0 0000 0000
1 0001 0111
2 0010 0110
3 0011 0101
4 0100 0100
5 0101 1011
6 0110 1010
7 0111 1001
8 1110 1000
9 1111 1111

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Gray Code
V
I Digit Gray Code Digit Gray Code

T 0 0000 8 1100
1 0001 9 1101
2 0011 10 1111
3 0010 11 1110
4 0110 12 1010
5 0111 13 1011
6 0101 14 1001
7 0100 15 1000

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V Example
I
T • 709310 = ? (in BCD)

7 0 9 3

0111 0000 1001 0011

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V Signed Integers
I • Previous examples were for “unsigned integers” (positive values
T only!)
• Must also have a mechanism to represent “signed integers” (positive
and negative values!)
• E.g., -510 = ?2
• Two common schemes: sign-magnitude and twos complement

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V Sign-Magnitude
I
T • Extra bit on left to represent sign
• 0 = positive value
• 1 = negative value
• E.g., 6-bit sign-magnitude representation of +5 and –5:

+5: 0 0 0 1 0 1 -5: 1 0 0 1 0 1

+ve 5 -ve 5

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V
Ranges
I Binary
Unsigned Sign-magnitude
T No. of bits Min Max Min Max
1 0 1
2 0 3 -1 1
3 0 7 -3 3
4 0 15 -7 7
5 0 31 -15 15
6 0 63 -31 31
n n-1 n-1
In General, n bits 0 2 -1 -(2 - 1) 2 -1

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Complement of Numbers
V
I • Complements are used in digital computers to simplify the subtraction operation.

T Complement for base – r system

Radix Complement Diminished radix complement

r’s complement (r-1)’s complement

• For Binary numbers r = 2

• 1’s complement and 2’s complement
• For Decimal numbers r = 10
• 9’s complement and 10’s complement

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Diminished Radix Complement - (r-1)’s complement

V
I • For a given number N containing n digits, (r-1)’s complement is defined as (rn-1) -N
• 1’scomplement of (101100)2
T = (26-1) – (101100) 2
= (1000000 – 1) - (101100) 2 = (111111) 2 - (101100) 2
= (010011)2
• 9’s complement of (546700)10
= (106-1) – (546700) 10
= (1000000 – 1) - (546700) 10 = (999999) 10 - (546700) 10
= (453299)10

Note : 1’s complement of a binary number is formed by changing 1’s to 0’s and 0’s to 1’s
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Radix Complement - r’s complement

V
I • For a given number N containing n digits, r’s complement is defined as rn-N for N ≠
0 and 0 for N = 0. rn-N = [(rn-1) – N + 1]
T • Most common scheme of representing negative numbers.

• 2’s complement of (101100)2

= (010011)2 + 1
= (010100) 2

• 10’s complement of (546700)10

= (453299)10 + 1
= (453300)10

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V Twos Complement Example

I
• Represent -5 in binary using 2’s complement notation
T 1. Decide on the number of bits 6 (for example)

2. Find the binary representation of the +ve value in 6 bits

000101

3. Flip all the bits (1’s complement) +5

111010

4. Add 1 (2’s complement) 111010

+ 1
111011 -5

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Sign Bit
V
I • In 2’s complement notation, the MSB is the sign bit (as with sign-
magnitude notation)
T • 0 = positive value
• 1 = negative value

+5: 0 0 0 1 0 1 -5: 1 1 1 0 1 1

+ve 5 -ve

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V “Complementary” Notation
I
T • Conversions between positive and negative numbers are easy
• For binary (base 2)…

2’s C

-ve
+ve

2’s C

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V Example
+5 0 0 0 1 0 1
I
T 2’s C
1 1 1 0 1 0
+ 1

-5 1 1 1 0 1 1

0 0 0 1 0 0
2’s C
+ 1

+5 0 0 0 1 0 1

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V Exercise – 2’s C conversions

I
T • Represent -20 as an 8-bit binary number in 2’s complement notation?
• Answer:

• 1100011 is a 7-bit binary number in 2’s complement notation. What

is the decimal value?
• Answer:

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V Answer

I
T • Represent -20 as an 8-bit binary number in 2’s complement notation?
• Answer: 11101100

• 1100011 is a 7-bit binary number in 2’s complement notation. What

is the decimal value?
• Answer: -29

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Ranges
V
I Binary
No. of bits 2’s complement
T Unsigned Sign-magnitude
Min Max Min Max Min Max
1 0 1
2 0 3 -1 1 -2 1
3 0 7 -3 3 -4 3
4 0 15 -7 7 -8 7
5 0 31 -15 15 -16 15
6 0 63 -31 31 -32 31

n n-1 n-1 n-1 n-1

n 0 2 -1 -(2 - 1) 2 -1 -2 2 -1
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V What is -5 plus +5?

I
T • Zero, of course, but let’s see
Sign-magnitude Twos-complement

-5: 10000101 -5: 11111011

+5: +00000101 +5: +00000101
10001010 00000000

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2’s Complement Subtraction

V
• Easy
I
• Just subtract, well … actually … just add!
T • If a carry is generated, discard the carry.
• If the subtrahend is larger than the minuend, then no carry is generated.
• The answer obtained is in 2’s complement and is negative.
• To get a true answer take the 2’s complement of the number and change
the sign.
A – B = A + (-B)

add 2’s complement of B

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V What is 10 subtract 3 using 2’s complement?

I
T 10 – 3 = 10 + (-3) = 7

+3: 000011
001010
1s C: 111100
+1: 1 +111101
-3: 111101
000111

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V What is 3 subtract 10 using 2’s complement?

I
T 3 – 10 = 3 + (-10) = -7

+10: 001010
000011
1s C: 110101
+1: 1 +110110
-10: 110110
111001
1s C : 000110
+1 : 1
2s C : 000111

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1’s Complement Subtraction

V
• Easy
I
• Just subtract, well … actually … just add!
T • If a carry is generated, remove the carry, add it to the result.
• If the subtrahend is larger than the minuend, then no carry is
• generated.
• The answer obtained is 1’s complement of the true result and negative.
• To get a true answer take the 1’s complement of the number and change
the sign. A – B = A + (-B)

add 1’s complement of B

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V What is 10 subtract 3 using 1’s complement?

I
T 10 – 3 = 10 + (-3) = 7

+3: 000011 001010

1s C: 111100 +111100
1000110 +

carry 1
000111

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V What is 3 subtract 10 using 1’s complement?

I
T 3 – 10 = 3 + (-10) = -7

+10: 001010 000011

1s C: 110101 +110101
111000
1s C : 000111

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V Exercises – Complementary Notations

I
T • What is the 3-digit 10’s complement of 247?
• Answer:

• What is the 3-digit 10’s complement of 17?

• Answer:

• 777 is a 10’s complement representation of what decimal value?

• Answer:

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V Answer

I
T • What is the 3-digit 10’s complement of 247?
• Answer: 753

• What is the 3-digit 10’s complement of 17?

• Answer: 983

• 777 is a 10’s complement representation of what decimal value?

• Answer: 223

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V
I
Logic Gates
T

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Boolean Constants and Variables

V  Logical statements can have either two values yes or no, true or false, 0 or 1.
I  Boolean 0 and 1 do not represent actual numbers but instead represent the
state, or logic level.
T

Logic 0 Logic 1
False True
Off On
Low High
No Yes
Open switch Closed switch

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Truth Tables
 A truth table is a means for describing how a logic circuit’s output depends
V on the logic levels present at the circuit’s inputs.
I
T
Inputs Output
A B X
A
1 1 1
? x
0 1 0
B
1 0 0
0 0 0

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Basic Logic Operators

V
I OR
T AND
NOT

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OR Operation
V  Boolean expression for the OR operation:
I x =A + B
T  The above expression is read as “x equals A OR B”

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AND Operation
V
 Boolean expression for the AND operation:
I x =A B
T  The above expression is read as “x equals A AND B”

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NOT Operation
V • The NOT operation is an unary operation, taking only one input variable.
I • Boolean expression for the NOT operation:
x= 𝐴
T • The above expression is read as “x equals the inverse of A”
• Also known as inversion or complementation.
• Can also be expressed as: A’

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NAND Gate
V  Boolean expression for the NAND operation:
I
T x=𝐴𝐵

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NOR Gate • Boolean expression for the NOR operation:

V
I x=𝐴 + 𝐵
T

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XOR Gate
V  An XOR gate accepts two input signals
I  If both are the same, the output is 0; otherwise, the output is 1
T

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Boolean Theorems and Laws

V • x 0= 0 Fallacy
I • x+1= 1 Tautology
T • x x= x Indempotence Law
• x+x= x Indempotence Law
• x x= 0 Complementarity Law
• x+x= 1 Complementarity Law
• x”= x Involution Law
• x+0= x
• x 1= x

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Boolean Theorems and Laws

V
I  x+y = y+x // Commutative Law
x y = y x
T
 x+(y+z)= (x+y)+z= x+y+z // Associative Law
 x(yz)= (xy)z = xyz

 x(y+z)= xy+xz // Distributive Law

 (w+x)(y+z)= wy+xy+wz+xz

 x + x’y = x+y // Absorption Law

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De-Morgan’s Theorems
V
I• (x + y)’= x’y’
• Implications and alternative symbol for NOR function
T• (xy)’= x’+ y’
• Implications and alternative symbol for NAND function
• Process of Demorgan:
(i) Complement entire function
(ii) Change all AND to OR and all OR to AND
(iii) Complement each of the individual variables

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Universal Gate - NAND

V
I
T

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Universal Gate - NAND NOT X X  X (Before Bubble)

VAND XY
X ZX
I
X
Y
ZXYXY X Z

T X Y Z 0
1
1
0
Equivalent to Inverter
NAND Gate Inverter 0 0 0
0 1 0
Equivalent to AND Gate
1 0 0
1 1 1
OR X
X Y Z
X Y
0 0 0
Z  XY  XY  XY 0 1 1
Y Equivalent to OR Gate
1 0 1
1 1 1
Inverters NAND Gate

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Universal Gate - NAND

V
I AND OR INVERTER
T

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Universal Gate - NOR

V
I
T

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X  X  X (Before Bubble)
Universal Gate - NOR NOT

VAND X X ZX X Z

XI
Y 0 1
Equivalent
1 0
Z XYXY XY to Inverter

YT X Y Z
0 0 0
“Inverters” NOR Gate 0 1 0
Equivalent to AND Gate
1 0 0
1 1 1
OR
XY
X X Y Z
Z  XY  XY
Y 0 0 0
0 1 1
NOR Gate “Inverter” Equivalent to OR Gate
1 0 1
1 1 1

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Universal Gate - NOR

V
I AND OR INVERTER
T

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Logic gate – PIN diagram

V
I
T

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