EXP.
NO: 1 Design a Testbench for 2x1Mux
Using Gates
AIM:
To design a Testbench for 2:1 MUX using gated in System Verilog.
APPARATUS REQUIRED:
❖ Personal computer
❖ Modelsim Software
PROCEDURE:
⮚ Write the System Verilog code for the logic design.
⮚ Enter the System Verilog code in Modelsim Editor.
⮚ Save and simulate the program.
⮚ Simulate the program after creating the test bench waveform and verify the functional design.
Steps to simulate.
1. Create a new project: Start by opening ModelSim and creating a new project. Click on the "File"
menu, then "New", and then select "Project". Give your project a name and select a working directory
for the project.
2. Add design files: Add your design files to the project by clicking on the "Add" button in the "Design"
tab of the "Project" window. Select your design files and click "OK".
3. Compile design: After adding your design files to the project, compile your design by clicking on the
"Compile" button in the "Design" tab of the "Project" window. This will check the syntax of your
design and generate a compiled version of the design.
4. Create a testbench: Create a testbench to verify the functionality of your design. To create a testbench,
click on the "File" menu, then "New", and select "Text Editor". Create a new file and write your
testbench code in this file.
5. Simulate the design: Once you have created your testbench, simulate your design by clicking on the
"Simulate" button in the "Design" tab of the "Project" window. This will open the Modelsim
simulation window.
6. Analyze simulation results: Analyze the simulation results to verify the functionality of your design.
You can view waveforms and other simulation data by using the various tools available in the
Modelsim simulation window.
7. Debug errors: If any errors or warnings are generated during the simulation, debug them by analyzing
the simulation results and modifying your design or testbench as necessary.
8. Save and export results: Once you are satisfied with the simulation results, save your work and export
any relevant results, such as waveforms or log files.
9. Close the project: Finally, close your project by clicking on the "File" menu and selecting "Close
Project". This will save your project and any changes you have made to it.
PROGRAM:
2:1 MUX
module mux_2x1_gate (
input a, b, sel,
output out
);
wire not_sel;
wire and1, and2;
wire or1;
assign not_sel = ~sel;
assign and1 = a & not_sel;
assign and2 = b & sel;
assign or1 = and1 | and2;
assign out = or1;
endmodule
module tb_mux_2x1_gate;
// Instantiate the DUT
mux_2x1_gate mux_inst (
.a(a),
.b(b),
.sel(sel),
.out(out)
);
// Define inputs and outputs
reg a, b, sel;
wire out;
initial begin
// Test case 1: sel = 0, a = 0, b = 0
sel = 0;
a = 0;
b = 0;
#10;
if (out !== 0) $display("Test case 1 failed");
// Test case 2: sel = 0, a = 0, b = 1
sel = 0;
a = 0;
b = 1;
#10;
if (out !== 0) $display("Test case 2 failed");
// Test case 3: sel = 0, a = 1, b = 0
sel = 0;
a = 1;
b = 0;
#10;
if (out !== 1) $display("Test case 3 failed");
// Test case 4: sel = 0, a = 1, b = 1
sel = 0;
a = 1;
b = 1;
#10;
if (out !== 1) $display("Test case 4 failed");
// Test case 5: sel = 1, a = 0, b = 0
sel = 1;
a = 0;
b = 0;
#10;
if (out !== 0) $display("Test case 5 failed");
// Test case 6: sel = 1, a = 0, b = 1
sel = 1;
a = 0;
b = 1;
#10;
if (out !== 1) $display("Test case 6 failed");
// Test case 7: sel = 1, a = 1, b = 0
sel = 1;
a = 1;
b = 0;
#10;
if (out !== 0) $display("Test case 7 failed");
// Test case 8: sel = 1, a = 1, b = 1
sel = 1;
a = 1;
b = 1;
#10;
if (out !== 1) $display("Test case 8 failed");
$display("All test cases passed");
end
endmodule
Program 2:
module mux_2to1(input logic a, b, select, output logic out);
always @(*) begin
if (select == 1'b0) begin
out = a;
end else begin
out = b;
end
end
endmodule
module tb_mux_2to1_gated_input;
// Inputs
logic a, b, select;
// Outputs
logic out;
// Instantiate the DUT
mux_2to1 uut(a, b, select, out);
// Stimulus
initial begin
// Test case 1: select input 0
a = 1'b1;
b = 1'b0;
select = 1'b0;
#10;
if (out !== 1'b1) $error("Test case 1 failed. Expected output to be 1.");
// Test case 2: select input 1
a = 1'b1;
b = 1'b0;
select = 1'b1;
#10;
if (out !== 1'b0) $error("Test case 2 failed. Expected output to be 0.");
// Test case 3: select input 0
a = 1'b0;
b = 1'b1;
select = 1'b0;
#10;
if (out !== 1'b0) $error("Test case 3 failed. Expected output to be 0.");
// Test case 4: select input 1
a = 1'b0;
b = 1'b1;
select = 1'b1;
#10;
if (out !== 1'b1) $error("Test case 4 failed. Expected output to be 1.");
$display("All test cases passed.");
end
endmodule
Simulator Output:
In this testbench, we first define a mux_2to1 module which implements the 2:1 multiplexer using gated
inputs. Then we create a testbench module tb_mux_2to1_gated_input where we instantiate the DUT
mux_2to1, provide inputs a, b, and select, and capture the output out.
In the stimulus section, we define four test cases where we set the input values and simulate for some time
using #10. After the simulation, we check the output out against the expected value using $error and display a
message using $display.
Truth Table:
Test bench waveform:
RESULT:
EX NO: IMPLEMENTATION OF SCOREBOARD FOR A SIMPLE DUT
AIM:
To implement a scoreboard for a simple DUT using system verilog.
APPARATUS REQUIRED:
❖ Personal computer
❖ Model Sim software
PROCEDURE:
⮚ Write the System Verilog code for the logic design.
⮚ Enter the System Verilog code in Modelsim Editor.
⮚ Save and simulate the program.
⮚ Simulate the program after creating the test bench waveform and verify the functional design.
Steps to simulate.
1. Create a new project: Start by opening ModelSim and creating a new project. Click on the "File"
menu, then "New", and then select "Project". Give your project a name and select a working directory
for the project.
2. Add design files: Add your design files to the project by clicking on the "Add" button in the "Design"
tab of the "Project" window. Select your design files and click "OK".
3. Compile design: After adding your design files to the project, compile your design by clicking on the
"Compile" button in the "Design" tab of the "Project" window. This will check the syntax of your
design and generate a compiled version of the design.
4. Create a testbench: Create a testbench to verify the functionality of your design. To create a testbench,
click on the "File" menu, then "New", and select "Text Editor". Create a new file and write your
testbench code in this file.
5. Simulate the design: Once you have created your testbench, simulate your design by clicking on the
"Simulate" button in the "Design" tab of the "Project" window. This will open the ModelSim
simulation window.
6. Analyze simulation results: Analyze the simulation results to verify the functionality of your design.
You can view waveforms and other simulation data by using the various tools available in the
ModelSim simulation window.
7. Debug errors: If any errors or warnings are generated during the simulation, debug them by analyzing
the simulation results and modifying your design or testbench as necessary.
8. Save and export results: Once you are satisfied with the simulation results, save your work and export
any relevant results, such as waveforms or log files.
9. Close the project: Finally, close your project by clicking on the "File" menu and selecting "Close
Project". This will save your project and any changes you have made to it.
PROGRAM 1:
// Scoreboard Module Definition
module scoreboard #(parameter int DATA_WIDTH = 8) (
input logic clk, rst_n,
input logic [DATA_WIDTH-1:0] dut_output,
input logic [DATA_WIDTH-1:0] expected_output,
output logic [DATA_WIDTH-1:0] data_mismatch
);
logic [DATA_WIDTH-1:0] scoreboard_data_mismatch;
// Comparator module to compare DUT output with expected output
comparator #(.DATA_WIDTH(DATA_WIDTH)) comp (
.a(dut_output),
.b(expected_output),
.eq(scoreboard_data_mismatch)
);
always_ff @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
data_mismatch <= 0;
end else begin
data_mismatch <= scoreboard_data_mismatch;
end
end
endmodule
// Comparator Module Definition
module comparator #(parameter int DATA_WIDTH = 8) (
input logic [DATA_WIDTH-1:0] a,
input logic [DATA_WIDTH-1:0] b,
output logic eq
);
assign eq = (a == b) ? 1'b1 : 1'b0;
endmodule
// Define the scoreboard module
module scoreboard;
// Inputs
input logic [7:0] DUT_output;
input logic [7:0] reference_output;
// Output
output logic score;
// Register to hold the score
logic [7:0] score_register;
// Scoreboard logic
always_comb begin
if (DUT_output == reference_output) begin
score_register = score_register + 1;
end
else begin
score_register = score_register - 1;
end
end
// Assign the scoreboard output
assign score = (score_register == 255);
endmodule
System verilog Test Bench:
Simulator Output:
Here, we have a scoreboard module that takes in the DUT output and the expected output, and compares
them using a comparator module. If there is a data mismatch, the scoreboard sets its own data_mismatch
output to 1.
The comparator module is a simple module that checks if two inputs are equal, and sets the output eq to 1 if
they are equal, otherwise to 0.
Program 2:
// Scoreboard module
module scoreboard();
logic [31:0] in_a_score;
logic [31:0] in_b_score;
logic [31:0] out_score;
// Monitor inputs and output of DUT
always @(posedge clk) begin
in_a_score <= in_a;
in_b_score <= in_b;
out_score <= out;
end
// Compare output of DUT with expected result
always @(posedge clk) begin
if (out_score != in_a_score + in_b_score) begin
$error("Scoreboard: Incorrect output received. Expected %d, received %d",
in_a_score + in_b_score, out_score);
end
end
endmodule
// DUT module
module dut(
input logic [31:0] in_a,
input logic [31:0] in_b,
output logic [31:0] out
);
// Perform simple addition operation
always @(in_a, in_b) begin
out <= in_a + in_b;
end
endmodule
// Testbench module
module testbench();
logic [31:0] in_a;
logic [31:0] in_b;
logic [31:0] out;
// Instantiate DUT and scoreboard
dut dut_inst(
.in_a(in_a),
.in_b(in_b),
.out(out)
);
scoreboard sb_inst();
// Generate input stimuli
initial begin
in_a = 10;
in_b = 20;
#5;
in_a = 15;
in_b = 25;
#5;
// Add more input stimuli as needed
end
endmodule
Simulator Output:
Here, the scoreboard module monitors the inputs and output of the DUT and compares the output with the
expected result (the sum of the inputs). If the output does not match the expected result, an error message is
displayed. The dut module performs a simple addition operation on the inputs, and the testbench module
generates the input stimuli for the DUT.
RESULT:
EX NO:3 IMPLEMENTATION AND TESTING OF SEMAPHORE FOR A SIMPLE DUT
AIM:
To implement and testing of Semaphore for a Simple DUT.
APPARATUS REQUIRED:
❖ Personal computer
❖ Model Sim software
PROCEDURE:
⮚ Write the System Verilog code for the logic design.
⮚ Enter the System Verilog code in Modelsim Editor.
⮚ Save and simulate the program.
⮚ Simulate the program after creating the test bench waveform and verify the functional design.
Steps to simulate.
1. Create a new project: Start by opening ModelSim and creating a new project. Click on the "File"
menu, then "New", and then select "Project". Give your project a name and select a working directory
for the project.
2. Add design files: Add your design files to the project by clicking on the "Add" button in the "Design"
tab of the "Project" window. Select your design files and click "OK".
3. Compile design: After adding your design files to the project, compile your design by clicking on the
"Compile" button in the "Design" tab of the "Project" window. This will check the syntax of your
design and generate a compiled version of the design.
4. Create a testbench: Create a testbench to verify the functionality of your design. To create a testbench,
click on the "File" menu, then "New", and select "Text Editor". Create a new file and write your
testbench code in this file.
5. Simulate the design: Once you have created your testbench, simulate your design by clicking on the
"Simulate" button in the "Design" tab of the "Project" window. This will open the ModelSim
simulation window.
6. Analyze simulation results: Analyze the simulation results to verify the functionality of your design.
You can view waveforms and other simulation data by using the various tools available in the
ModelSim simulation window.
7. Debug errors: If any errors or warnings are generated during the simulation, debug them by analyzing
the simulation results and modifying your design or testbench as necessary.
8. Save and export results: Once you are satisfied with the simulation results, save your work and export
any relevant results, such as waveforms or log files.
9. Close the project: Finally, close your project by clicking on the "File" menu and selecting "Close
Project". This will save your project and any changes you have made to it.
PROGRAM 1:
Two processes accessing the same resource
In the example below,
semaphore sema is created with the 1 key, two processes are accessing the display method at the same
time, but only one process will get the semaphore key and the other process will wait till it gets the key.
module semaphore_ex;
semaphore sema; //declaring semaphore sema
initial begin
sema=new(1); //creating sema with '1' key
fork
display(); //process-1
display(); //process-2
join
end
//display method
task automatic display();
sema.get(); //getting '1' key from sema
$display($time,"\tCurrent Simulation Time");
#30;
sema.put(); //putting '1' key to sema
endtask
endmodule
Simulator Output:
0 Current Simulation Time
30 Current Simulation Time
Program 2:
Creating semaphore with ‘1’ key, putting more number of keys back to the semaphore.
module semaphore_ex;
semaphore sema; //declaring semaphore sema
initial begin
sema=new(1); //creating sema with '1' keys
fork
display(1); //process-1
display(2); //process-2
display(3); //process-3
join
end
//display method
task automatic display(int key);
sema.get(key); //getting 'key' number of keys from sema
$display($time,"\tCurrent Simulation Time, Got %0d keys",key);
#30;
sema.put(key+1); //putting 'key' number of keys to sema
endtask
endmodule
Simulator Output:
0 Current Simulation Time, Got 1 keys
30 Current Simulation Time, Got 2 keys
60 Current Simulation Time, Got 3 keys
RESULT:
EX NO:4 IMPLEMENTATION OF A MAILBOX BY ALLOCATING MEMORY
AIM:
To implement a Mailbox using System Verilog.
APPARATUS REQUIRED:
❖ Personal computer
❖ Model Sim software
PROCEDURE:
⮚ Write the System Verilog code for the logic design.
⮚ Enter the System Verilog code in Modelsim Editor.
⮚ Save and simulate the program.
⮚ Simulate the program after creating the test bench waveform and verify the functional design.
Steps to simulate.
1. Create a new project: Start by opening ModelSim and creating a new project. Click on the "File"
menu, then "New", and then select "Project". Give your project a name and select a working directory
for the project.
2. Add design files: Add your design files to the project by clicking on the "Add" button in the "Design"
tab of the "Project" window. Select your design files and click "OK".
3. Compile design: After adding your design files to the project, compile your design by clicking on the
"Compile" button in the "Design" tab of the "Project" window. This will check the syntax of your
design and generate a compiled version of the design.
4. Create a testbench: Create a testbench to verify the functionality of your design. To create a testbench,
click on the "File" menu, then "New", and select "Text Editor". Create a new file and write your
testbench code in this file.
5. Simulate the design: Once you have created your testbench, simulate your design by clicking on the
"Simulate" button in the "Design" tab of the "Project" window. This will open the ModelSim
simulation window.
6. Analyze simulation results: Analyze the simulation results to verify the functionality of your design.
You can view waveforms and other simulation data by using the various tools available in the
ModelSim simulation window.
7. Debug errors: If any errors or warnings are generated during the simulation, debug them by analyzing
the simulation results and modifying your design or testbench as necessary.
8. Save and export results: Once you are satisfied with the simulation results, save your work and export
any relevant results, such as waveforms or log files.
9. Close the project: Finally, close your project by clicking on the "File" menu and selecting "Close
Project". This will save your project and any changes you have made to it.
PROGRAM 1:
Mailbox is used for communication between generator and driver.
Process-1(Generator class) will generate (created and randomize) the packet and put into the mailbox
mb_box
Process-2(Driver class) gets the generated packet from the mailbox and display the fields
//-------------------------------------------------------------------------
// Packet
//-------------------------------------------------------------------------
class packet;
rand bit [7:0] addr;
rand bit [7:0] data;
//Displaying randomized values
function void post_randomize();
$display("Packet::Packet Generated");
$display("Packet::Addr=%0d,Data=%0d",addr,data);
endfunction
endclass
//-------------------------------------------------------------------------
//Generator - Generates the transaction packet and send to driver
//-------------------------------------------------------------------------
class generator;
packet pkt;
mailbox m_box;
//constructor, getting mailbox handle
function new(mailbox m_box);
this.m_box = m_box;
endfunction
task run;
repeat(2) begin
pkt = new();
pkt.randomize(); //generating packet
m_box.put(pkt); //putting packet into mailbox
$display("Generator::Packet Put into Mailbox");
#5;
end
endtask
endclass
//-------------------------------------------------------------------------
// Driver - Gets the packet from generator and display's the packet items
//-------------------------------------------------------------------------
class driver;
packet pkt;
mailbox m_box;
//constructor, getting mailbox handle
function new(mailbox m_box);
this.m_box = m_box;
endfunction
task run;
repeat(2) begin
m_box.get(pkt); //getting packet from mailbox
$display("Driver::Packet Recived");
$display("Driver::Addr=%0d,Data=%0d\n",pkt.addr,pkt.data);
end
endtask
endclass
//-------------------------------------------------------------------------
// tbench_top
//-------------------------------------------------------------------------
module mailbox_ex;
generator gen;
driver dri;
mailbox m_box; //declaring mailbox m_box
initial begin
//Creating the mailbox, Passing the same handle to generator and driver,
//because same mailbox should be shared in-order to communicate.
m_box = new(); //creating mailbox
gen = new(m_box); //creating generator and passing mailbox handle
dri = new(m_box); //creating driver and passing mailbox handle
$display("------------------------------------------");
fork
gen.run(); //Process-1
dri.run(); //Process-2
join
$display("------------------------------------------");
end
endmodule
Simulator Output:
------------------------------------------
Packet::Packet Generated
Packet::Addr=3,Data=38
Generator::Packet Put into Mailbox
Driver::Packet Recived
Driver::Addr=3,Data=38
Packet::Packet Generated
Packet::Addr=118,Data=92
Generator::Packet Put into Mailbox
Driver::Packet Recived
Driver::Addr=118,Data=92
------------------------------------------
RESULT:
