COENG 7: Gate Level
Modelling
UNIT 2
Introduction
• Digital designs are typically done at a higher level of abstraction, such
as RTL.
• However, for smaller, deterministic circuits, it is often intuitive to use
gate-level modeling.
• Gate-level modeling involves gates and has a one-to-one relationship
between hardware schematics and Verilog code.
What is Gate Level Modeling?
• Gate-level modeling is a lower-level approach in digital design.
• It uses combinational elements like AND and OR gates.
• It provides a direct translation from a hardware schematic to Verilog
code.
Schematic Diagram
• A schematic diagram is a representation of a system's elements using
abstract, graphic symbols.
• It replaces realistic pictures with symbolic representations of
components.
• Schematic diagrams are widely used in electronics to visualize circuits.
Verilog as a Hardware Description Language
(HDL)
• Verilog is standardized as IEEE 1364.
• It is a hardware description language (HDL) used to model electronic
systems.
• Verilog is mainly used for design and verification of digital circuits at
the register-transfer level (RTL) of abstraction.
Primitives in Verilog
• Verilog provides support for basic logic gates known as primitives.
• These primitives can be instantiated like modules because they are
already predefined.
• Primitives simplify gate-level modeling by allowing easy integration of
basic logic gates into your Verilog code
Example Verilog Code
• Below is an example Verilog code for a 2-input AND gate:
module and2_gate (input A, B, output Y);
assign Y = A & B;
endmodule
Benefits of Gate-Level Modeling
• Gate-level modeling offers fine-grained control over circuit
implementation.
• It is essential for designing specific components within a larger
system.
• It allows for precise optimization of circuits when performance and
area constraints are critical.
Verilog Simulation of AND, OR,
and XOR Gates
AND, OR, and XOR Gate Primitives
• AND, OR, and XOR gates are essential logic gates.
• They take multiple scalar inputs and produce a single scalar output.
• We will implement these gates in Verilog.
Verilog Code - Gates Module
module gates(input a, b, output c, d, e);
and (c, a, b); // c is the AND gate output
or (d, a, b); // d is the OR gate output
xor (e, a, b); // e is the XOR gate output
endmodule
Verilog Code - Testbench (tb)
module tb;
reg a, b;
wire c, d, e;
integer i;
gates u0 (.a(a), .b(b), .c(c), .d(d), .e(e));
initial begin
{a, b} = 0;
$monitor("[T=%0t a=%0b b=%0b c(and)=%0b d(or)=%0b e(xor)=%0b", $time, a,
b, c, d, e);
for (i = 0; i < 10; i = i + 1) begin
#1 a <= $random;
b <= $random;
end
end
endmodule
Simulation Log
ncsim> run
[T=0 a=0 b=0 c(and)=0 d(or)=0 e(xor)=0
[T=1 a=0 b=1 c(and)=0 d(or)=1 e(xor)=1
[T=2 a=1 b=1 c(and)=1 d(or)=1 e(xor)=0
[T=4 a=1 b=0 c(and)=0 d(or)=1 e(xor)=1
[T=5 a=1 b=1 c(and)=1 d(or)=1 e(xor)=0
[T=6 a=0 b=1 c(and)=0 d(or)=1 e(xor)=1
[T=7 a=1 b=0 c(and)=0 d(or)=1 e(xor)=1
[T=10 a=1 b=1 c(and)=1 d(or)=1 e(xor)=0
ncsim: *W,RNQUIE: Simulation is complete.
Verilog Simulation of NAND, NOR,
and XNOR Gates
NAND, NOR, and XNOR Gate Primitives
• NAND, NOR, and XNOR gates are important logic gates that perform
the opposite operations of AND, OR, and XOR gates.
Verilog Code - Gates Module
module gates(input a, b, output c, d, e);
nand (c, a, b); // c is the NAND gate output
nor (d, a, b); // d is the NOR gate output
xnor (e, a, b); // e is the XNOR gate output
endmodule
Verilog Code - Testbench (tb)
module tb;
reg a, b;
wire c, d, e;
integer i;
gates u0 (.a(a), .b(b), .c(c), .d(d), .e(e));
initial begin
{a, b} = 0;
$monitor("[T=%0t a=%0b b=%0b c(nand)=%0b d(nor)=%0b e(xnor)=%0b", $time,
a, b, c, d, e);
for (i = 0; i < 10; i = i + 1) begin
#1 a <= $random;
b <= $random;
end
end
endmodule
Simulation Log
ncsim> run
[T=0 a=0 b=0 c(nand)=1 d(nor)=1 e(xnor)=1
[T=1 a=0 b=1 c(nand)=1 d(nor)=0 e(xnor)=0
[T=2 a=1 b=1 c(nand)=0 d(nor)=0 e(xnor)=1
[T=4 a=1 b=0 c(nand)=1 d(nor)=0 e(xnor)=0
[T=5 a=1 b=1 c(nand)=0 d(nor)=0 e(xnor)=1
[T=6 a=0 b=1 c(nand)=1 d(nor)=0 e(xnor)=0
[T=7 a=1 b=0 c(nand)=1 d(nor)=0 e(xnor)=0
[T=10 a=1 b=1 c(nand)=0 d(nor)=0 e(xnor)=1
ncsim: *W,RNQUIE: Simulation is complete.
Multiple Inputs
• These gates can also have more than two inputs, making them
versatile in various digital designs.
Verilog Code - Gates Module (Multiple Inputs)
module gates(input a, b, c, d, output x, y, z);
and (x, a, b, c, d); // x is the output
or (y, a, b, c, d); // y is the output
nor (z, a, b, c, d); // z is the output
endmodule
Verilog Code - Testbench (tb) - Multiple Inputs
module tb; for (i = 0; i <
reg a, b, c, d; 10; i = i + 1) begin
wire x, y, z; #1 a <=
$random;
integer i;
gates u0 (.a(a), .b(b), b <= $random;
.c(c), .d(d), .x(x), .y(y), c <= $random;
.z(z));
d <= $random;
initial begin
end
{a, b, c, d} = 0;
end
$monitor("[T=%0t
a=%0b b=%0b c=%0b d=%0b x=%0b endmodule
y=%0b z=%0b", $time, a, b, c, d,
x, y, z);
Simulation Log - Multiple Inputs
ncsim> run
[T=0 a=0 b=0 c=0 d=0 x=0 y=0 z=1
[T=1 a=0 b=1 c=1 d=1 x=0 y=1 z=0
[T=2 a=1 b=1 c=1 d=0 x=0 y=1 z=0
[T=3 a=1 b=1 c=0 d=1 x=0 y=1 z=0
[T=4 a=1 b=0 c=1 d=0 x=0 y=1 z=0
[T=5 a=1 b=0 c=1 d=1 x=0 y=1 z=0
[T=6 a=0 b=1 c=0 d=0 x=0 y=1 z=0
[T=7 a=0 b=1 c=0 d=1 x=0 y=1 z=0
[T=8 a=1 b=1 c=1 d=0 x=0 y=1 z=0
[T=9 a=0 b=0 c=0 d=1 x=0 y=1 z=0
[T=10 a=0 b=1 c=1 d=1 x=0 y=1 z=0
ncsim: *W,RNQUIE: Simulation is complete.
Verilog Simulation of Buffer (BUF)
and Inverter (NOT) Gates
Buffer (BUF) Gate
• The BUF gate, short for buffer, transfers the input value to the output
without any change in polarity.
• It has one scalar input and one scalar output.
Inverter (NOT) Gate
• The NOT gate, also known as an inverter, inverts the polarity of the
input signal.
• A 0 at its input becomes a 1, and vice versa.
• It has one scalar input and one scalar output.
Verilog Code - Gates Module
module gates(input a, b, output c, d);
buf (c, a, b); // c is the BUF gate output
not (d, a, b); // d is the NOT gate output
endmodule
Verilog Code - Testbench (tb)
module tb;
reg a, b;
wire c, d;
integer i;
gates u0 ( .a(a), .b(b), .c(c), .d(d));
initial begin
{a, b} = 0;
$monitor("[T=%0t a=%0b b=%0b c(buf)=%0b d(not)=%0b", $time, a, b, c, d);
for (i = 0; i < 10; i = i + 1) begin
#1 a <= $random;
b <= $random;
end
end
endmodule
Simulation Log
ncsim> run
[T=0 a=0 b=0 c(buf)=0 d(not)=1
[T=1 a=0 b=1 c(buf)=1 d(not)=0
[T=2 a=1 b=1 c(buf)=1 d(not)=0
[T=4 a=1 b=0 c(buf)=0 d(not)=1
[T=5 a=1 b=1 c(buf)=1 d(not)=0
[T=6 a=0 b=1 c(buf)=1 d(not)=0
[T=7 a=1 b=0 c(buf)=0 d(not)=1
[T=10 a=1 b=1 c(buf)=1 d(not)=0
ncsim: *W,RNQUIE: Simulation is complete.
Verilog Simulation of Bufif/Notif
Gates
Bufif/Notif Gates
• Bufif and Notif gates are variations of buffers and inverters that
include an additional control signal.
• These gates have a valid output only if the control signal is enabled;
otherwise, the output is in a high-impedance state.
• There are two versions: bufif1 and notif1 with a normal polarity of
control (indicated by a 1) and bufif0 and notif0 with an inverted
polarity of control (indicated by a 0).
Bufif1 Gate
• The bufif1 gate functions as a buffer with an enable signal.
• When the control signal is '1', it passes the input value to the output.
• When the control signal is '0', the output is in a high-impedance state.
Notif1 Gate
• The notif1 gate is an inverter with an enable signal.
• When the control signal is '1', it inverts the input value at the output.
• When the control signal is '0', the output is in a high-impedance state.
Notif1 Gate
module gates(input a, b, control, output c, d);
bufif1 (c, a, control, b); // bufif1 gate, c is the output
notif1 (d, a, control, b); // notif1 gate, d is the output
endmodule
Verilog Code - Testbench (tb)
module tb;
reg a, b, control;
wire c, d;
integer i;
gates u0 (.a(a), .b(b), .control(control), .c(c), .d(d));
initial begin
{a, b, control} = 0;
$monitor("[T=%0t a=%0b b=%0b control=%0b c(bufif1)=%0b d(notif1)=%0b", $time,
a, b, control, c, d);
for (i = 0; i < 10; i = i + 1) begin
#1 a <= $random;
b <= $random;
control <= $random & 1; // Control signal as random '0' or ‘1’
end
end
endmodule
Simulation Log
ncsim> run
[T=0 a=0 b=0 control=0 c(bufif1)=z d(notif1)=z
[T=1 a=0 b=1 control=1 c(bufif1)=0 d(notif1)=1
[T=2 a=1 b=1 control=0 c(bufif1)=z d(notif1)=z
[T=4 a=1 b=0 control=1 c(bufif1)=1 d(notif1)=0
[T=5 a=1 b=1 control=0 c(bufif1)=z d(notif1)=z
[T=6 a=0 b=1 control=1 c(bufif1)=0 d(notif1)=1
[T=7 a=1 b=0 control=0 c(bufif1)=z d(notif1)=z
[T=10 a=1 b=1 control=1 c(bufif1)=1 d(notif1)=0
ncsim: *W,RNQUIE: Simulation is complete.
Verilog Gate Level Examples
Multiplexer (2x1)
• A multiplexer (MUX) is a device that selects from multiple input
signals and forwards one to the output.
Verilog Code - 2x1 Multiplexer
module mux_2x1 (input a, b, sel, output out);
wire sel_n;
wire out_0;
not (sel_n, sel);
and (out_0, a, sel);
and (out_1, b, sel_n);
or (out, out_0, out_1);
endmodule
Simulation Log - 2x1 Multiplexer
ncsim> run
T=0 a=0 b=0 sel=0 out=0
T=1 a=0 b=1 sel=1 out=0
T=2 a=1 b=1 sel=1 out=1
T=3 a=1 b=0 sel=1 out=1
T=6 a=0 b=1 sel=0 out=1
T=7 a=1 b=1 sel=0 out=1
T=8 a=1 b=0 sel=0 out=0
T=9 a=0 b=1 sel=0 out=1
T=10 a=1 b=1 sel=1 out=1
ncsim: *W,RNQUIE: Simulation is complete.
Full Adder
• A full adder is a digital circuit that adds three one-bit binary numbers:
two operands and a carry bit.
• The result is the sum and a carry bit.
Verilog Code - Full Adder
module fa (input a, b, cin, output sum, cout);
wire s1, net1, net2;
xor (s1, a, b);
and (net1, a, b);
xor (sum, s1, cin);
and (net2, s1, cin);
xor (cout, net1, net2);
endmodule
Simulation Log - Full Adder
ncsim> run
T=0 a=0 b=0 cin=0 cout=0 sum=0
T=1 a=0 b=1 cin=1 cout=1 sum=0
T=2 a=1 b=1 cin=1 cout=1 sum=1
T=3 a=1 b=0 cin=1 cout=1 sum=0
T=6 a=0 b=1 cin=0 cout=0 sum=1
T=7 a=1 b=1 cin=0 cout=1 sum=0
T=8 a=1 b=0 cin=0 cout=0 sum=1
T=9 a=0 b=1 cin=0 cout=0 sum=1
T=10 a=1 b=1 cin=1 cout=1 sum=1
ncsim: *W,RNQUIE: Simulation is complete.
Decoder (2 to 4)
• A 2 to 4 decoder has two inputs, an enable pin, and four outputs.
• It switches on one of the four outputs based on the binary value of
the inputs and the enable signal.
Verilog Code - 2 to 4 Decoder
module dec_2x4 (input x, y, en, output a, b, c, d);
and (a, x, y, en);
and (b, x, !y, en);
and (c, !x, y, en);
and (d, !x, !y, en);
endmodule
Simulation Log - 2 to 4 Decoder
ncsim> run
T=0 x=0 y=0 en=1 a=0 b=0 c=0 d=0
T=1 x=0 y=1 en=1 a=0 b=1 c=0 d=0
T=2 x=1 y=1 en=1 a=1 b=0 c=0 d=0
T=3 x=1 y=0 en=1 a=0 b=0 c=1 d=0
T=6 x=0 y=1 en=1 a=0 b=1 c=0 d=0
T=7 x=1 y=1 en=1 a=1 b=0 c=0 d=0
T=8 x=1 y=0 en=1 a=0 b=0 c=1 d=0
T=9 x=0 y=1 en=1 a=0 b=1 c=0 d=0
T=10 x=1 y=1 en=1 a=1 b=0 c=0 d=0
ncsim: *W,RNQUIE: Simulation is complete.
Encoder (4 to 2)
• A 4 to 2 encoder converts multiple inputs into a binary code at its
output.
• It produces a 2-bit code based on the active input line.
Verilog Code - 4 to 2 Encoder
module enc_4x2 (input a, b, c, d, output x, y);
or (x, b, d);
or (y, c, d);
endmodule
Simulation Log - 4 to 2 Encoder
ncsim> run T=10 a=1 b=0 c=0 d=1 x=1 y=1
T=0 a=0 b=0 c=0 d=0 x=0 y=0 T=11 a=1 b=0 c=1 d=0 x=0 y=1
T=2 a=0 b=0 c=0 d=1 x=1 y=1 T=12 a=1 b=0 c=1 d=1 x=1 y=1
T=3 a=0 b=0 c=1 d=0 x=0 y=1 T=13 a=1 b=1 c=0 d=0 x=1 y=0
T=4 a=0 b=0 c=1 d=1 x=1 y=1 T=14 a=1 b=1 c=0 d=1 x=1 y=1
T=5 a=0 b=1 c=0 d=0 x=1 y=0 T=15 a=1 b=1 c=1 d=0 x=1 y=1
T=6 a=0 b=1 c=0 d=1 x=1 y=1 T=16 a=1 b=1 c=1 d=1 x=1 y=1
T=7 a=0 b=1 c=1 d=0 x=1 y=1 T=17 a=0 b=0 c=0 d=0 x=0 y=0
T=8 a=0 b=1 c=1 d=1 x=1 y=1 ncsim: *W,RNQUIE: Simulation
T=9 a=1 b=0 c=0 d=0 x=0 y=0 is complete.
