goldfinch_tb_top.u_goldfinch_top.u_goldfinch_uc_top.u_uc.
u_uc_sifive_peripherals_wr
apper.u_uart_top.pclk
slave
0x21408004 0x8050 W static address valid, static address = 0x50
0x2a010074 0xC000 W SLV_INST_ID = C
0x2a010084 0x7405 W MXDS_MAX_WR_SPEED = userdefined
//MXDS_MAX_RD_SPEED = 2MHz MXDS_CLK_DATA_TURN= 8ns
0x2a010070 0x603C W SLV_MIPI_MFG_ID = 0x3A02
0x2a010074 0xb3b8c5f0 W SLV_PID_DCR = 5F0 SLV_INST_ID = C SLV_PART_ID= B3B8
0x2a010078 0x4e00 W SLV_CHAR_CTRL, DCR = 4e
0x2a010078 0x4e01 W SLV_CHAR_CTRL, DCR = 4e max data speed limit =
1
0x2a010000 0x00 W disable
0x2a010004 0x378050 W static address valid, static address = 0x50
Dynamic_address= 0x37
0x2a010004 0x8050 R static address valid, static address = 0x50
0x2a010008 0x140a4 R /raead
0x2a010010 0x0 R //RESPONSE_QUEUE_PORT //read for no of commands
written
0x2a01001C 0x306 W CMD_EMPTY_BUF_THLD = 06 -- for interrupt
RESP_BUF_THLD = 03 --
0x2a010020 0x04020403 W DATA_BUFFER_THLD_CTRL for interrupts
0x2a010034 0x0 W //RESET_CTRL = 0
0x2a010038 0x0 W SLV_EVENT_STATUS = 0
0x2a01004C 0x10 R QUEUE_STATUS_LEVEL //readonly
0x2a010050 0x40 R DATA_BUFFER_STATUS_LEVEL //readonly
0x2a010054 0x0 W PRESENT_STATE //readonly
0x2a010058 0x0 W CCC_DEVICE_STATUS //readonly
0x2a010070 0x603C W SLV_MIPI_MFG_ID = 0x3A02
0x2a010074 0xb3b8c5f0 W SLV_PID_DCR = 5F0 SLV_INST_ID = C SLV_PART_ID= B3B8
0x2a0100D4 0x15300BE W BUS_FREE_AVAIL_TIMING -- BUS_AVAILABLE_TIME == 1530
0x2a0100D4 0x1530000 R Read
0x2a0100D8 0x17672 W BUS_IDLE_TIMING = 0x17672
0x2a0100E0 0x3130312a R I3C_VER_ID - read
0x2a010040 0x1b5b W INTR_STATUS_EN = all interrupts enabled
0x2a010044 0x1b5b W INTR_STATUS_signal = all interrupts enabled
0x2a010000 0x0 W
sleep
0x2a010000 0x80000000 W Enable controller
msater
sleep 3 clocks
0x2a000008 0x10a1 r
0x2a000010 0x0 r
0x2a000024 0x00000000 w
0x2a00001C 0xe040a w QUEUE_THLD_CTRL -- CMD_EMPTY_BUF_THLD -- 0xa
RESP_BUF_THLD -- 0x04 IBI_STATUS_THLD -- e0
0x2a000020 0x02010502 w DATA_BUFFER_THLD_CTRL TX_EMPTY_BUF_THLD -- 8
locations RX_BUF_THLD -- 64 loctions TX_START_THLD -- 4 location RX_START_THLD -- 8
locations
0x2a000024 0x02 w nothing reserved bit
0x2a000030 0x0 w IBI_SIR_REQ_REJECT 0 - ACK the SIR Request
sleep 5 clocks
0x2a00004c 0x00000 w
0x2a000034 0x0 w reset control IBI_QUEUE_RST RX_FIFO_RST TX_FIFO_RST
RESP_QUEUE_RST CMD_QUEUE_RST SOFT_RST
0x2a000034 0x10 r
0x2a000050 0x00 r
0x2a0000B0 0x683c r
0x2a000040 0x23f w INTR_STATUS_EN enable all interrupts
0x2a000044 0x23f w INTR_SIGNAL_EN enable all interrupts
0x2a000004 0x80550000 w DEVICE_ADDR DYNAMIC_ADDR_VALID -- 1 DYNAMIC_ADDR =
0x55
0x2a0000b4 0xa0028 w SCL_I3C_OD_TIMING open drain timing I3C_OD_LCNT --
0x28 I3C Open Drain High Count -- 0xA
0x2a0000b8 0x80008 w SCL_I3C_PP_TIMING I3C Push Pull Low Count -- 0x8 I3C
Push Pull High Count -- 0x08
0x2a0000bC 0xe8017a w SCL_I2C_FM_TIMING fast mode timing I2C Fast Mode Low
Count - 0x17a I2C Fast Mode High Count - 0xe80
0x2a0000C0 0xff00f6 w SCL_I2C_FMP_TIMING fastmode plus timing I2C Fast Mode
Plus Low Count - f6 I2C Fast Mode Plus high Count - 0xff
0x2a0000C8 0x5c091f11 w SCL_EXT_LCNT_TIMING SCL Extended Low Count Timing
Register I3C_EXT_LCNT_1 - 0x11 I3C_EXT_LCNT_2 - 0xf1 I3C_EXT_LCNT_3 - 0x09
I3C_EXT_LCNT_4 - 0x5c
0x2a0000CC 0x30000003 w SCL Termination Bit Low count Timing Register I3C
Read Termination Bit Low coun - STOP HOLD Count - b'11
0x2a0000D0 0x50000 w SDA Hold and Mode Switch Delay Timing Register 0x5
0x2a0000D4 0x16 w Bus Free Timing Register I3C Bus Free Count Value --
0x16
0x2a0000D8 0x55 w I3CM_BUS_IDLE_TIMING -- 0x55
0x2a0000E0 0x3130312a r I3C_VER_ID
0x2a0000E4 0x6c633030 r I3C_VER_TYPE
0x2a0000E8 0x12355 r QUEUE_SIZE_CAPABILITY TX_BUF_SIZE - 64 words
RX_BUF_SIZE - 64 CMD_BUF_SIZE -16 RESP_BUF_SIZE - 8 IBI_BUF_SIZE - 4
0x2a00005C 0x120380 r Pointer for Device Address Table Registers
P_DEV_ADDR_TABLE_START_ADDR - 0x380 DEV_ADDR_TABLE_DEPTH - 0x12
0x2a000000 0x80000001 w Device Control Register Enable
0x2a000060 0x48200 r Pointer for Device Characteristics Table
DEV_CHAR_TABLE_DEPTH 0x48 P_DEV_CHAR_TABLE_START_ADDR 0x200
0x2a00005C 0x120380 r
0x2a000380 0xD50050 w Device Address Table of Device1 Device Static Address
- 0x50 DEV_DYNAMIC_ADDR - - 0xd5
0x2a000384 0xc10051 w Device Address Table of Device1 Device Static Address
- 0x51 DEV_DYNAMIC_ADDR - - 0xC1
0x2a00003C 0x9 r Interrupt Status Register TRANSFER_ERR_STS - 1
0x2a00000C 0x44208103 w
sleep more
0x2a000000 0xC0000001 w
0x2a00000C 0x44208103 w
sleep more
0x2a00000C 0x04408383 w
0x2a000054 0x400 R //read present state
slave
0x2a01000C 0xC0010 W
0x2a010014 0x11111111 W
0x2a010014 0x22222222 W
0x2a010014 0x33333333 W
sleep
master
0x2a00000C 0xC2D01 w
