Brij Patel 20BECEG093 200410107126

SARDAR VALLABHBHAI PATEL INSTITUTE

OF TECHNOLOGY, VASAD

LABORATORY MANUAL
DIGITAL FUNDAMENTALS
SUBJECT CODE: 3130704
Computer Engineering Department
B.E. 3rd SEMESTER

Name: Patel Brij Kumar Jagdish Bhai

Enrollment no.: 200410107126

Student ID: 20BECEG093

Batch: C

Year: 2021-2022

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LOGISIM

* Feature Of Logisim.

* Tools in Logisim

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➢ From using this gates tools we can draw a

different type of gates circuits easily .

➢ Here we Have all type of gate like

and,or,not,nand,nor,nand etc…

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➢ From above picture we can see that logisim

also provides a various other like wiring , plexers
,arithmetic,memory ,input / output , base .

➢ On top of the screen left side clicking by

clicking edit option we get option for saving
file,open file etc….

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➢ Here we can see that clicking on project we

get very useful option for perfoming any task
on that circuit which created by us as shown in
picture .

➢ At last we can consider that logisim is very

useful because Logisim is an educational tool for
designing and simulating digital logic circuits. ... With
the capacity to build larger circuits from smaller
subcircuits, and to draw bundles of wires with a single
mouse drag, Logisim can be used (and is used) to design
and simulate entire CPUs for educational purposes.

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All THE STANDARD GATES

AIM :- To study and verify the truth table of

logic gates.
Theory : - The basic logic gates are the
building blocks of more complex logic circuits.
These logic gates perform the basic Boolean
functions, such as AND, OR, NAND, NOR,
Inversion, Exclusive-OR, Exclusive-NOR. Fig.
below shows the circuit symbol, Boolean
function, and truth. It is seen from the Fig that
each gate has one or two binary inputs, A
and B, and one binary output, C. The small
circle on the output of the circuit symbols
designates the logic complement. The AND,
OR, NAND, and NOR gates can be extended
to have more than two inputs. A gate can be
extended to have multiple inputs if the binary
operation it represents is commutative and
associative.
➢These basic logic gates are implemented
as small-scale integrated circuits (SSICs) or
as part of more complex medium scale
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(MSI) or very large-scale (VLSI) integrated

circuits. Digital IC gates are classified not
only by their logic operation, but also the
specific logiccircuit family to which they
belong. Each logic family has its own basic
electronic circuit upon which more
complex digital circuits and functions are
developed. The following logic families are
the most frequently used.

➢TTL Transistor-transistor logic

➢ECL Emitter-coupled logic
➢MOS Metal-oxide semiconductor
➢CMOS Complementary metal-oxide
semiconductor

➢TTL and ECL are based upon bipolar

transistors. TTL has a popularity among
logic families. ECL is used only in systems
requiring high-speed operation. MOS and
CMOS, are based on field effect transistors.
They are widely used in large scale
integrated circuits because of their high
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component density and relatively low

power consumption. CMOS logic
consumes far less power than MOS logic.
There are various commercial integrated
circuit chips available. TTL ICs are usually
distinguished by numerical designation as
the 5400 and 7400 series.

➢Name of gate :- There are three standard

logic gates.

➢AND gate
➢OR gate
➢NOT gate

Description :-
1. Check the components for their working.
2. Insert the appropriate IC into the IC base.
3. Make connections as shown in the circuit
diagram.

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4. Provide the input data via the input

switches and observe the output on output
LEDs

➢Symbol of gate:-
1. AND gate :

2. OR gate :

3. NOT gate:

➢Expression of gate :-

1. And gate :-
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A.B = (c) output

2. OR gate :-
A+B = (c) output

3. Not gate :-
_
A = (c) output

➢Truth Table :-

1. And gate:-

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2. OR gate :-

3. NOT gate:-

➢Logisim Implemented Circuit:-

1. (A+B).C

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2. (A.B.C)

3. (A+B+C)

4. (A.B)’ + (C.D)’

5. (A+B).(C+D)

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Practical 3

AIM : To design and implementation using NAND gate.

THEORY: Boolean algebra is a branch of mathematical logic,
where the variables are either true (1) or false (0).In order to
construct NOT, AND, OR, XOR gates from NAND gates only, we
need to be familiar with the following boolean algebra laws:

1.Involution Law
2.Idempotency (Idempotent) law
3.DeMorgan's Law
Name of Gate: NAND Gate
Description in detail : To realize why NAND gate is known as the universal
gate by implementation of :
a. NOT using NAND
b. AND using NAND
c. OR using NAND
d. XOR using NAND
Symbol of gate:
Nand Gate

NOT using NAND

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AND using NAND

OR using NAND

NOR using NAND

Expression of gate:
Expression of NAND gate is

Truth table

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Logisim implemented circuit

1.(A+B)(C+D)

2.A’B’C’

3.A’B’+(C+D)’

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4.(A+B)C

5.(AB)’+(A’+B’)

6.(A+B)(C+D)(E+F)

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PRACTICAL 4

AIM: To design and implementation using NOR gate.

THEORY: Boolean algebra is a branch of mathematical logic,
where the variables are either true (1) or false (0).In order to
construct NOT, AND, OR, XOR gates from NOR gates only, we
need to be familiar with the following boolean algebra laws:
1.Involution Law
2.Idempotency (Idempotent) law
3.DeMorgan's Law

NAME OF GATE: NOR Gate

DESCRIPTION IN DETAIL: To realize why NOR gate is known as
the universal gate by implementation of :
a. NOT using NOR
b. AND using NOR
c. OR using NOR
d. XOR using NOR
SYMBOL OF NOR GATE:

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Expression of gate:
Expression of NOR gate is

Truth table

Logisim implemented circuit

1)(A+A)’

2)[(A+B)’]’

3)(A’+B’)’

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4)(AB)’

5)A’B+AB’

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PRACTICAL 5
HALF ADDER AND FULL ADDER

AIM: TO DESIGN AND STUDY THE HALF ADDER & FULL

ADDER.
THEORY: The Adder circuit is a combinational logic
circuit. There are two types of adder circuits:
1)Half Adder &
2)Full Adder

1) Half adder
A combinational circuit that performs the addition of two
bits is called a half-adder. This circuit needs two binary
inputs and two binary outputs. The input variables
produce the sum and the carry.

Truth Table
X Y C S
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0

Boolean Expression:

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The simplified Boolean expression for the two outputs

obtained from the truth table.
S = x’y + xy’
C = xy

S = x  y and C = xy

Circuit

Observation Table

2)FULL ADDER

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A combinational circuit that performs the addition of

three bits is called a Full-adder. This consists of three inputs
and two outputs.

Truth Table
X Y Z C S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

Boolean Expression:
The simplified Boolean expressions:
For S:
 S = x’y’z + x’yz’ + xy’z’ +xyz
For C:
 C = xy + xz + yz
Implementation of a Full-adder with two half adders
and an OR gate:
S = x’y’z + x’yz’ + xy’z’ + xyz
= x’ (y’z+yz’) + x (y’z’+yz)

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= x’ (y’z+yz’) + x (y’z+yz’)’
= x’ (y  z) + x (y  z)’
=xyz
S=xyz

C = x’yz +xy’z +xyz’ +xyz

= (x’y + xy’) z + xy (z’+z)
= (x  y) z + xy
 C = (x  y) z + xy

Circuit

Observation Table

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PRACTICAL 6
HALF & FULL SUBTRACTOR

AIM: To design and study the half subtractor and full

subtractor.
THEORY: The subtractor circuit is also a combinational
logic circuit. There are two types of subtractor circuits:

1) Half subtractor and

2) Full subtractor

HALF SUBTRACTOR:
A half subtractor is a combinational circuit that subtracts
two bits and produces their difference. It also has an
output to specify if a 1 has been borrowed. The half
subtractor needs two inputs and two outputs (Difference
and Borrow).

TRUTH TABLE
X Y B D
0 0 0 0
0 1 1 1
1 0 0 1
1 1 0 0

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Boolean Expression:
The simplified Boolean expressions for the two outputs
obtained from the truth table.
D = x’y + xy’
B = x’y
D = x  y and B = x’y

Circuit

Observation Table

FULL SUBTRACTOR:

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A full subtractor is a combinational circuit that performs

the subtraction between two bits, taking into account
that a 1 may have been borrowed by a lower significant
stage. This circuit has three inputs and two outputs.

TRUTH TABLE
X Y Z B D
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 1 0
1 0 0 0 1
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

Boolean Expression:
The simplified Boolean expressions:
For D
 D = x’y’z + x’yz’ + xy’z’ +xyz
For B
 B = x’y + x’z + yz
Implementation of a Full-subtractor with two half
subtractors and an OR gate:

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D = x’y’z + x’yz’ + xy’z’ + xyz

= x’ (y’z+yz’) + x (y’z’+yz)
= x’ (y’z+yz’) + x (y’z+yz’)’
= x’ (y  z) + x (y  z)’
=xyz
D=xyz

B= x’y’z +x’yz’ +x’yz +xyz

= z (x’y’+xy) + x’y (z’+z)
= z (x’y’+xy) + x’y
= z (x  y)’ + x’y
 B = (x  y)’ z + x’y

Circuit

TRUTH TABLE

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PRACTICAL 7
CODE CONVERTERS

AIM: To design and study the Code Converters:

a) Binary to Gray Code Converter
b) Gray to Binary Code Converter

APPARATUS: [1] Digital Trainer

[2] Hook up wires
[3] TTL IC 7486

THEORY: A code converter is a combinational circuit that makes

the two systems compatible even though each uses a different
binary code. Using code converters between two systems of
different codes, we can use the output of one system as input to
another.

[A] BINARY TO GRAY CODE CONVERTER

Truth Table:

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Boolean Expression:

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CIRCUIT

[B] GRAY TO BINARY CODE CONVERTER

TRUTH TABLE

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BOOLEAN EXPRESSION

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CIRCUIT

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PRACTICAL 8
IMPLEMENTATION OF MULTIPLEXERS

AIM:- To study the 8x1 Multiplexer.

APPARATUS:- 1. Digital Trainer
2. Hook up wires
3. IC 74151 and IC 74138
THEORY:-
MULTIPLEXER:
Multiplexing means transmitting a large number of
information units over a smaller number of channels or
lines.
A digital multiplexer is a combinational circuit that selects
binary information from one of many input lines and
directs it to a single output line.
The selection of a particular input line is controlled by a
set of selection lines. Normally there are 2n input lines and
n selection lines whose bit combinations determine which
input is selected.
A multiplexer is also called a data selector since it selects
one of the many inputs and steers the binary information
to the output line.
The size of a multiplexer is specified by the number 2n of
its input lines and the single output line. It is then implied

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that it also contains n selection lines. A multiplexer is

often abbreviated as MUX.

PROCEDURE:
For 8X1 Multiplexer:
1. Fix the IC 74151 on Digital trainer breadboard so that
each pin is in different hole and no two pins are
connected.
2. Apply Vcc (+5Volts) and Ground to IC using hook up
wires through trainer board.
3. Connect the select lines and strobe pin of the IC to the
input switches.
4. Then connect the selected data input pins of IC to the
switches.
5. Connect the output pins of the IC to the LEDs.
6. Observe the output and verify the Truth table by giving
different inputs.

CIRCUIT DIAGRAM:

PTO
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8X1 Multiplexer Logic Diagram

Truth Table

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PRACTICAL 9
IMPLEMENTATION OF DEMULTIPLEXER

AIM: To study the 1X8 Demultiplexer.

APPARATUS: 1. Digital Trainer
2. Hook up wires
3. IC 74151 and IC 74138
THEORY:
DEMULTIPLEXER
A Demultiplexer is a circuit that receives information on a
single line and transmits this information on one of 2n
possible output lines. The selection of a specific output line
is controlled by the bit values of n selection lines. A
decoder with an enable input can function as a
Demultiplexer, if the enable line is taken as a data input
line and input lines of decoder are taken as the selection
lines.
PROCEDURE:
For 1X8 Demultiplexer:
1. Fix the IC 74138 on Digital trainer breadboard so that
each pin is in different hole and no two pins are
connected.
2. Apply Vcc (+5Volts) and Ground to IC using hook up
wires through trainer board.

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3. From Enables G1, G2 and G3, short G2 and G3 and

connect with input switch. Apply logic 0 to G2 and G3
using switch.
4. Use Enable G1 as a data input and connects to the
input switch. Also connect the select lines of the IC to the
input switches.
5. Connect the output pin of the IC to the LED.
6. Observe the output and verify the Truth table by giving
different inputs.
CIRCUIT DIAGRAM

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TRUTH TABLE

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PRACTICAL 10
Implementation of SR flip flop, D flip flop and JK flip
flop

AIM: To study and verify the Different Flip-Flops.(D,JK and

T Flip-Flops).
APPARATUS: 1. Digital Trainer
2. Hook up wires
3. IC 7474 and IC 7476
THEORY:
A sequential circuit consists of a combinational circuit to
which memory elements are connected to form a
feedback path. The memory elements are devices
capable of storing binary information within them.
The memory elements used in clocked sequential circuits
are called Flip-Flops. These circuits are binary cells
capable of storing one bit of information. A Flip-Flop
circuit has two outputs, one for the normal value and one
for the complement value of the bit stored in it. The major
differences among various types of Flip-flops are in the
number of inputs they possess and in the manner in which
the inputs affect the binary state.
PROCEDURE:

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For D Flip-Flop
1. Apply Vcc (+5Volts) and Ground to IC using hook up
wires through trainer board. 2. From the dual D Flip-flop in
the IC, select one D Flip-flop and connect input D, clear
and preset pins to the input switches. 3. Connect outputs
of that Flip-Flop in the IC to the LED. 4. From the function
generator or manually (From Trainer Board) apply clock
pulse to the clock pin of the Flip-Flop. 5. Verify the table of
D Flip-Flop giving different input conditions.
For JK and T Flip-Flop
1. Apply Vcc (+5Volts) and Ground to IC using hook up
wires through trainer board. 2. From the dual JK Flip-flop in
the IC, select one JK Flip-flop and connect inputs J, K,
clear and preset pins to the input switches. 3. Connect
outputs of that Flip-Flop in the IC to the LED. 4. From the
function generator or manually (From Trainer Board)
apply clock pulse to the clock pin of the Flip-Flop. 5. Verify
the table of JK Flip-Flop giving different input conditions.
6. For T Flip-Flip, first short J and K inputs and make single
input that is input T. Then the above steps and verify the
table for T Flip-Flop.
[1] D Flip-Flop:
The D Flip-Flop receives the designation from its ability to
transfer “data” into a Flip-Flop. The logic diagram (with
NAND gates), characteristics table and symbol for a
clocked D Flip-Flop are shown below:
CIRCUIT DIAGRAM

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TRUTH TABLE

SYMBOL

[2] JK Flip-Flop:

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Many digital systems are constructed entirely with JK Flip-

Flops because they are the most versatile available. JK
Flip-Flop is used for any general application. A JK Flip-Flop
is a refinement of the RS Flip-Flop in that the indeterminate
state of the RS type is defined in the JK type. When J=1
and K=1, the Flip-Flop toggles i.e. goes to the opposite
state. The logic diagram, characteristic table and symbol
for a clocked JK Flip-Flop are shown below:
CIRCUIT DIAGRAM

TRUTH TABLE

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SYMBOL

[3] T Flip-Flop:
The T Flip-Flop is a single input version of the JK Flip-Flop.
The T Flip-Flop is obtained from a JK type if both inputs are
tied together. The designation T comes from the ability of
the Flip-Flop to “toggle” or change state. The symbol,
characteristic table and equation of the T Flip Flop are
shown here:
TRUTH TABLE

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SYMBOL

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PRACTICAL-11
SHIFT REGISTER

AIM: To study the Shift Register.

THEORY:
A register is a group of binary cells suitable for holding binary
information. A group of Flip-Flops constitutes a register. Since
each Flip-Flop is a binary cell capable of storing one bit of
information. An n-bit register has a group of n Flip-Flops and is
capable of storing any binary information containing n bits.
A register capable of shifting its binary information either to the
right or to the left is called a shift register. The logical
configuration of a shift register consists of a chain of Flip-Flops
connected in cascade, with the output of one Flip-Flop
connected to the input of the next Flip-Flop. All Flip-Flops
receive a common clock pulse that causes the shift from one
stage to the next.
The simplest possible shift register is one that uses only Flip-Flops
as shown below:
Q1 Q2 Q3 Q4

Serial Q D Q Serial
Input D Q D Q D Output

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Above register shifts its contents to the right. A register that can shift in only
one direction is called a unidirectional shift register and a register capable of
shifting both right and left is called a bi-directional shift register.
The transfer of new information into a register is referred to as loading the
register. If all the bits of the register are loaded simultaneously with a single
clock pulse, we say that the loading is done in parallel. If a parallel-load
capability is added to a shift register, then data entered in parallel can be
taken out in serial fashion by shifting the data stored in the register.
If the register has both shift and parallel-load capabilities, it is called a shift
register with parallel load or universal shift register.

RIGHT SHIFT REGISTER

Observation Table

Observation Table

CLEA CLOC A B QA QB ….. QH

R K
0 X X X 0 0 …… 0

1 I L X L QA ……QG

1 I X L L QA ……QG

1 I H H H QA ……QG

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..
PRACTICAL-12

Design and implement binary counter

AIM: To study the function of binary

THEORY:

One common requirement in digital circuits is counting, both forward and backward.
Digital clocks and watches are everywhere, timers are found in a range of appliances from
microwave ovens to VCRs, and counters for other reasons are found in everything from
automobiles to test equipment.

Although we will see many variations on the basic counter, they are all fundamentally very
similar. The demonstration below shows the most basic kind of binary counting circuit.

In the 4-bit counter to the right, we are using edge-triggered master-slave flip-flops similar to those in
the Sequential portion of these pages. The output of each flip-flop changes state on the falling edge (1-
to-0 transition) of the T input.

The count held by this counter is read in the reverse order from the order in which the flip -flops are
triggered. Thus, output D is the high order of the count, while output A is the low order. The binary
count held by the counter is then DCBA, and runs from 0000 (decimal 0) to 1111 (decimal 15). The
next clock pulse will cause the counter to try to increment to 10000 (decimal 16). However, that 1 bit
is not held by any flip-flop and is therefore lost. As a result, the counter actually reverts to 0000, and
the count begins again.

..
In future pages on counters, we will use a different input scheme, as shown to the left. Instead
of changing the state of the input clock with each click, you will send one complete clock pulse to the
counter when you click the input button. The button image will reflect the state of the clock pulse,
and the counter image will be updated at the end of the pulse. For a clear view without taking excessive
time, each clock pulse has a duration or pulse width of 300 ms (0.3 second). The demonstration system
will ignore any clicks that occur within the duration of the pulse
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A major problem with the counters shown on this page is that the individual flip -flops do not all
change state at the same time. Rather, each flip-flop is used to trigger the next one in the series.
Thus, in switching from all 1s (count = 15) to all 0s (count wraps back to 0), we don't see a
smooth transition. Instead, output A falls first, changing the apparent count to 14. This triggers
output B to fall, changing the apparent count to 12. This in turn triggers output C, which leaves
a count of 8 while triggering output D to fall. This last action finally leaves us with the correct
output count of zero. We say that the change of state "ripples" through the counter from one flip-
flop to the next. Therefore, this circuit is known as a "ripple counter."

This causes no problem if the output is only to be read by human eyes; the ripple effect
is too fast for us to see it. However, if the count is to be used as a selector by other digital circuits
(such as a multiplexer or demultiplexer), the ripple effect can easily allow signals to get mixed
together in an undesirable fashion. To prevent this, we need to devise a method of causing all of
the flip-flops to change state at the same moment. That would be known as a "synchronous
counter" because the flip-flops would be synchronized to operate in unison. That is the subject
of the next page in this series.

DM7490A: Decade and Binary Counter

General Description

The DM7490A monolithic counter contains four master slave flip-flops and additional gating to provide
a divide-by two counter and a three-stage binary counter for which the count cycle length is divide-by-
five. The counter has a gated zero reset and also has gated set-to-nine inputs for use in BCD nine’s
complement applications. To use the maximum count length (decade or four-bit binary), the B input is
connected to the QA output. The input count pulses are applied to input A and the outputs are as
described in the appropriate Function Table. A symmetrical divide-by-ten count can be obtained from
the counters by connecting the QD output to the A input and applying the input count to the B input
which gives a divide-by-ten square wave at output QA.

Features
[1 ] Typical power dissipation 145 mW
[2] Count frequency 42 MHz

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CONCLUSION:

In this experiment we learned about the decade counters and their uses in our day to day life.

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